Complementary organic compute-in-memory nand gate circuit and preparation method thereof

Abstract

The application discloses a complementary organic memory and computing integrated NOT gate circuit and a preparation method thereof, and belongs to the technical field of organic integrated circuits. IN ; the source electrode on the p-type organic semiconductor layer is connected with the drain electrode on the n-type organic semiconductor layer, and serves as an output terminal V OUT . The NOT gate circuit of the application increases the data storage function on the basis of performing the NOT logic operation; that is, the result of the NOT logic operation can be stored in the gate circuit persistently after the input signal is removed, so that the working energy consumption can be reduced obviously; and the material used is mainly organic / polymer material, so that the process is simple, the low-temperature preparation is suitable, the cost is low, and the flexible application is suitable.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of organic integrated circuits, and particularly relates to a complementary organic NOT gate circuit integrating data storage and logic operation and a preparation method thereof. BACKGROUND

[0002] Modern computers are based on the Von Neumann architecture; in which, the arithmetic unit and the memory are two separate units. With the continuous reduction of transistor size, the time and energy required for frequent data exchange between the arithmetic unit and the memory have gradually become a bottleneck problem restricting the performance improvement of computers, i.e., the so-called Von Neumann bottleneck. In recent years, developing memory-compute integrated circuits, i.e., integrating data storage and logic operation in the same unit chip, is considered as one of the effective strategies to solve the Von Neumann bottleneck.

[0003] Gate circuits are the basic units for building various functional integrated circuits. However, traditional NOT, AND, OR, NAND, NOR, etc. gate circuits can only perform corresponding logic operations. In recent years, researchers have reported an increasing number of memory-compute integrated gate circuits by connecting transistor memory with photoelectric or pure electrical mode writing and erasing to conventional transistors (or resistors) [Nanotechnology, 2013, 24, 205202; Nature 2020, 587, 72.; Adv. Funct. Mater. 2020, 30, 2002506; IEEE Electron Device Lett., 2022, 43, 1902; ACS Nano 2023, 17, 6095; IEEE Electron Device Lett., 2023, 44, 610; etc.]. These reported memory-compute integrated gate circuits can not only realize NOT, NAND, NOR, etc. logic operations, but also realize data storage functions; they lay a foundation for the development of memory-compute integrated circuits and provide an effective strategy to solve the Von Neumann bottleneck. However, these reported memory-compute integrated gate circuits are composed of different types of semiconductor components, and their architecture is complex; the main materials used are inorganic semiconductors and inorganic insulating materials, and the equipment required for the preparation process is expensive, the process is complicated, and the energy consumption is high.

[0004] Compared with inorganic transistor memory, organic transistor memory has the innate advantages of wide material sources, low-temperature preparation, solution processing, and good mechanical flexibility. Based on organic transistor memory, the preparation of memory and computing integrated gate circuit can greatly simplify the process, save energy consumption, reduce production cost, and more easily develop flexible memory and computing integrated circuits that can be statically and dynamically bent, which can be widely used in price tags, Internet of Things, biological medicine, wearable electronics and other fields. Memory and computing integrated NAND gate circuit is one of the basic units of memory and computing integrated gate circuit. Compared with other structures of memory and computing integrated NAND gate circuit, the complementary memory and computing integrated NAND gate circuit has more significant advantages in energy consumption. The complementary organic memory and computing integrated NAND gate circuit needs p-type and n-type organic transistor memory. So far, all reported organic transistor memories are p-type working mode; and n-type organic transistor memory has not been reported. The complementary organic memory and computing integrated NAND gate circuit composed of a p-type organic transistor memory and an n-type organic transistor memory has not been reported. SUMMARY

[0005] In view of the Von Neumann bottleneck problem faced by the conventional gate circuit of the prior art, and the above-mentioned problems in the framework, preparation process and procedure of the memory and computing integrated gate circuit of the prior art, the present application provides a complementary organic memory and computing integrated NAND gate circuit and a preparation method thereof. The complementary organic memory and computing integrated NAND gate circuit is composed of a p-type organic transistor memory and an n-type organic transistor memory connected in series. Compared with the existing conventional NAND gate circuit, the complementary organic memory and computing integrated NAND gate circuit of the present application increases the data storage function on the basis of performing non-logic operation; that is, after the input signal is removed, the result of non-logic operation can be stored in the gate circuit persistently. Compared with other existing memory and computing integrated NAND gate circuits, the complementary organic memory and computing integrated NAND gate circuit of the present application works in a complementary mode, which can significantly reduce the working energy consumption; and the materials used are mainly organic / polymer materials, which have the advantages of simple process, low-temperature preparation, low cost, and suitability for flexible applications.

[0006] The present application is realized by the following technical solutions:

[0007] A complementary organic storage and calculation integrated NOT gate circuit, comprising a substrate 1 and a gate electrode 2, a ferroelectric gate polymer gate dielectric layer 3, an interface passivation layer 4 and an organic semiconductor layer located thereon, wherein the organic semiconductor layer comprises a p-type organic semiconductor layer 5 and an n-type organic semiconductor layer 6, and a source electrode and a drain electrode are arranged on the p-type organic semiconductor layer 5 and the n-type organic semiconductor layer 6; wherein the gate electrode 2, the ferroelectric gate polymer gate dielectric layer 3, the interface passivation layer 4, the p-type organic semiconductor layer 5 and the drain electrode 7 and the source electrode 8 located thereon constitute a p-type organic transistor memory, and the gate electrode 2, the ferroelectric gate polymer gate dielectric layer 3, the interface passivation layer 4, the n-type organic semiconductor layer 6 and the drain electrode 9 and the source electrode 10 located thereon constitute an n-type organic transistor memory; the p-type organic transistor memory and the n-type organic transistor memory are connected in series mode, and share one gate electrode 2 as an input terminal V IN ; the source electrode 8 on the p-type organic semiconductor layer is connected with the drain electrode 9 on the n-type organic semiconductor layer as an output terminal V OUT ; the drain electrode 7 on the p-type organic semiconductor layer is connected with a working voltage V DD , and the source electrode 10 on the n-type organic semiconductor layer is as a ground terminal GND.

[0008] Further, the material of the substrate 1 is one or more of glass, silicon, polyethylene terephthalate, polyethylene naphthalate or polyethersulfone.

[0009] Further, the material of the drain electrode, the source electrode and the gate electrode 2 is one or more of indium tin oxide, gold, silver, copper and aluminum.

[0010] Further, the material of the ferroelectric polymer gate dielectric layer 3 is one or a combination of poly(vinylidene fluoride-trifluoroethylene) and vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer.

[0011] Further, the material of the interface passivation layer 4 is one of tetracontane, polymethyl methacrylate, polystyrene, polyvinyl alcohol or polyvinylpyrrolidone.

[0012] Further, the material of the p-type organic semiconductor layer 5 is one of pentacene, copper phthalocyanine, zinc phthalocyanine, 2,7-bis(octyl)[1]benzothiopheno[3,2-b][1]benzothiophene and 2,9-didecyldinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene.

[0013] Further, the material of the n-type organic semiconductor layer 6 is one of fullerene and fluorinated copper phthalocyanine.

[0014] Furthermore, the thickness of the source electrode, drain electrode, and gate electrode is 20–120 nanometers; the thickness of the ferroelectric polymer gate dielectric layer is 100–1000 nanometers; the thickness of the interface passivation layer is 5–50 nanometers; and the thickness of both the p-type organic semiconductor layer and the n-type organic semiconductor layer is 20–100 nanometers.

[0015] On the other hand, the present invention also provides a method for fabricating a complementary organic in-memory computing NOT gate circuit, comprising the following steps: using vacuum thermal deposition technology or solution method, a gate electrode, a ferroelectric polymer gate dielectric layer, an interface passivation layer, a p-type semiconductor layer and an n-type semiconductor layer, a source electrode and a drain electrode are sequentially fabricated on the substrate surface to obtain a complementary organic in-memory computing NOT gate circuit.

[0016] Furthermore, the preparation method specifically includes the following steps:

[0017] Step 1: The gate electrodes of p-type organic transistor memory and n-type organic transistor memory are fabricated on the substrate surface using vacuum thermal deposition technology, and patterned using a mask.

[0018] Step 2: Prepare a ferroelectric polymer solution and use a solution method to prepare a ferroelectric polymer gate dielectric layer on the surface of the gate electrode obtained in Step 1; then perform heat treatment on the ferroelectric gate dielectric layer to remove residual solvent in the ferroelectric gate dielectric layer; the heat treatment temperature is 100-150℃; the time is 60-120 minutes; the mass concentration of the ferroelectric polymer solution is 2%-15%;

[0019] Step 3: Treat the prepared ferroelectric gate dielectric layer with oxygen plasma for 0.5 to 5 minutes;

[0020] Step 4: Prepare a solution for the interface passivation layer. On the surface of the ferroelectric gate dielectric layer obtained in Step 3, prepare the interface passivation layer using a solution method.

[0021] Step 5: A p-type organic semiconductor layer is prepared on the surface of the interface passivation layer obtained in Step 4 using vacuum thermal deposition technology, and a mask is used to pattern it.

[0022] Step 6: An n-type organic semiconductor layer is prepared on the surface of the interface passivation layer obtained in Step 4 using vacuum thermal deposition technology, and patterned using a mask;

[0023] Step 7: Drain and source electrodes are fabricated on the surfaces of the p-type and n-type organic semiconductor layers obtained in Steps 5 and 6 using vacuum thermal deposition technology, and patterned using a mask; thus obtaining a complementary organic in-memory computing NOT gate circuit.

[0024] Furthermore, the solution-based techniques include spin coating, blade coating, spray coating, or drop coating.

[0025] Compared with the prior art, the advantages of the present invention are as follows:

[0026] (1) Compared with existing conventional complementary organic NOT gate circuits, the complementary organic in-memory computing integrated NOT gate circuit of the present invention adds data storage function on the basis of performing NOT operations; that is, after the input signal is removed, the result of the NOT operation can be persistently stored in the gate circuit. This lays the foundation for the development of in-memory computing integrated circuits;

[0027] (2) Compared with other existing in-memory computing NOT gate circuits, the present invention realizes an n-type organic transistor memory; and connects it with a p-type organic transistor memory to obtain an in-memory computing NOT gate circuit that operates in a complementary mode, which can significantly reduce operating power consumption.

[0028] (3) Compared with other existing in-memory computing integrated NOT gate circuits, the main material of the complementary organic in-memory computing integrated NOT gate circuit of the present invention is organic / polymer material, which can realize flexible application. Its preparation method has obvious advantages of simple process, low temperature preparation and low cost. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0030] Figure 1 A top plan view of the complementary organic in-memory computing NOT gate circuit provided by the present invention;

[0031] In the figure: 1. Substrate; 2. Gate electrode; 3. Ferroelectric polymer gate dielectric layer; 4. Interface passivation layer; 5. P-type organic semiconductor layer; 6. N-type organic semiconductor layer; 7. Drain electrode and 8. Source electrode of p-type organic transistor memory; 9. Drain electrode and 10. Source electrode of n-type organic transistor memory.

[0032] Figure 2 A schematic cross-sectional view of the complementary organic in-memory computing NOT gate circuit provided by the present invention;

[0033] Figure 3 The circuit diagram of the complementary organic in-memory computing NOT gate circuit provided by the present invention;

[0034] Figure 4 The transfer characteristics of the p-type organic transistor memory in the complementary organic memory-in-memory NOT gate circuit provided in Embodiment 1 of the present invention when the source-drain voltage is -5 volts.

[0035] Figure 5 The storage and retention time characteristics of the p-type organic transistor memory in the complementary organic in-memory NOT gate circuit provided in Embodiment 1 of the present invention;

[0036] Figure 6 Storage cycle endurance of p-type organic transistor memory in the complementary organic in-memory computing NOT gate circuit provided in Embodiment 1 of the present invention;

[0037] Figure 7 The transfer characteristics of the n-type organic transistor memory in the complementary organic memory-computing NOT gate circuit provided in Embodiment 1 of the present invention when the source-drain voltage is 5 volts.

[0038] Figure 8 The storage retention time characteristics of the n-type organic transistor memory in the complementary organic in-memory computing NOT gate circuit provided in Embodiment 1 of the present invention;

[0039] Figure 9 Storage cycle endurance of n-type organic transistor memory in the complementary organic in-memory computing NOT gate circuit provided in Embodiment 1 of the present invention;

[0040] Figure 10 The input-output voltage characteristics of the complementary organic memory-computing NOT gate circuit provided in Embodiment 1 of the present invention at an operating voltage of 5 volts;

[0041] Figure 11 The complementary organic in-memory computing NOT gate circuit provided in Embodiment 1 of the present invention has good working durability when repeatedly performing non-logic operations.

[0042] Figure 12 The complementary organic in-memory computing NOT gate circuit provided in Embodiment 1 of the present invention exhibits the storage retention time characteristics of its operation results (1 state and 0 state) after undergoing NOT logic operation. Detailed Implementation

[0043] The embodiments of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solution of the present invention more clearly, and are therefore only examples and should not be used to limit the scope of protection of the present invention.

[0044] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0045] Example 1

[0046] like Figure 1 and Figure 2As shown, this invention provides a complementary organic in-memory computing NOT gate circuit, including a substrate 1 and a gate electrode 2, a ferroelectric gate polymer dielectric layer 3, an interface passivation layer 4, and an organic semiconductor layer thereon. The organic semiconductor layer includes a p-type organic semiconductor layer 5 and an n-type organic semiconductor layer 6, each with a source electrode and a drain electrode. Structurally, the gate electrode 2, the ferroelectric gate polymer dielectric layer 3, the interface passivation layer 4, the p-type organic semiconductor layer 5, and the drain electrode 7 and source electrode 8 thereon together form a p-type organic transistor memory. The gate electrode 2, the ferroelectric gate polymer dielectric layer 3, the interface passivation layer 4, the n-type organic semiconductor layer 6, and the drain electrode 9 and source electrode 10 thereon together form an n-type organic transistor memory. The p-type and n-type organic transistor memories are connected in series, sharing a single gate electrode 2 as the input terminal V. IN The source electrode 8 on the p-type organic semiconductor layer is connected to the drain electrode 9 on the n-type organic semiconductor layer, serving as the output terminal V. OUT The drain electrode 7 on the p-type organic semiconductor layer is connected to the operating voltage V. DD The source electrode 10 on the n-type organic semiconductor layer serves as the ground terminal GND.

[0047] In this embodiment, the substrate is made of polyethylene naphthalate; the gate electrode is made of aluminum, with a preferred thickness of 40–100 nanometers; the ferroelectric polymer gate dielectric layer is made of vinylidene fluoride-trifluoroethylene-trifluorochloroethylene copolymer, with a preferred thickness of 300–700 nanometers; the passivation layer is made of tetratetradecane, with a preferred thickness of 6–12 nanometers; the p-type organic semiconductor is made of 2,7-bisoctyl[1]benzothiophene[3,2-b][1]benzothiophene, with a preferred thickness of 30–50 nanometers; the n-type organic semiconductor is made of copper fluorinated phthalocyanine, with a preferred thickness of 30–50 nanometers; and the drain electrode and source electrode are made of gold, with a preferred thickness of 30–50 nanometers.

[0048] In this invention, all substances are commercially available products.

[0049] Performance testing:

[0050] The electrical performance of the fabricated complementary organic in-memory computing NOT gate circuit was tested using an Agilent B1500A semiconductor test and analyzer. All tests were conducted at room temperature and in an atmospheric environment.

[0051] The complementary organic in-memory NOT gate circuit provided in Example 1 consists of a p-type organic transistor memory and an n-type organic transistor memory connected in series. Its top plan view and cross-sectional structural diagram are shown below. Figure 1 andFigure 2 As shown;

[0052] In Example 1, the transfer characteristics of the p-type organic transistor memory at a source-drain voltage of -5 volts are as follows: Figure 4 As shown, its source-drain current increases significantly with the increase of negative gate voltage, exhibiting a typical p-type operating mode, and also exhibiting a large hysteresis characteristic, which indicates that it has storage function; the storage and retention time characteristics of the p-type organic transistor memory are as follows: Figure 5 As shown, after erasing / writing operations with gate voltage pulses of positive and negative 20 volts respectively, the source and drain currents representing the stored logic 0 and 1 states showed very slight changes within a test time lasting up to 20,000 seconds, indicating that it has stable memory retention characteristics; the memory cycle endurance of the p-type organic transistor memory is as follows: Figure 6 As shown, during 2000 cycles of erasing and writing using positive / negative 20V gate voltage pulses, the source and drain currents representing the stored logic 0 and 1 states change repeatedly but remain very stable, indicating that it has very reliable storage cycle durability.

[0053] In Example 1, the transfer characteristics of the n-type organic transistor memory at a source-drain voltage of 5 volts are as follows: Figure 7 As shown, its source-drain current increases significantly with the increase of the forward gate voltage, exhibiting a typical n-type operating mode, and also exhibiting a large hysteresis characteristic, which indicates that it has a storage function; the storage and retention time characteristics of the n-type organic transistor memory are as follows. Figure 8 As shown, after erasing / writing operations with negative / positive 20-volt gate voltage pulses respectively, the source-drain currents representing the stored logic 0 and 1 states showed very slight changes within a test time lasting up to 20,000 seconds, indicating that it has stable memory retention characteristics; the memory cycle endurance of the n-type organic transistor memory is as follows... Figure 9 As shown, during 2000 cycles of repeated erasing and writing operations using negative / positive 20-volt gate voltage pulses, the source and drain currents of the stored logic 0 and 1 states can change repeatedly and remain very stable, indicating that it has very reliable storage cycle durability.

[0054] In Example 1, the circuit diagram of the complementary organic in-memory computing NOT gate circuit is as follows: Figure 3 As shown, the shared gate electrode serves as the input terminal (V). IN In a p-type organic transistor memory, the source electrode is connected to the drain electrode of an n-type organic transistor memory, serving as the output terminal (V). OUT The drain electrode of a p-type organic transistor memory is connected to the operating voltage (V). DDThe source electrode of the n-type organic transistor memory is used as the ground terminal (GND). The operating voltage of the complementary organic memory-in-memory NOT gate described in Example 1 is set to 5 volts, and its tested input-output voltage characteristics are as follows: Figure 10 As shown, it is obvious that when the input voltage is negative (defined as logic 0 state), the output voltage is close to 5 volts, corresponding to logic 1 state; when the input voltage is positive (defined as logic 1 state), the output voltage is close to 0 volts, corresponding to logic 0 state; this presents a clear NOT logic operation. Specifically, positive / negative 20 volt input voltages are defined as logic 1 / 0 states respectively; when positive / negative 20 volt input voltage pulses are repeatedly applied to the input terminal, low output voltage (0.08~0.20 volts) and high output voltage (4.90~4.94 volts) can be measured repeatedly at the output terminal, corresponding to logic 0 and 1 states respectively. This repeated test can withstand 2000 cycles without significant attenuation. Figure 11 As shown, this demonstrates that the complementary organic in-memory computing NOT gate circuit possesses clear logical operation capabilities and high operational reliability. When a negative 20-volt input voltage pulse is applied to the input terminal (i.e., input logic 0), its output voltage approaches 5 volts, corresponding to logic 0 state, and this output voltage can be stably maintained for 20,000 seconds without significant change. When a positive 20-volt input voltage pulse is applied to the input terminal (i.e., input logic 1), its output voltage approaches 0 volts, corresponding to logic 0 state, and this output voltage slightly increases to 0.4 volts during the 20,000-second test period, still clearly maintaining the 0 state. The test data are as follows: Figure 11 As shown, this demonstrates clear storage functionality and high operational stability.

[0055] The test results show that the p-type and n-type organic transistor memories in the complementary organic in-memory computing NOT gate circuit provided in the embodiment have excellent storage characteristics. The complementary organic in-memory computing NOT gate circuit provided by the present invention has both reliable and stable non-logic operation and (operation result) storage functions, laying the foundation for the subsequent development of in-memory computing integrated circuits.

[0056] Example 2

[0057] This embodiment provides a method for fabricating a complementary organic in-memory computing NOT gate circuit, comprising the following steps: using vacuum thermal deposition or solution deposition techniques, a gate electrode, a ferroelectric polymer gate dielectric layer, an interface passivation layer, p-type and n-type semiconductor layers, and a source / drain electrode are sequentially fabricated on a substrate surface to obtain a complementary organic in-memory computing NOT gate circuit. Specifically, the method includes the following steps:

[0058] (1) Commercially purchased polyethylene naphthalate was used as a substrate; on the substrate, gate electrodes of p-type and n-type organic transistor memory were fabricated using vacuum thermal deposition technology and patterned using a mask;

[0059] (2) Prepare a ferroelectric polymer solution and prepare a ferroelectric polymer gate dielectric layer on the surface of the gate electrode obtained in step 1 using a solution method; then heat treat the ferroelectric gate dielectric layer to remove residual solvent in the ferroelectric gate dielectric layer; the heat treatment temperature is preferably 120-145℃; the time is preferably 60-120 minutes; the mass concentration of the ferroelectric polymer solution is preferably 5%-10%; the thickness of the obtained ferroelectric gate insulating layer can be optimized and adjusted by adjusting the concentration of the solution and the specific solution method preparation parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.);

[0060] (3) The prepared ferroelectric grid dielectric layer is subjected to oxygen plasma treatment, and the treatment time is preferably 1 to 3 minutes;

[0061] (4) Prepare a solution for the interface passivation layer. On the surface of the ferroelectric gate dielectric layer obtained in step 3, prepare the interface passivation layer by solution method. By adjusting the concentration of the solution and the specific solution method process parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.), the thickness of the obtained interface passivation layer can be optimized.

[0062] (5) A p-type organic semiconductor layer is prepared on the surface of the interface passivation layer obtained in step 4 using vacuum thermal deposition technology, and a mask is used to pattern it; the thickness of the obtained p-type organic semiconductor layer can be optimized and adjusted by specific preparation parameters;

[0063] (6) An n-type organic semiconductor layer is prepared on the surface of the interface passivation layer obtained in step 4 using vacuum thermal deposition technology, and a mask is used to pattern it; the thickness of the obtained n-type organic semiconductor layer can be optimized and adjusted by specific preparation parameters;

[0064] (7) The source and drain electrodes of the p-type and n-type organic transistor memory are prepared on the surface of the p-type and n-type organic semiconductor layers obtained in steps 5 and 6 using vacuum thermal deposition technology, and patterned using a mask; thus obtaining a complementary organic memory-computing integrated NOT gate circuit.

[0065] This embodiment does not have any special requirements for the vacuum thermal deposition technology or solution process used in the preparation of each thin film layer; methods commonly used by those skilled in the art can be adopted.

[0066] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0067] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0068] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A complementary organic in-memory computing NOT gate circuit, characterized in that, The device includes a substrate (1) and a gate electrode (2), a ferroelectric gate polymer gate dielectric layer (3), an interface passivation layer (4), and an organic semiconductor layer thereon. The organic semiconductor layer includes a p-type organic semiconductor layer (5) and an n-type organic semiconductor layer (6). Both the p-type organic semiconductor layer (5) and the n-type organic semiconductor layer (6) have source and drain electrodes. The gate electrode (2), the ferroelectric gate polymer gate dielectric layer (3), the interface passivation layer (4), the p-type organic semiconductor layer (5), and the drain electrode (7) and source electrode (8) thereon constitute a p-type organic transistor memory. The gate electrode (2), the ferroelectric gate polymer gate dielectric layer (3), the interface passivation layer (4), the n-type organic semiconductor layer (6), and the drain electrode (9) and source electrode (10) thereon constitute an n-type organic transistor memory. The p-type organic transistor memory and the n-type organic transistor memory are connected in series and share a single gate electrode (2) as the input terminal V. IN The source electrode (8) on the p-type organic semiconductor layer is connected to the drain electrode (9) on the n-type organic semiconductor layer, serving as the output terminal V. OUT The drain electrode (7) on the p-type organic semiconductor layer is connected to the operating voltage V. DD The source electrode (10) on the n-type organic semiconductor layer serves as the ground terminal GND.

2. The complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The substrate (1) is made of one or more of glass, silicon, polyethylene phthalate, polyethylene terephthalate, or polyethersulfone. The drain electrode, source electrode, and gate electrode (2) are made of one or more of indium tin oxide, gold, silver, copper, and aluminum.

3. The complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The ferroelectric polymer gate dielectric layer (3) is made of one or a combination of poly(vinylidene fluoride-trifluoroethylene), vinylidene fluoride-trifluoroethylene-trifluorochloroethylene copolymer.

4. The complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The material of the interface passivation layer (4) is one of tetradecane, polymethyl methacrylate, polystyrene, polyvinyl alcohol or polyvinylpyrrolidone.

5. The complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The p-type organic semiconductor layer (5) is made of one of the following: pentane, copper phthalocyanine, zinc phthalocyanine, 2,7-bisoctyl[1]benzothiophene[3,2-b][1]benzothiophene, and 2,9-dicepyldinaphthalene[2,3-b:2′,3′-f]thiophene[3,2-b]thiophene.

6. The complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The n-type organic semiconductor layer (6) is made of either fullerene or copper fluorinated phthalocyanine.

7. The complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The thickness of the source electrode, drain electrode, and gate electrode is 20–120 nm; the thickness of the ferroelectric polymer gate dielectric layer is 100–1000 nm; the thickness of the interface passivation layer is 5–50 nm; and the thickness of both the p-type organic semiconductor layer and the n-type organic semiconductor layer is 20–100 nm.

8. The method for fabricating a complementary organic in-memory computing NOT gate circuit as described in claim 1, characterized in that, The process includes the following steps: using vacuum thermal deposition or solution method, a gate electrode, a ferroelectric polymer gate dielectric layer, an interface passivation layer, a p-type semiconductor layer and an n-type semiconductor layer, a source electrode and a drain electrode are sequentially fabricated on the substrate surface to obtain a complementary organic memory-computing integrated NOT gate circuit.

9. The method for fabricating a complementary organic in-memory computing NOT gate circuit as described in claim 8, characterized in that, The preparation method specifically includes the following steps: Step 1: The gate electrodes of p-type organic transistor memory and n-type organic transistor memory are fabricated on the substrate surface using vacuum thermal deposition technology, and patterned using a mask. Step 2: Prepare a ferroelectric polymer solution and use a solution method to prepare a ferroelectric polymer gate dielectric layer on the surface of the gate electrode obtained in Step 1; then perform heat treatment on the ferroelectric gate dielectric layer to remove residual solvent in the ferroelectric gate dielectric layer; the heat treatment temperature is 100-150℃; the time is 60-120 minutes; the mass concentration of the ferroelectric polymer solution is 2%-15%; Step 3: Treat the prepared ferroelectric gate dielectric layer with oxygen plasma for 0.5 to 5 minutes; Step 4: Prepare a solution for the interface passivation layer. On the surface of the ferroelectric gate dielectric layer obtained in Step 3, prepare the interface passivation layer using a solution method. Step 5: A p-type organic semiconductor layer is prepared on the surface of the interface passivation layer obtained in Step 4 using vacuum thermal deposition technology, and a mask is used to pattern it. Step 6: An n-type organic semiconductor layer is prepared on the surface of the interface passivation layer obtained in Step 4 using vacuum thermal deposition technology, and patterned using a mask; Step 7: Drain electrodes and source electrodes are prepared on the surface of the p-type and n-type organic semiconductor layers obtained in Steps 5 and 6 using vacuum thermal deposition technology, and patterned using a mask; thus obtaining a complementary organic in-memory computing NOT gate circuit.

10. The method for fabricating a complementary organic in-memory computing NOT gate circuit as described in claim 9, characterized in that, The solution-based techniques include spin coating, blade coating, spray coating, or drop coating.

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