Bridge drive anti-continuity protection circuit

Abstract

The utility model discloses a kind of bridge drive anti-through protection circuit, including double-channel driver N2, its enable end EN and two output ends;Terminal PWMA_OUT and terminal PWMB_OUT are led out from the two output ends of double-channel driver N2, for output bridge circuit's drive signal;The terminal PWMA_OUT and terminal PWMB_OUT are respectively connected to the two input ends of NAND gate N3;The output end Y of NAND gate N3 is connected to level adjustment circuit;The level adjustment circuit is connected with the enable end EN of double-channel driver N2, to control the high and low of the enable end EN level of double-channel driver N2 according to the output end signal of NAND gate N3.The utility model has the advantages that: protection to bridge circuit is realized, protection can be carried out quickly when through occurs in bridge circuit, simultaneously with the holding lock of protection action, reset control etc., simultaneously, circuit is simple and reliable, protection is stable.

Description

Technical Field

[0001] This utility model relates to bridge topology switching power supplies in the field of power electronics technology and pulse power electronics technology, and in particular to a bridge drive anti-shoo-through protection circuit. Background Technology

[0002] With the rapid development of power electronics and semiconductor technologies, switching power supplies and high-voltage pulse solid-state switches have moved towards fully intelligent and digital control. Digital control, with its superior characteristics and comprehensive monitoring functions, is increasingly widely used. However, the core operating voltage of current digital control chips (such as DSP chips and FPGA chips) is relatively low, as low as 1.8V or even 1.2V. This means that digital power supplies are inevitably susceptible to electromagnetic interference during operation, leading to CNC program crashes or freezes. In such cases, the control circuit will exhibit uncertain control states. Furthermore, digital chip programs have a startup delay of several milliseconds to hundreds of milliseconds upon power-on, and the output control state is uncertain during power-on startup. Program crashes, freezes, and uncertain power-on states in digital power supplies often necessitate the addition of extra buffer and protection circuits, which undoubtedly increases circuit complexity and cost. Existing technologies often address this technical problem by improving the avoidance of program crashes. For example, patent application number 201920246661.0 describes a circuit for preventing program crashes, including a watchdog chip, a first field-effect transistor (FET), and a second FET. Combined with an external control circuit, the watchdog chip's timing is controlled via an I2C bus to periodically restart the microprocessor, achieving automatic restart in case of system crashes without manual intervention. The use of the first and second FETs improves the transmission capability between the watchdog chip and the external control circuit. The circuit is simple, low-cost, small in size, and easy to use. While this solution can significantly reduce digital chip crashes, crashes are an objective reality and cannot be completely avoided. Therefore, from a crash prevention perspective, it's possible to reduce, not eliminate, crashes. Thus, using protection circuits to assist in protecting against the consequences of crashes is more effective and can better protect the circuit.

[0003] Because of the uncertainty of the output state of digital circuits, in bridge topology switching power supplies and pulse power electronic circuits, the presence of digital bridge driver chips can cause abnormal output, leading to the simultaneous conduction of the bridge driver. This simultaneous conduction of bridge circuits is also not allowed in upper and lower bridge switching topologies, because it will cause the upper and lower bridge switching transistors (i.e., MOS or IGBT power switching transistors) to shoot through, making the switching transistors easily damaged by overcurrent due to shoot-through. Utility Model Content

[0004] The purpose of this utility model is to overcome the shortcomings of the prior art and provide a bridge-driven anti-shoo-through protection circuit for protecting bridge circuits. It can quickly protect the bridge circuit when a shoot-through occurs, and also has the functions of holding lock and reset control for protection actions.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a bridge drive anti-shoot-through protection circuit, including a dual-channel driver N2, which has an enable terminal EN and two output terminals; terminals PWMA_OUT and PWMB_OUT are led out from the two output terminals of the dual-channel driver N2 for outputting the drive signal of the bridge circuit;

[0006] The terminals PWMA_OUT and PWMB_OUT are respectively connected to the two input terminals of NAND gate N3; the output terminal Y of NAND gate N3 is connected to the level adjustment circuit; the level adjustment circuit is connected to the enable terminal EN of dual-channel driver N2, and is used to control the level of the enable terminal EN of dual-channel driver N2 according to the output signal of NAND gate N3.

[0007] The level adjustment circuit includes: a thyristor V2 and a thyristor drive circuit;

[0008] The input terminal of the thyristor drive circuit is connected to the output terminal Y of the NAND gate N3, and the output terminal of the thyristor drive circuit is connected to the G terminal of the thyristor V2; the input terminal of the thyristor V2 is connected to the enable terminal EN of the dual-channel driver N2; the output terminal of the thyristor V2 is grounded.

[0009] The thyristor driving circuit includes a transistor V3, which is positioned between the power supply VCC and the gate (G) terminal of the thyristor V2. The base (B) terminal of the transistor V3 is connected to the output terminal Y of the NAND gate N3. The transistor V3 controls the high and low level signals at the gate (G) terminal of the thyristor V3 to control whether the thyristor V2 is turned on or off.

[0010] The output terminal Y of the NAND gate N3 is grounded through resistor R6, and the output terminal Y is connected to the base (B) of transistor V3 through resistor R8. The emitter (E) of transistor V3 is grounded, and the collector (C) of transistor V3 is connected to power supply VCC and the anode of diode V4. The cathode of diode V4 is connected to the gate (G) of thyristor V2.

[0011] The cathode of diode V4 is grounded through resistor R5; the anode of diode V4 is grounded through capacitor C3.

[0012] The protection circuit also includes an optocoupler N11. The first terminal of the optocoupler N11 on the LED side is connected to the power supply VCC, and the second terminal is connected to the anode of diode V6. The cathode of diode V6 is connected to the input terminal of thyristor V2. The first output terminal of the optocoupler N11 on the phototransistor side leads to terminal F_LOCK, and the second output terminal is grounded. Terminal F_LOCK is connected to the indicator light module to trigger the indicator light module to light up the indicator light through the signal of terminal F_LOCK.

[0013] The power supply VCC is connected to the terminal F_LOCK via resistor R2 and LED V1, so that the LED V1 can indicate the trigger status of the protection circuit.

[0014] The protection circuit also includes an optocoupler N12. The first end of the optocoupler N12 on the LED side is connected to the power supply VCC, and the second end leads out to the reset terminal F_RST. The first and second ends of the optocoupler N12 on the phototransistor side are both grounded. Fault reset control is achieved by adjusting the high and low level signals of the reset terminal F_RST.

[0015] The advantages of this invention are: it provides protection for bridge circuits, quickly protecting them in the event of a shoot-through, and includes features such as holding lock and reset control for protection actions. The circuit is simple, reliable, and provides stable protection. When both bridge drivers are high simultaneously (i.e., when a shoot-through occurs), it can quickly cut off the output, lock the fault state, and provide an alarm output. The reset circuit and fault indicator circuit are integrated into a single chip, making it simple and reliable. Appropriately connecting reverse-biased diodes (V4, V5, V6) in series effectively reduces the risk of circuit malfunction when the voltage level is not zero. The overall circuit is simple, reliable, and has strong anti-interference capabilities. Attached Figure Description

[0016] The following is a brief explanation of the contents of each of the accompanying drawings and the markings in the drawings:

[0017] Figure 1 This is a circuit diagram of the bridge drive anti-shoo-through protection circuit of this utility model. Detailed Implementation

[0018] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and the description of the preferred embodiments.

[0019] This embodiment mainly protects the switching devices in the upper and lower bridge switching topologies of the bridge drive circuit, preventing the upper and lower bridge switching transistors (i.e., power switching transistors such as MOS or IGBT) from shoot-through, which can easily cause overcurrent damage to the switching transistors. After detecting shoot-through between the upper and lower bridges, the fault protection is triggered, the enable terminal of the drive chip outputting the drive signal is pulled low, and the chip stops working after the enable is stopped. The fault remains valid until a reset signal arrives to reset the drive chip, after which the output signal can be woken up.

[0020] like Figure 1 As shown, the bridge circuit uses the N2 chip as the driver, which has two inputs, two outputs, and two enable terminals. Under normal conditions, the enable terminals ENA and ENB are both led out to the PWM_EN terminal through resistor R4. This terminal is used to input the enable signal. When the enable signal is valid, the N2 chip outputs the corresponding bridge drive signal based on the PWMA_IN and PWMB_IN signals at the input terminals, outputting through the PWMA_OUT and PWMB_OUT terminals. If both the PWMA_OUT and PWMB_OUT terminals are high, it indicates a shoot-through fault, and the N2 chip should be disabled to continue operating, thus activating the protection function. In this application, the main protection method is to pull down the enable terminals of ENA and ENB, thereby disabling the N2 chip from operation. The N2 dual-channel driver is implemented using the IVCR2404D chip.

[0021] like Figure 1 As shown, a bridge-driven anti-shoot-through protection circuit includes a dual-channel driver N2 with an enable terminal EN and two output terminals; terminals PWMA_OUT and PWMB_OUT are led out from the two output terminals of the dual-channel driver N2 for outputting the drive signal of the bridge circuit.

[0022] The terminals PWMA_OUT and PWMB_OUT are respectively connected to the two input terminals of NAND gate N3; the output terminal Y of NAND gate N3 is connected to a level adjustment circuit; the level adjustment circuit is connected to the enable terminal EN of the dual-channel driver N2, and is used to control the level of the enable terminal EN of the dual-channel driver N2 according to the output signal of NAND gate N3. The enable terminal EN of N2 is active high and inactive low, thereby controlling the operation of N2 according to the high and low levels, thus playing a protective role.

[0023] The EN terminal is pulled low by a level adjustment circuit. The level adjustment circuit includes a thyristor V2 and a thyristor driver circuit. The input terminal of the thyristor driver circuit is connected to the output terminal Y of the NAND gate N3, and the output terminal of the thyristor driver circuit is connected to the G terminal of the thyristor V2. The input terminal of the thyristor V2 is connected to the enable terminal EN of the dual-channel driver N2. The output terminal of the thyristor V2 is grounded.

[0024] In this embodiment, the thyristor driving circuit includes a transistor V3, which is positioned between the power supply VCC and the gate (G) terminal of the thyristor V2. The base (B) of transistor V3 is connected to the output terminal Y of the NAND gate N3. Transistor V3 controls the high and low level signals at the gate of the thyristor V3 to control whether the thyristor V2 is turned on or off. The output terminal Y of the NAND gate N3 is grounded through resistor R6 and connected to the base (B) of transistor V3 through resistor R8. The emitter (E) of transistor V3 is grounded, and the collector (C) of transistor V3 is connected to the power supply VCC and the anode of diode V4. The cathode of diode V4 is connected to the gate (G) terminal of the thyristor V2. The power supply VCC provides electrical energy and can be directly connected to the power supply port of the NAND gate N3 or supplied to V3 through resistor R7. The cathode of diode V4 is grounded through resistor R5, and the anode of diode V4 is grounded through capacitor C3. The NAND gate N3 uses the SN74LVC1 G00DBVR chip, which has two input terminals, one ground terminal, one power supply terminal, and one output terminal Y; the ground terminal and the power supply terminal are grounded and connected to the power supply VCC, respectively.

[0025] The N2 chip's EN enable terminal has two enable pins, ENA and ENB. ENA and ENB are connected together and then connected to the PWM_EN terminal via resistor R4. The digital enable signal is obtained through this terminal to control the N2's output. ENB is grounded via capacitor C4. The SCR V2 is used to pull the EN terminal low in case of a fault. For safety, a diode V5 is included. The anode of V5 is connected to ENA and ENB; the cathode is connected to input terminal A of the SCR V2.

[0026] Furthermore, in order to achieve continuous fault protection and subsequent reset control, two optocouplers N11 and N12 are provided.

[0027] The optocoupler N11 has the following characteristics: Its LED side has one terminal connected to the power supply VCC, and its second terminal connected to the anode of diode V6. The cathode of diode V6 is connected to the input of the thyristor V2. The phototransistor side of optocoupler N11 has a first output terminal F_LOCK and a second output terminal grounded. Terminal F_LOCK is connected to the indicator light module, used to trigger the indicator light module to illuminate the indicator light via a signal from terminal F_LOCK. The indicator light module can use the digital chip of the digital power supply to read the level signal of terminal F_LOCK to achieve fault protection alarm indication.

[0028] Alternatively, the power supply VCC can be connected to the terminal F_LOCK via resistor R2 and LED V1. The LED V1 can then be used to indicate the trigger status of the protection circuit. Whether the additional LED V1 is lit or not can be used to determine whether the circuit is in a fault protection state.

[0029] Optocoupler N12: The first terminal of the LED side of optocoupler N12 is connected to the power supply VCC, and the second terminal leads to the reset terminal F_RST; the first and second terminals of the phototransistor side of optocoupler N12 are both grounded; fault reset control is achieved by adjusting the high and low level signals of the reset terminal F_RST. The first terminal of the phototransistor side of optocoupler N12 is grounded through capacitor C2; at the same time, the terminal F_LOCK is grounded through capacitor C1.

[0030] In this solution, the two optocouplers N11 and N12 can be implemented using an integrated optocoupler N1. N1 has two optocoupler modules to achieve the above functions, thus making the circuit simple and reliable. The integrated circuit optocoupler driver includes the HCPL0630 chip.

[0031] The working principle of this solution is explained below with reference to the accompanying drawings:

[0032] As attached Figure 1As shown, a bridge-driven anti-shoot-through protection circuit adds a NAND gate N3 to the output of a two-output driver N2 with enable control. When the drive signals PWMA_OUT and PWMB_OUT are both high (i.e., when shoot-through occurs), the output Y of N3 is low. Consequently, transistor V3 is cut off because its input B terminal is low. At this time, VCC is applied to the gate of thyristor V2 through resistor R7 and diode V4, causing thyristor V2 to turn on. The two enable terminals ENA and ENB of driver N2 are pulled down to low level by the turned-on thyristor V2 through diode V5. When the two enable terminals ENA and ENB of the device N2 are low, the outputs OUTA and OUTB are forced to be low (i.e., the drive signals PWMA_OUT and PWMB_OUT are forced to be low). Furthermore, since the thyristor V2 is turned on, VCC maintains the thyristor V2 continuously on through resistor R1, one photodiode of the optocoupler driving N1, and diode V6, thus achieving fault locking and preventing the drive signals PWMA_OUT and PWMB_OUT from self-starting output. VCC maintains the thyristor V2 continuously on through resistor R1, one photodiode of the optocoupler driving N1, and diode V6. When the circuit is activated, the output IO1 of optocoupler driver N1 goes low due to the conduction of the photodiode (i.e., F_LOCK is a low-level signal). When the digital control chip (such as DSP or FPGA) detects that F_LOCK is low, it provides a fault indication. Resistor R2 and LED V1 also serve as fault indicators. In case of a reset fault, the digital control chip first sets the enable signal PWM_EN to low, and then provides a low-level active reset pulse on the reset signal F_RST. This reset pulse is applied to the output of optocoupler driver N1 through another photodiode. At the IO2 terminal, since the output IO2 of the optocoupler driver N1 is low, and the PWM_EN signal is also low, the current that sustains the on-state of the thyristor V2 is lost (i.e., becomes 0). Furthermore, since the drive signals PWMA_OUT and PWMB_OUT are not simultaneously high under normal conditions, the output Y of the NOT gate N3 will be high. This high voltage level, through resistor R8, turns on the transistor V3, thus making the voltage applied to the trigger electrode of the thyristor V2 0. Then, the thyristor V2 turns off due to the zero-crossing, achieving fault reset and ultimately achieving the purpose of the bridge drive shoot-through protection circuit.

[0033] The advantages of this invention are: when both drivers of the bridge circuit are high simultaneously (i.e., when a shoot-through occurs), the output can be quickly cut off, and the fault state can be locked to provide an alarm output; the reset circuit and fault indicator circuit are integrated into a single chip, which is simple and reliable. The appropriate series insertion of reverse-biased diodes (V4, V5, V6) effectively reduces the risk of circuit malfunction when the voltage level is not zero. The overall circuit is simple, reliable, and has strong anti-interference capabilities.

[0034] Obviously, the specific implementation of this invention is not limited to the above-described methods. Any non-substantial improvements made using the inventive concept and technical solution of this invention are within the protection scope of this invention.

Claims

1. A bridge-driven anti-shoot-through protection circuit, comprising a dual-channel driver N2, having an enable terminal EN and two output terminals; terminals PWMA_OUT and PWMB_OUT are led out from the two output terminals of the dual-channel driver N2 for outputting drive signals for the bridge circuit; characterized in that The terminals PWMA_OUT and PWMB_OUT are respectively connected to the two input terminals of NAND gate N3; the output terminal Y of NAND gate N3 is connected to the level adjustment circuit; the level adjustment circuit is connected to the enable terminal EN of dual-channel driver N2, and is used to control the level of the enable terminal EN of dual-channel driver N2 according to the output signal of NAND gate N3.

2. The bridge drive anti-shoot-through protection circuit of claim 1, wherein: The level adjustment circuit includes: a thyristor V2 and a thyristor drive circuit; The input terminal of the thyristor drive circuit is connected to the output terminal Y of the NAND gate N3, and the output terminal of the thyristor drive circuit is connected to the G terminal of the thyristor V2; the input terminal of the thyristor V2 is connected to the enable terminal EN of the dual-channel driver N2; the output terminal of the thyristor V2 is grounded.

3. A bridge drive anti-shoot-through protection circuit as claimed in claim 2, characterized in that: The thyristor driving circuit includes a transistor V3, which is positioned between the power supply VCC and the gate (G) terminal of the thyristor V2. The base (B) terminal of the transistor V3 is connected to the output terminal Y of the NAND gate N3. The transistor V3 controls the high and low level signals at the gate (G) terminal of the thyristor V3 to control whether the thyristor V2 is turned on or off.

4. A bridge drive anti-shoot-through protection circuit as claimed in claim 3, characterized in that: The output terminal Y of the NAND gate N3 is grounded through resistor R6, and the output terminal Y is connected to the base (B) of transistor V3 through resistor R8. The emitter (E) of transistor V3 is grounded, and the collector (C) of transistor V3 is connected to power supply VCC and the anode of diode V4. The cathode of diode V4 is connected to the gate (G) of thyristor V2.

5. A bridge drive anti-shoot-through protection circuit as claimed in claim 4, characterized in that: The cathode of diode V4 is grounded through resistor R5; the anode of diode V4 is grounded through capacitor C3.

6. A bridge drive anti-shoot-through protection circuit as claimed in any one of claims 2 to 5, wherein: The protection circuit also includes an optocoupler N11. The first terminal of the optocoupler N11 on the LED side is connected to the power supply VCC, and the second terminal is connected to the anode of diode V6. The cathode of diode V6 is connected to the input terminal of thyristor V2. The first output terminal of the optocoupler N11 on the phototransistor side leads to terminal F_LOCK, and the second output terminal is grounded. Terminal F_LOCK is connected to the indicator light module to trigger the indicator light module to light up the indicator light through the signal of terminal F_LOCK.

7. A bridge drive anti-shoot-through protection circuit as claimed in claim 6, characterized in that: The power supply VCC is connected to the terminal F_LOCK via resistor R2 and LED V1, so that the LED V1 can indicate the trigger status of the protection circuit.

8. A bridge drive anti-shoot-through protection circuit as claimed in claim 6, characterized in that: The protection circuit also includes an optocoupler N12. The first end of the optocoupler N12 on the LED side is connected to the power supply VCC, and the second end leads out to the reset terminal F_RST. The first and second ends of the optocoupler N12 on the phototransistor side are both grounded. Fault reset control is achieved by adjusting the high and low level signals of the reset terminal F_RST.

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