T-type inverter driving signal interlocking circuit and inverter

Abstract

The utility model provides a T-type inverter driving signal interlocking circuit and an inverter. Comprising a first NOT gate for receiving a first signal and outputting a first inversion signal; the second NOT gate receives the second signal and outputs a second inverted signal; the third NOT gate receives the third signal and outputs a third inversion signal; the fourth NOT gate receives the fourth signal and outputs a fourth inverted signal; the first input end of the first AND gate driving unit receives a first signal, the second input end of the first AND gate driving unit is connected with the output end of the second NOT gate, and the third input end of the first AND gate driving unit is connected with the output end of the third NOT gate; the first input end of the second AND gate driving unit receives a second signal, the second input end is connected with the output end of the first NOT gate, the third input end is connected with the output end of the fourth NOT gate, and the second AND gate driving unit outputs a lower tube driving signal. Interlocking of driving signals is achieved, it is guaranteed that the upper pipe and the lower pipe, the upper pipe and one middle pipe, and the lower pipe and the other middle pipe of the T-type inverter cannot be switched on at the same time during operation, and operation safety of the inverter is effectively guaranteed.

Description

TECHNICAL FIELD

[0001] The utility model belongs to photovoltaic inverter technical field, especially a kind of T-type inverter drive signal interlock circuit and inverter. BACKGROUND

[0002] Photovoltaic inverter is mainly used to convert the direct current generated by solar panel into alternating current.The core module that can convert direct current into alternating current is inverter circuit, and the popular inverter circuit on market is multi-level H bridge and T-type inverter circuit (also commonly known as T-type inverter).To convert direct current into alternating current using T-type inverter, the accurate control of the drive signal of four power switch tubes (such as Insulated Gate Bipolar Transistor (IGBT) or Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)) in T-type inverter bridge arm is needed.Taking common-collector T-type inverter as an example, the upper tube and the lower tube, the upper tube and the left middle tube, the lower tube and the right middle tube cannot be turned on at the same time, otherwise bridge arm short circuit will be caused, and instantaneous maximum current will be generated.The core microcontroller unit (MCU) (digital signal processor (DSP)) of photovoltaic inverter controls the on and off of power switch tube of T-type inverter circuit through sine wave pulse width modulation (SPWM) modulation strategy.However, in actual operation, the drive signal sent by DSP inevitably fluctuates, which can cause the upper tube and the lower tube of T-type inverter to be turned on at the same time, and can endanger the operation safety of T-type inverter circuit and even the whole photovoltaic inverter.Therefore, drive signal interlocking needs to be realized at hardware level. UTILITY MODEL CONTENTS

[0003] The utility model aims at providing a kind of T-type inverter drive signal interlocking circuit and inverter, simple structure, can interlock the signal interlocking circuit of T-type inverter drive signal.

[0004] In the first aspect, the utility model provides a kind of T-type inverter drive signal interlocking circuit, it receives first signal, second signal, third signal, fourth signal, and includes:

[0005] Inverting unit, comprising:

[0006] The first non-gate receives first signal and outputs first inverted signal;

[0007] The second non-gate receives second signal and outputs second inverted signal;

[0008] The third non-gate receives third signal and outputs third inverted signal;

[0009] a fourth inverter receiving the fourth signal and outputting a fourth inverted signal;

[0010] a driving interlock module, comprising:

[0011] a first AND gate driving unit having a first input receiving the first signal, a second input connected to the output of the second inverter, and a third input connected to the output of the third inverter, the output of the first AND gate driving unit outputting an upper tube driving signal;

[0012] a second AND gate driving unit having a first input receiving the second signal, a second input connected to the output of the first inverter, and a third input connected to the output of the fourth inverter, the output of the second AND gate driving unit outputting a lower tube driving signal.

[0013] Preferably, the first AND gate driving unit comprises an AND gate one and an AND gate two.

[0014] The first input of the AND gate one is connected to the first input of the first AND gate driving unit, and the second input of the AND gate one is connected to the second input of the first AND gate driving unit.

[0015] The first input of the AND gate two is connected to the output of the AND gate one, the second input of the AND gate two is connected to the third input of the first AND gate driving unit, and the output of the AND gate two is connected to the output of the first AND gate driving unit.

[0016] The second AND gate driving unit comprises an AND gate three and an AND gate four.

[0017] The first input of the AND gate three is connected to the first input of the second AND gate driving unit, and the second input of the AND gate three is connected to the second input of the second AND gate driving unit.

[0018] The first input of the AND gate four is connected to the output of the AND gate three, the second input of the AND gate four is connected to the third input of the second AND gate driving unit, and the output of the AND gate four is connected to the output of the second AND gate driving unit.

[0019] Preferably, further comprising: a fifth inverter, a sixth inverter, an AND gate five and an AND gate six.

[0020] The input of the fifth inverter is connected to the output of the AND gate one, the output of the fifth inverter is connected to the first input of the AND gate five, the second input of the AND gate five receives a third signal, and the output of the AND gate five outputs a middle tube one driving signal.

[0021] The input of the sixth inverter is connected to the output of the AND gate three, the first input of the AND gate six is connected to the output of the sixth inverter, the second input of the AND gate six receives a fourth signal, and the output of the AND gate six outputs a middle tube two driving signal.

[0022] Preferably, the first AND gate driving unit comprises: an AND gate one and an AND gate two;

[0023] The first input end of the AND gate one is connected with the second input end of the first AND gate driving unit, and the second input end of the AND gate one is connected with the third input end of the first AND gate driving unit;

[0024] The first input end of the AND gate two is connected with the output end of the AND gate one, the second input end of the AND gate two is connected with the first input end of the first AND gate driving unit, and the output end of the AND gate two is connected with the output end of the first AND gate driving unit.

[0025] Preferably, the second AND gate driving unit comprises: an AND gate three and an AND gate four;

[0026] The first input end of the AND gate three is connected with the second input end of the second AND gate driving unit, and the second input end of the AND gate three is connected with the third input end of the second AND gate driving unit,

[0027] The first input end of the AND gate four is connected with the output end of the AND gate three, the second input end of the AND gate four is connected with the first input end of the second AND gate driving unit, and the output end of the AND gate four is connected with the output end of the second AND gate driving unit.

[0028] Preferably, further comprising: a third AND gate driving unit and a fourth AND gate driving unit,

[0029] The third AND gate driving unit receives a third signal at the first input end, and the output end of the third AND gate driving unit outputs a middle tube one driving signal.

[0030] The fourth AND gate driving unit receives a fourth signal at the first input end, and the output end of the fourth AND gate driving unit outputs a middle tube two driving signal.

[0031] Preferably, the third AND gate driving unit comprises: an AND gate five, an AND gate six and a fifth NOT gate; the first input end of the AND gate five is connected with the output end of the first NOT gate, and the second input end of the AND gate five receives a second signal;

[0032] The input end of the fifth NOT gate is connected with the output end of the AND gate five;

[0033] The first input end of the AND gate six receives the third signal, the second input end of the AND gate six is connected with the output end of the fifth NOT gate, and the output end of the AND gate six outputs the middle tube one driving signal.

[0034] The fourth AND gate driving unit comprises: an AND gate seven, an AND gate eight and a sixth NOT gate; the first input end of the AND gate seven is connected with the output end of the second NOT gate, the second input end of the AND gate seven receives the first signal, and the input end of the sixth NOT gate is connected with the output end of the AND gate seven;

[0035] The first input end of the AND gate eight receives the fourth signal, the second input end of the AND gate eight is connected with the output end of the sixth NOT gate, and the output end of the AND gate eight outputs the middle tube two driving signal.

[0036] Preferably, the signal delay device further comprises an input end and an output end, and the signal delay device comprises a resistor, a capacitor and a diode; the cathode of the diode is connected with the input end of the signal delay device, the anode of the diode is connected with the output end of the signal delay device; one end of the resistor is connected with the cathode of the diode, the other end of the resistor is connected with the anode of the diode, one end of the capacitor is connected with the anode of the diode, and the other end of the capacitor is grounded.

[0037] The output end of the first NOT gate is connected with the second input end of the second AND gate driving unit through a signal delay device;

[0038] The output end of the second NOT gate is connected with the second input end of the first AND gate driving unit through a signal delay device;

[0039] The output end of the third NOT gate is connected with the third input end of the first AND gate driving unit through a signal delay device;

[0040] The output end of the fourth NOT gate is connected with the third input end of the second AND gate driving unit through a signal delay device.

[0041] Preferably, the signal delay device further comprises an input end and an output end, and the signal delay device comprises a resistor, a capacitor and a diode; the cathode of the diode is connected with the input end of the signal delay device, the anode of the diode is connected with the output end of the signal delay device; one end of the resistor is connected with the cathode of the diode, the other end of the resistor is connected with the anode of the diode, one end of the capacitor is connected with the anode of the diode, and the other end of the capacitor is grounded.

[0042] The output end of the first NOT gate is connected with the second input end of the second AND gate driving unit through a signal delay device;

[0043] The output end of the second NOT gate is connected with the second input end of the first AND gate driving unit through a signal delay device;

[0044] The output end of the third NOT gate is connected with the third input end of the first AND gate driving unit through a signal delay device;

[0045] The output end of the fourth NOT gate is connected with the third input end of the second AND gate driving unit through a signal delay device.

[0046] The output end of the fifth NOT gate is connected with the first input end of the AND gate five through a signal delay device;

[0047] The output end of the sixth NOT gate is connected with the first input end of the AND gate six through a signal delay device.

[0048] An inverter comprising at least one phase T-type inverter circuit, comprising at least any one of the T-type inverter drive signal interlocking circuits described above, and the T-type inverter drive signal interlocking circuit is connected and drives the T-type inverter circuit.

[0049] The T-type inverter drive signal interlocking circuit and the inverter provided by the utility model realize the interlocking of the signal for driving the T-type inverter by only using simple logic gate electronic components, ensure that the upper tube and the lower tube of the T-type inverter, the upper tube and one of the middle tubes, and the lower tube and the other middle tube do not appear to be opened at the same time when running, and effectively guarantee the running safety of the T-type inverter. BRIEF DESCRIPTION OF DRAWINGS

[0050] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0051] Figure 1 T-type inverter drive signal interlocking circuit circuit for example Figure One

[0052] Figure 2 Common collector T-type inverter circuit schematic for example Figure One

[0053] Figure 3 T-type inverter drive signal interlocking circuit circuit for example Figure Two

[0054] Figure 4 T-type inverter drive signal interlocking circuit circuit for example Figure Three

[0055] Figure 5 T-type inverter drive signal interlocking circuit circuit for example Figure Four

[0056] Figure 6 T-type inverter drive signal interlocking circuit circuit for example Figure Five

[0057] Figure 7 Common collector T-type inverter circuit schematic for example Figure Two

[0058] BRIEF DESCRIPTION OF DRAWINGS

[0059] 1 - signal delay.

[0060] ​​​​​​​The specific embodiments of the application have been shown and described in the above drawings and text. These drawings and text are not meant to limit the scope of the inventive concept in any way but are merely meant to illustrate the inventive concept to one of ordinary skill in the art by reference to a particular embodiment. DETAILED DESCRIPTION

[0061] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to all alternative embodiments, as would be understood by one skilled in the art. The following exemplary embodiments are described herein with reference to specific embodiments thereof, but those skilled in the art will recognize that the application is not limited thereto. Thus, embodiments falling within the scope of the application are envisioned and appreciated.

[0062] The technical solutions of the application and how the technical solutions solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the application will be described below with reference to the drawings.

[0063] Embodiment One

[0064] One of the functions of a photovoltaic inverter is to convert DC power into AC power. The photovoltaic inverter receives DC power from photovoltaic panels or energy storage batteries, converts the DC power into AC power through a T-shaped inverter circuit composed of power switching tubes (MOS tubes, IGBTs, etc.), and then provides the AC power to a load or a power grid. As shown in the T-shaped inverter, Figure 2 Each IGBT has a gate G, a collector C, and an emitter E. A diode is provided between the collector C and the emitter E, with the cathode of the diode connected to the collector C and the anode of the diode connected to the emitter E. As shown in Figure 2 The cross point OUT connects the emitter E of the upper tube, the collector C of the lower tube, and the emitter E of the right middle tube. The cross point OUT is the current output point of the T-shaped inverter circuit, and CON1 refers to the connection of the next stage of electronic circuit of the T-shaped inverter circuit, which is only for illustration. Figure 2As shown, the collector C of the upper tube is connected to HV-HV (HV-HV refers to the positive of the DC bus voltage), and the emitter E of the lower tube is connected to H_GND (H_GND refers to the negative of the DC bus voltage). Among them, the chip (DSP) of the photovoltaic inverter outputs PWM waves to control the opening or closing of the power switch tube, that is, the gate of the power switch tube receives a high level to open, and receives a low level to turn off, and the low level generally refers to 0V or close to 0V. A single-phase photovoltaic inverter has a T-type inverter circuit, and a three-phase photovoltaic inverter has three T-type inverter circuits (corresponding to R\S\T three-phase currents), and each T-type inverter circuit can be controlled independently. Taking one of the T-type inverter circuits as an example, it is generally composed of 4 power switch tubes, and has an upper tube, a lower tube and two middle tubes. The T-type inverter has two middle tubes in common emitter connection or common collector connection (referring to the common emitter connection mode shown in page 18 of the master's thesis “Design and Implementation of T-type Three-level Inverter” and the common collector connection mode shown in page 23 of the master's thesis “T-type Three-level Inverter Technology Research”). The opening and closing of the four power switch tubes are controlled by the DSP independently. How to modulate the opening and closing of the four power switch tubes is the prior art (SPWM modulation strategy technology, that is, outputting the desired sine wave through the opening and closing of the four power switch tubes), so this application will not be repeated. However, the upper tube and the lower tube of the T-type inverter cannot be turned on at the same time, and the upper tube and a certain middle tube cannot be turned on at the same time, and the lower tube and another middle tube cannot be turned on at the same time. Taking the common emitter T-type inverter shown in page 18 of the master's thesis “Design and Implementation of T-type Three-level Inverter” as an example, the upper tube SA1 and the right middle tube SA3 cannot be turned on at the same time, and the lower tube SA4 and the left middle tube SA2 cannot be turned on at the same time. Taking the common collector T-type inverter shown in page 23 of the master's thesis “T-type Three-level Inverter Technology Research” as an example, the upper tube S1 and the left middle tube S3 cannot be turned on at the same time, and the lower tube S2 and the right middle tube S4 cannot be turned on at the same time. A T-type inverter output has three states, P state of the upper half of the sine wave: output positive DC bus; O state of the midpoint of the sine wave: output DC bus midpoint; N state of the lower half of the sine wave: output negative DC bus.

[0065] Figure 1 T-type inverter drive signal interlocking circuit circuit for example Figure One ; Common collector T-type inverter circuit schematic for example Figure 2 ; T-type inverter drive signal interlocking circuit circuit for example Figure One ; T-type inverter drive signal interlocking circuit circuit for example Figure 3 ; T-type inverter drive signal interlocking circuit circuit for example Figure Two ; T-type inverter drive signal interlocking circuit circuit for example Figure 4 ; T-type inverter drive signal interlocking circuit circuit for example Figure Three ; T-type inverter drive signal interlocking circuit circuit for example Figure 5 ; T-type inverter drive signal interlocking circuit circuit for example Figure Four ; T-type inverter drive signal interlocking circuit circuit for example Figure 6Example of a T-type inverter drive signal interlock circuit Figure Five ; Figure Seven Schematic diagram of a common-collector T-type inverter circuit as an example Figure Two .

[0066] like Figures 1-2 As shown in Figure 2, taking a T-type inverter with a common collector as an example, the distribution of its upper transistor, lower transistor, middle transistor one, and middle transistor two is shown in Figure 2. Figure 2 In this embodiment, the middle tube 1 is the left middle tube, and the middle tube 2 is the right middle tube. This T-type inverter drive signal interlock circuit receives a first signal, a second signal, a third signal, and a fourth signal. These first, second, third, and fourth signals are all PWM waves generated by the DSP. One set of first, second, third, and fourth signals is used to drive one T-type inverter circuit (for example, a three-phase inverter may have three T-type inverters, requiring three sets of first, second, third, and fourth signals). These three sets of signals do not interfere with each other, and their modulation strategies will differ. The first, second, third, and fourth signals are merely designations and do not represent the three T-type inverters. The first signal received by each component of the T-type inverter is in the same state at the same time (refer to the inverter's SPWM modulation technology for details). Based on the DSP's SPWM modulation strategy, the first signal H can be considered to mainly drive the upper transistor, the second signal L mainly drive the lower transistor, the third signal N mainly drive the left middle transistor, and the fourth signal M mainly drive the right middle transistor. The "used" here means they play an important role in the switching process of the corresponding power switches, not necessarily for direct driving (if there is no hardware-level interlocking circuit, then the first signal H, second signal L, third signal N, and fourth signal M can be considered to directly drive the corresponding power switches). Let the first signal be H, the second signal L, the third signal N, and the fourth signal M; the upper transistor drive signal be D_H, the lower transistor drive signal be D_L, the middle transistor one drive signal be D_N, and the middle transistor two drive signal be D_M. In this embodiment, the left middle transistor of the T-type inverter is directly driven by the third signal N, and the right middle transistor is directly driven by the fourth signal M. When the upper MOSFET drive signal D_H is high, the upper MOSFET is turned on; when the upper MOSFET drive signal D_H is low, the upper MOSFET is turned off. When the lower MOSFET drive signal D_L is high, the lower MOSFET is turned on; when the lower MOSFET drive signal D_L is low, the lower MOSFET is turned off. When the middle MOSFET 1 drive signal D_N is high, the middle MOSFET 1 is turned on; when the middle MOSFET 1 drive signal D_N is low, the middle MOSFET 1 is turned off. When the middle MOSFET 2 drive signal D_M is high, the middle MOSFET 2 is turned on; when the middle MOSFET 2 drive signal D_M is low, the middle MOSFET 2 is turned off.

[0067] For example, when the entire T-type inverter is in the waveform output of the positive half cycle, the upper tube is frequently switched, and the middle tube two is in the always-on state. The always-on middle tube two is to reduce the loss when the T-type inverter switches state, which is a conventional modulation strategy. At this time, the lower tube needs to be in the always-off state, and the middle tube one is opposite to the switching state of the upper tube (i.e., in the positive half cycle, the middle tube one is also frequently switched, but when the upper tube is on, the middle tube one is off, and when the upper tube is off, the middle tube one is on). When the output of the T-type inverter is the midpoint of the DC bus, the middle tube one and the middle tube two will be turned on at the same time, which is the existing theory and will not be repeated here. Although the DSP can control the second signal L and the third signal N to be low, signal fluctuations will inevitably occur, causing the second signal L or the third signal N to be high. Without the drive signal interlocking circuit, this situation will cause the lower tube or the middle tube one to be turned on, and thus the situation of the upper tube and the lower tube being turned on at the same time or the upper tube and the middle tube one being turned on at the same time will occur, which will cause the T-type inverter circuit to be short-circuited instantaneously, generate a large pulse current, and thus damage the power device (IGBT / MOSFET), and even damage the drive circuit, the DC bus capacitor, and the power supply. Therefore, the drive signal interlocking circuit needs to be added to prevent this situation.

[0068] As shown in Figure 1 and Figure 2 , the T-type inverter drive signal interlocking circuit of the embodiment includes an inverting unit, a first NOT gate U1F that receives a first signal H and outputs a first inverted signal ; a second NOT gate U2F that receives a second signal L and outputs a second inverted signal ; a third NOT gate U3F that receives a third signal N and outputs a third inverted signal ; and a fourth NOT gate U4F that receives a fourth signal M and outputs a fourth inverted signal ;

[0069] A drive interlocking module includes a first AND gate drive unit, a first input end of which receives the first signal H, a second input end of which is connected with the output end of the second NOT gate U2F, and a third input end of which is connected with the output end of the third NOT gate U3F. The output end of the first AND gate drive unit outputs an upper tube drive signal D_H. The first AND gate drive unit receives the first signal H, the second inverted signal , and the third inverted signal , and performs logical AND operation to generate the upper tube drive signal D_H, which is used to control the opening and closing of the upper tube. The inverted signal refers to a signal that is completely opposite in phase (180 degrees apart) and completely opposite in logic (such as 0 and 1) to the original signal, and also represents the direct negation of the logic value.

[0070] A second AND gate driving unit, whose first input end receives the second signal L, whose second input end is connected with the output end of the first NOT gate U1F, and whose third input end is connected with the output end of the fourth NOT gate U4F, outputs the lower tube driving signal D_L at its output end. The second AND gate driving unit receives the second signal L, the first inverted signal and the fourth inverted signal and performs logical AND operation to generate the lower tube driving signal D_L, which is used to control the turn-on and turn-off of the lower tube.

[0071] As shown in Figure 2 the above scheme, taking the common collector T-type inverter as an example, the upper tube driving signal D_H used to drive the upper tube is controlled by the first signal H, the second inverted signal , the third inverted signal , the lower tube driving signal D_L used to drive the lower tube is controlled by the second signal L, the first inverted signal , the fourth inverted signal , the third signal N can directly drive the left middle tube, and the fourth signal M can directly drive the right middle tube. The logical control of the four power switching tubes of a single T-type inverter is shown in Table 1:

[0072] Table 1:

[0073]

[0074] As can be seen from Table 1, the T-type inverter driving signal interlocking circuit of the embodiment interlocks the first signal H, the second inverted signal , the third inverted signal to form the upper tube driving signal D_H, and interlocks the second inverted signal , the first inverted signal , the fourth inverted signal The interlocking forms a lower tube driving signal D_L. When the second signal L and the third signal N are low, the upper tube driving signal D_H can follow the change of the first signal H, and the upper tube is normally driven. When the first signal H and the fourth signal M are low, the lower tube driving signal D_L can follow the change of the second signal L, and the lower tube is normally driven. When the upper tube is normally driven, the lower tube driving signal D_L is low because the second signal L is low, even if the second signal L fluctuates, the lower tube driving signal D_L is still low when the first signal H is high, preventing the upper tube and the lower tube from being turned on at the same time. Similarly, when modulated by SPWM, the third signal N is low, and if the third signal N fluctuates to high, the upper tube driving signal D_H will be low, preventing the upper tube and the middle tube from being turned on at the same time. For the T-type inverter in the negative half cycle, the above-mentioned T-type inverter driving signal interlocking circuit can effectively ensure that the upper tube and the lower tube are not turned on at the same time in the positive half cycle, and the upper tube and the middle tube are not turned on at the same time; in the negative half cycle, the lower tube and the upper tube are not turned on at the same time, and the lower tube and the middle tube are not turned on at the same time.

[0075] As shown in Figure 1 The T-type inverter driving signal interlocking circuit further includes a signal delay device 1, which has an input end and an output end. The signal delay device 1 includes a resistor, a capacitor and a diode. The cathode of the diode is connected to the input end of the signal delay device 1, and the anode of the diode is connected to the output end of the signal delay device 1. One end of the resistor is connected to the cathode of the diode, and the other end of the resistor is connected to the anode of the diode. One end of the capacitor is connected to the anode of the diode, and the other end of the capacitor is grounded. The signal delay device 1 is essentially an RC filter in parallel with a reverse diode. The cathode of the diode is connected to the output end of the NOT gate, and the anode of the diode is connected to one input end of the AND gate. When the signal output by the NOT gate flips from low to high, the diode is reverse-biased and cut off. After passing through the signal delay device 1, the rising edge of the signal requires a time delay, because after the signal enters the input end of the signal delay device 1, it passes through the resistor and then charges the capacitor. When the capacitor is charged to a certain extent until the potential at the connection node of the capacitor and the resistor reaches a certain threshold (the input end of the AND gate can recognize it as high), the time for the capacitor to charge to the threshold is the signal delay time. When the signal output by the NOT gate flips from high to low, the capacitor begins to discharge, and the diode is forward-biased and conducts, accelerating the discharge. This causes a very small delay.

[0076] The output end of the first NOT gate U1F is connected to the second input end of the second AND gate driving unit through a signal delay device 1; the output end of the second NOT gate U2F is connected to the second input end of the first AND gate driving unit through a signal delay device 1; the output end of the third NOT gate U3F is connected to the third input end of the first AND gate driving unit through a signal delay device 1; and the output end of the fourth NOT gate U4F is connected to the third input end of the second AND gate driving unit through a signal delay device 1.

[0077] In this embodiment, signal delay units 1 are set at the output terminals of the first, second, third, and fourth NOT gates to delay the time for the low-level to flip to a high-level. The above transistor drive signal D_H=H& & and lower transistor drive signal For example, suppose H, , , All signals are high, and L is low. When the upper transistor needs to be turned off and the lower transistor turned on, the first signal H will change from high to low. When the signal changes from low to high, the second signal L will also change from low to high. If the lower transistor drive signal D_L has already received the high-level second signal L, and there is no signal delay unit 1 to delay it... When the signal flips to a high level, the lower transistor drive signal D_L outputs a high level, turning on the lower transistor. Since the upper transistor's turn-off takes time, not instantaneous, if the lower transistor turns on before the upper transistor is fully turned off, both transistors will be on simultaneously. This will generate huge capacitance spikes, severely damaging both the upper and lower transistors in the power switch cabinet, and potentially even other circuits in the inverter. Therefore, the lower transistor needs a delayed turn-on, hence the first inverted signal... After passing through signal delay unit 1, the signal is delayed for a period of time before being received by the second AND gate drive unit. At this time, the upper transistor has been completely turned off, and the lower transistor can be safely turned on, effectively ensuring the safety of the inverter.

[0078] The same applies to the upper tube and middle tube one, and the lower tube and middle tube two, so they will not be repeated here.

[0079] Example 2

[0080] This embodiment is a further optimization based on Embodiment 1, introducing the third signal N and the fourth signal M into the logic interlock control. For example... Figure 2 and Figure 3 As shown, the first AND gate driver unit includes AND gate 1 U1Y and AND gate 2 U2Y; the first input terminal of AND gate 1 U1Y is connected to the first input terminal of the first AND gate driver unit, and the second input terminal of AND gate 1 U1Y is connected to the second input terminal of the first AND gate driver unit; the first input terminal of AND gate 2 U2Y is connected to the output terminal of AND gate 1 U1Y, the second input terminal of AND gate 2 U2Y is connected to the third input terminal of the first AND gate driver unit, and the output terminal of AND gate 2 U2Y is connected to the output terminal of the first AND gate driver unit.

[0081] The second AND gate driving unit comprises an AND gate three U3Y and an AND gate four U4Y. The first input end of the AND gate three U3Y is connected with the first input end of the second AND gate driving unit, and the second input end of the AND gate three U3Y is connected with the second input end of the second AND gate driving unit. The first input end of the AND gate four U4Y is connected with the output end of the AND gate three U3Y, the second input end of the AND gate four U4Y is connected with the third input end of the second AND gate driving unit, the output end of the AND gate four U4Y is connected with the output end of the second AND gate driving unit.

[0082] As shown in Figure 3 , the T-type inverter driving signal interlocking circuit further comprises a fifth NOT gate U5F, a sixth NOT gate U6F, an AND gate five U5Y and an AND gate six U6Y.

[0083] The input end of the fifth NOT gate U5F is connected with the output end of the AND gate one U1Y, the output end of the fifth NOT gate U5F is connected with the first input end of the AND gate five U5Y, the second input end of the AND gate five U5Y receives the third signal N, and the output end of the AND gate five U5Y outputs the middle tube one driving signal D_N.

[0084] The input end of the sixth NOT gate U6F is connected with the output end of the AND gate three U3Y, the first input end of the AND gate six U6Y is connected with the output end of the sixth NOT gate U6F, the second input end of the AND gate six U6Y receives the fourth signal M, and the output end of the AND gate six U6Y outputs the middle tube two driving signal D_M.

[0085] The signal logic expression of the above-mentioned optimized T-type inverter driving signal interlocking circuit is shown in Table 2:

[0086] Table 2:

[0087]

[0088] Taking the T-type inverter as a common collector for example, at this time, the middle tube one is the left middle tube, the middle tube two is the right middle tube, the upper tube cannot be turned on at the same time as the middle tube one, and the lower tube cannot be turned on at the same time as the middle tube two. When the T-type inverter is in the positive half cycle, the second signal L is low, the middle tube one driving signal D_N=N& (L+H) is equivalent to D_N=N& (0+H)=N&H, and the middle tube two driving signal D_M=M& (L+H) is equivalent to D_M=M& (1+H)=M&H; when the T-type inverter is in the negative half cycle, the first signal H is low, the middle tube one driving signal D_N=N& (L+H) is equivalent to D_N=N& (L+1)=N&L, and the middle tube two driving signal D_M=M& (L+H) is equivalent to D_M=M& (1+H)=M&. ​​​​​​​ As can be seen, the middle tube one drive signal D_N and the middle tube two drive signal D_M change their respective logic expressions when the T-type inverter is in different states. For example, during the positive half cycle, the middle tube one drive signal D_N is controlled by the first signal H and the third signal N, and the middle tube two drive signal D_M is controlled by the first signal H and the fourth signal M, and is not controlled by the second signal L; during the negative half cycle, the middle tube one drive signal D_N is controlled by the second signal L and the third signal N, and the middle tube two drive signal D_M is controlled by the second signal L and the fourth signal M, and is not controlled by the first signal H. Thus, if the second signal L fluctuates to a high level during the positive half cycle, it will not cause the middle tube two drive signal D_M to output a low level and cause the middle tube two to be turned off. Similarly, if the first signal H fluctuates to a high level during the negative half cycle, it will not cause the middle tube one drive signal D_N to output a low level and cause the middle tube one to be turned off. In this way, the stable operation of the T-type inverter can be ensured.

[0089] As shown in Figure 3 , the T-type inverter drive signal interlocking circuit of the present embodiment further comprises two signal delay devices 1, the output end of the fifth NOT gate U5F is connected to the first input end of the AND gate five U5Y through a signal delay device 1; the output end of the sixth NOT gate U6F is connected to the first input end of the AND gate six U6Y through a signal delay device 1. Delaying the signals output by the fifth NOT gate U5F and the sixth NOT gate U6F can effectively prevent the upper tube and the middle tube one from being turned on at the same time, and the lower tube and the middle tube two from being turned on at the same time, thereby effectively ensuring the stable operation of the T-type inverter.

[0090] Embodiment Three

[0091] The present embodiment is a further optimization based on Embodiment One:

[0092] As shown in Figure 1 , Figure 2 and Figure 4 , specifically, as shown in Figure 1 , the first AND gate drive unit is internally provided as follows: the first AND gate drive unit comprises an AND gate one U1Y and an AND gate two U2Y, the first input end of the AND gate one U1Y is connected to the first input end of the first AND gate drive unit, the second input end of the AND gate one U1Y is connected to the second input end of the first AND gate drive unit, the first input end of the AND gate two U2Y is connected to the output end of the above-mentioned AND gate one U1Y, the second input end of the AND gate two U2Y is connected to the third input end of the first AND gate drive unit, and the output end of the AND gate two U2Y is connected to the output end of the first AND gate drive unit. In scheme one, the first signal H and the second inverted signal are first logically ANDed to obtain a result, and then the result is logically ANDed with the third inverted signal After performing a logical AND operation, the upper transistor drive signal D_H is obtained.

[0093] Or such as Figure 4 As shown, the internal configuration of the first AND gate driver unit can be as described in Scheme 2: The first AND gate driver unit includes AND gate 1 U1Y and AND gate 2 U2Y. The first input terminal of AND gate 1 U1Y is connected to the second input terminal of the first AND gate driver unit, and the second input terminal of AND gate 1 U1Y is connected to the third input terminal of the first AND gate driver unit. The first input terminal of AND gate 2 U2Y is connected to the output terminal of the aforementioned AND gate 1 U1Y, the second input terminal of AND gate 2 U2Y is connected to the first input terminal of the first AND gate driver unit, and the output terminal of AND gate 2 U2Y is connected to the output terminal of the first AND gate driver unit. Scheme 2 involves first connecting the second signal L with the third inverted signal... A logical AND operation is performed to obtain a result. Then, the result is combined with the first signal H to obtain the upper transistor drive signal D_H.

[0094] Specifically, such as Figure 1 As shown, the internal configuration of the second AND gate driver unit can be as described in Scheme 3: The second AND gate driver unit includes AND gate 3 U3Y and AND gate 4 U4Y. The first input terminal of AND gate 3 U3Y is connected to the first input terminal of the second AND gate driver unit, the second input terminal of AND gate 3 U3Y is connected to the second input terminal of the second AND gate driver unit, the first input terminal of AND gate 4 U4Y is connected to the output terminal of the aforementioned AND gate 3 U3Y, the second input terminal of AND gate 4 U4Y is connected to the third input terminal of the second AND gate driver unit, and the output terminal of AND gate 4 U4Y is connected to the output terminal of the second AND gate driver unit. Scheme 3 first connects the second signal L with the first inverted signal... Perform a logical AND operation to obtain a result, then combine the above result with the fourth inverted signal. After performing a logical AND operation, the lower transistor drive signal D_L is obtained.

[0095] Or such as Figure 4 As shown, the internal configuration of the second AND gate driver unit can be as described in Scheme 4: The second AND gate driver unit includes AND gate 3U3Y and AND gate 4U4Y. The first input terminal of AND gate 3U3Y is connected to the second input terminal of the second AND gate driver unit, the second input terminal of AND gate 3U3Y is connected to the third input terminal of the second AND gate driver unit, the first input terminal of AND gate 4U4Y is connected to the output terminal of the aforementioned AND gate 3U3Y, the second input terminal of AND gate 4U4Y is connected to the first input terminal of the second AND gate driver unit, and the output terminal of AND gate 4U4Y is connected to the output terminal of the second AND gate driver unit. Scheme 4 first inverts the first signal... With the fourth inverted signal A logical AND operation is performed to obtain a result. Then, the result is combined with the second signal L to obtain the lower transistor drive signal D_L.

[0096] like Figure 5 As shown, the third AND gate driver unit receives a third signal N at its first input terminal, its second input terminal is connected to the output terminal of the first NOT gate U1F, and its output terminal outputs a transistor drive signal D_N. The third AND gate driver unit receives the third signal N and a first inverted signal. A logical AND operation is then performed to generate the drive signal D_N for the first intermediate transistor, which is used to control the on and off of the first intermediate transistor. The third AND gate unit includes AND gate 9U9Y. The first input terminal of AND gate 9U9Y is connected to the first input terminal of the third AND gate drive unit, the second input terminal of AND gate 9U9Y is connected to the second input terminal of the third AND gate drive unit, and the output terminal of AND gate 9U9Y is connected to the output terminal of the third AND gate drive unit. As mentioned above, when the two intermediate transistors of the T-type inverter are configured with a common collector, intermediate transistor 1 is the left intermediate transistor; when the two intermediate transistors of the T-type inverter are configured with a common emitter, intermediate transistor 1 is the right intermediate transistor.

[0097] like Figure 5 As shown, the fourth AND gate driver unit receives the fourth signal M at its first input terminal, and its second input terminal is connected to the output terminal of the second NOT gate U2F. The output terminal of the fourth AND gate driver unit outputs the transistor two driving signal D_M. The fourth AND gate driver unit receives the fourth signal M and the second inverted signal. A logical AND operation is then performed to generate the second intermediate transistor drive signal D_M, which is used to control the on and off of the second intermediate transistor. This third AND gate unit includes AND gate + U10Y. The first input terminal of AND gate + U10Y is connected to the first input terminal of the fourth AND gate drive unit, the second input terminal of AND gate + U10Y is connected to the second input terminal of the fourth AND gate drive unit, and the output terminal of AND gate + U10Y is connected to the output terminal of the fourth AND gate drive unit. As mentioned earlier, when the two intermediate transistors of the T-type inverter are configured with a common collector, the second intermediate transistor is the right intermediate transistor; when the two intermediate transistors of the T-type inverter are configured with a common emitter, the second intermediate transistor is the left intermediate transistor.

[0098] As shown in Table 3 below, the signal logic expression of the drive signal interlock circuit in this embodiment is as follows:

[0099] Table 3:

[0100]

[0101] Taking a T-type inverter with a common collector as an example, in this case, the first intermediate transistor is the left intermediate transistor, and the second intermediate transistor is the right intermediate transistor. When the T-type inverter is in the positive half-cycle and outputting the positive DC bus, the second signal L is at a low level ( When the signal is high (D_L is low, and the lower transistor is normally off), the fourth signal M is high (the middle transistor is normally open), and the third signal N is complementary to the first signal H. When the first signal H is high, the third signal N is low. When the signal is high (intermediate transistor 1 is off), D_H=H, the upper transistor is on, D_N=0, D_L=0, and it will not be affected by the fluctuations of the second signal L or the third signal N, thus preventing the intermediate transistor 2 from turning on; when the first signal H is low ( When the upper transistor is high, the lower transistor is off, while the third signal N is high, and the middle transistor is on. If the second signal L or the third signal N fluctuates and becomes high when the upper transistor is on, D_H = 0. The upper transistor can be directly turned off due to this abnormal situation, avoiding the simultaneous on / off of the upper and lower transistors, or the simultaneous on / off of the upper and middle transistors. This is because the switching of power transistors is not instantaneous, but requires an extremely short nanosecond (ns) time. If D_H is not introduced to... Based on this judgment, it is highly likely that simultaneous conduction will occur at the instant the first signal H transitions from high to low. Therefore, this setting serves as a double safety measure.

[0102] When the T-type inverter outputs the DC bus midpoint, the first and second intermediate transistors are on, while the upper and lower transistors are off. At this time, the third signal N and the fourth signal M are high, the first signal H and the second signal L are low, the upper transistor drive signal D_H is low, the lower transistor drive signal D_L is low, D_N is high, and D_M is high.

[0103] When the T-type inverter outputs a negative DC bus, the upper transistor is off, the first intermediate transistor is normally open, and the second intermediate transistor and the lower transistor are alternately turned on. At this time, the first signal H is low (i.e., the upper transistor drive signal D_H is low), the third signal N is high (i.e., the intermediate transistor drive signal D_N is high), and the second signal L and the fourth signal M are complementary (i.e., when the second signal L is high, the fourth signal M is low, at which point the lower transistor drive signal D_L is high and the intermediate transistor drive signal D_M is low; when the second signal L is low, the fourth signal M is high, at which point the lower transistor drive signal D_L is low and the intermediate transistor drive signal D_M is high).

[0104] Example 4:

[0105] However, as shown in Table 3 of Embodiment 3, the driving signal D_N of the middle tube is N& However, during the positive half-cycle of the T-type inverter, the intermediate transistor 1 cannot be turned on simultaneously with the upper transistor. During the negative half-cycle, D_N2 must remain normally open. However, the logic expression of D_N2 shows that it is only controlled by the third signal N and the first signal H. If the first signal H fluctuates and becomes high, it will cause the intermediate transistor 1 drive signal D_N to output a low level, resulting in the intermediate transistor 1 being turned off, which is detrimental to the output of the T-type inverter. For the intermediate transistor 2 drive signal D_MD_N=M& Similarly.

[0106] This embodiment is based on the optimization of embodiment three, as shown in Figure 6 and Figure 7 This embodiment introduces the control of the lower tube in the logic control of the middle tube one drive signal D_N, and introduces the control of the upper tube in the logic control of the middle tube two drive signal D_M, to enhance the control of the middle tube one drive signal D_N and the middle tube two drive signal D_M.

[0107] Continue to take the signal definition mentioned in embodiment one as an example, that is, define the first signal as H, the second signal as L, the third signal as N, the fourth signal as M, the upper tube drive signal as D_H, the lower tube drive signal as D_L, the middle tube one drive signal as D_N, and the middle tube two drive signal as D_N.

[0108] The third input end of the third AND gate driving unit receives the second signal L, and the internal setting of the third AND gate driving unit can be as scheme five: the third AND gate driving unit includes AND gate five U5Y, AND gate six U6Y and fifth NOT gate U5F, the first input end of AND gate five U5Y is connected with the second input end of the third AND gate driving unit, and the second input end of AND gate five U5Y is connected with the third input end of the third AND gate driving unit; the input end of fifth NOT gate U5F is connected with the output end of AND gate five U5Y; the first input end of AND gate six U6Y is connected with the first input end of the third AND gate driving unit, and the output end of fifth NOT gate U5F is connected with the second input end of AND gate six U6Y through a signal delay device 1, and the output end of AND gate six U6Y is connected with the output end of the third AND gate driving unit. Through the above setting of the logic gate, the second signal L is first ANDed with the first inverted signal After the logic AND operation, the inverted operation is performed to obtain , and then the logic AND operation with the third signal N is performed to obtain the middle tube one drive signal D_N=N&( +H).

[0109] The third input end of the fourth AND gate driving unit receives the first signal H, and the internal setting of the fourth AND gate driving unit can be as scheme six: the fourth AND gate driving unit includes AND gate seven U7Y, AND gate eight U8Y and sixth NOT gate U6F.

[0110] The first input end of AND gate seven U7Y is connected with the second input end of the fourth AND gate driving unit, and the second input end of AND gate seven U7Y is connected with the third input end of the fourth AND gate driving unit; the input end of sixth NOT gate U6F is connected with the output end of AND gate seven U7Y; the first input end of AND gate eight U8Y is connected with the first input end of the fourth AND gate driving unit, and the output end of sixth NOT gate U6F is connected with the second input end of AND gate eight U8Y through a signal delay device 1, and the output end of AND gate eight U8Y is connected with the output end of the fourth AND gate driving unit. Through the above setting of the logic gate, the second inverted signal After performing a logical AND operation with the first signal H, and then performing an inversion operation, we obtain... Then, a logical AND operation is performed with the fourth signal M to obtain the second-stage transistor drive signal D_M = M & (L + ... ).

[0111] It is worth noting that in this fourth embodiment, if the T-type inverter is configured with a common collector, then the first middle transistor is the right middle transistor, and the second middle transistor is the left middle transistor. The upper transistor and the second middle transistor cannot be turned on simultaneously, and the lower transistor and the first middle transistor cannot be turned on simultaneously. If the T-type inverter is configured with a common emitter, then the first middle transistor is the left middle transistor, and the second middle transistor is the right middle transistor. In this case, the upper transistor and the second middle transistor cannot be turned on simultaneously, and the lower transistor and the first middle transistor cannot be turned on simultaneously. The interlocking relationship between the upper transistor drive signal D_H, the lower transistor drive signal D_L, the first middle transistor drive signal D_N, and the second middle transistor drive signal D_M is shown in Table 4.

[0112] As shown in Table 4 below, the signal logic expression of the drive signal interlock circuit in this embodiment two is as follows:

[0113] Table 4:

[0114]

[0115] Taking a T-type inverter with a common collector configuration as an example, in this configuration, transistor 1 is the right transistor, transistor 2 is the left transistor, the upper transistor cannot be turned on simultaneously with transistor 2, and the lower transistor cannot be turned on simultaneously with transistor 1. When the T-type inverter is in the positive half-cycle, the second signal LL is low, and the drive signal D_N for transistor 1 is D_N = N&( +H) is equivalent to D_N=N&(1+H)=N&H, and the driving signal D_M of the middle tube is D_M=M&(L+H). This is equivalent to D_M = M & (0 + ... =M& When the T-type inverter is in the negative half-cycle, the first signal H is low, and the intermediate transistor drive signal D_N = N& ( +H) is equivalent to D_N=N&( +0) = N& The driving signal of the middle tube is D_M = M & (L + ) is equivalent to D_M = M & (L + 1) = M & L. Thus, it can be seen that the logic expression of the middle tube one drive signal D_N and the middle tube two drive signal D_M changes when the T-type inverter is in different states. For example, during the positive half cycle, the middle tube one drive signal D_N is controlled only by the first signal H and the third signal N, and is not controlled by the fluctuation of the second signal L; during the negative half cycle, the middle tube two drive signal D_M is controlled only by the second signal L and the fourth signal M, and is not controlled by the first signal H. Thus, if the second signal L fluctuates to a high level during the positive half cycle, it will not cause the middle tube one drive signal D_N to output a low level to cause the middle tube one (at this time, the right middle tube) to turn off. Similarly, during the negative half cycle, if the first signal H fluctuates to a high level, it will not cause the middle tube two drive signal D_M to output a low level to cause the middle tube two (at this time, the left middle tube) to turn off. In this way, the stable operation of the T-type inverter can be ensured.

[0116] Embodiment five:

[0117] An inverter, comprising at least one phase T-type inverter circuit, the T-type inverter drive signal interlocking circuit of any one of the embodiments one to four, and the T-type inverter drive signal interlocking circuit is connected to and drives the T-type inverter circuit.

[0118] A large number of first, second, third, etc. input terminals are used in the present application, and these pronouns do not constitute a specific limitation on the position of the input terminals of each AND gate. Adding conventional passive components between the connections of different logic gates is considered an equivalent solution of the present application and falls within the protection scope of the present application. The reference numerals of the first NOT gate U1F, the second NOT gate U2F, the third NOT gate U3F, the fourth NOT gate U4F, the fifth NOT gate U5F, and the sixth NOT gate U6F in the drawings and the description of the drawings do not mean that they are integrated on one NOT gate chip. The first to sixth NOT gates can be taken from different NOT gate chips. Similarly, the reference numerals of the AND gate one U1Y, the AND gate two U2Y, the AND gate three U3Y, the AND gate four U4Y, the AND gate five U5Y, the AND gate six U6Y, the AND gate seven U7Y, the AND gate eight U8Y, the AND gate nine U9Y, and the AND gate ten U10Y in the drawings and the description of the drawings do not mean that they are integrated on one AND gate chip. The first to tenth AND gates can be taken from different multi-input AND gate chips.

[0119] In addition, in the drawings of the present application, the lines with dots represent that the lines are connected together. The lines without dots represent that the lines are not connected. Reference is made to the design of the circuit schematic diagram.

[0120] It needs to be particularly pointed out that in actual application, the upper tube driving signal, the lower tube driving signal, the middle tube one driving signal and the middle tube two driving signal of the T-type inverter driving signal interlocking circuit of the application will pass through an optical coupling isolator and a transistor and then be sent into the T-type inverter. The connection of the T-type inverter driving signal interlocking circuit and the T-type inverter shown in the drawings of the specification of the application is only schematic.

[0121] The above embodiments are only preferred embodiments of the utility model, and do not limit the protection scope of the utility model, so that: equivalent changes made according to the structure, shape, principle of the utility model should be covered in the protection scope of the utility model.

[0122] It is understood that the structure, proportion, size, etc. shown in the drawings of the specification are only used to cooperate with the content disclosed in the specification for understanding and reading by those skilled in the art, and are not used to limit the limiting conditions of the utility model that can be implemented, so they do not have technical substantive significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effect and purpose that the utility model can produce, should still fall within the scope covered by the technical content disclosed by the utility model. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" in the specification are only for clear description, and not for limiting the scope of the utility model that can be implemented. The change or adjustment of the relative relationship, without substantially changing the technical content, is also considered as the scope of the utility model that can be implemented.

[0123] It also needs to be pointed out that when an element is referred to as "fixed on" or "disposed on" another element, it can be directly on another element or there can be a middle element. When an element is referred to as "connected" to another element, it can be directly connected to another element or indirectly connected to another element through a middle element.

[0124] In addition, the description of "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

Claims

1. A T-type inverter drive signal interlock circuit that receives a first signal, a second signal, a third signal, a fourth signal, the circuit comprising: Comprising: an inverting unit, comprising: a first NOT gate (U1F) receiving the first signal and outputting a first inverted signal; a second NOT gate (U2F) receiving the second signal and outputting a second inverted signal; a third NOT gate (U3F) receiving the third signal and outputting a third inverted signal; a fourth NOT gate (U4F) receiving the fourth signal and outputting a fourth inverted signal; a driving interlocking module, comprising: a first AND gate driving unit, a first input end of which receives the first signal, a second input end of which is connected with an output end of the second NOT gate (U2F), and a third input end of which is connected with an output end of the third NOT gate (U3F), an output end of the first AND gate driving unit outputting an upper tube driving signal; a second AND gate driving unit, a first input end of which receives the second signal, a second input end of which is connected with an output end of the first NOT gate (U1F), and a third input end of which is connected with an output end of the fourth NOT gate (U4F), an output end of the second AND gate driving unit outputting a lower tube driving signal.

2. The T-1 inverter drive signal interlock circuit of claim 1, wherein, The first AND gate driving unit comprises: an AND gate one (U1Y) and an AND gate two (U2Y); a first input end of the AND gate one (U1Y) is connected with the first input end of the first AND gate driving unit, and a second input end of the AND gate one (U1Y) is connected with the second input end of the first AND gate driving unit; a first input end of the AND gate two (U2Y) is connected with an output end of the AND gate one (U1Y), a second input end of the AND gate two (U2Y) is connected with the third input end of the first AND gate driving unit, and an output end of the AND gate two (U2Y) is connected with the output end of the first AND gate driving unit; The second AND gate driving unit comprises: an AND gate three (U3Y) and an AND gate four (U4Y); a first input end of the AND gate three (U3Y) is connected with the first input end of the second AND gate driving unit, and a second input end of the AND gate three (U3Y) is connected with the second input end of the second AND gate driving unit; a first input end of the AND gate four (U4Y) is connected with an output end of the AND gate three (U3Y), a second input end of the AND gate four (U4Y) is connected with the third input end of the second AND gate driving unit, and an output end of the AND gate four (U4Y) is connected with the output end of the second AND gate driving unit.

3. The T-1 inverter drive signal interlock circuit of claim 2, wherein, Further comprising: a fifth NOT gate (U5F), a sixth NOT gate (U6F), an AND gate five (U5Y) and an AND gate six (U6Y); an input end of the fifth NOT gate (U5F) is connected with an output end of the AND gate one (U1Y), an output end of the fifth NOT gate (U5F) is connected with a first input end of the AND gate five (U5Y), a second input end of the AND gate five (U5Y) receives the third signal, and an output end of the AND gate five (U5Y) outputs a middle tube one driving signal; An input terminal of the sixth NOT gate (U6F) is connected with an output terminal of the AND gate three (U3Y), a first input terminal of the AND gate six (U6Y) is connected with an output terminal of the sixth NOT gate (U6F), a second input terminal of the AND gate six (U6Y) receives the fourth signal, and an output terminal of the AND gate six (U6Y) outputs the middle tube two driving signal.

4. The T-1 inverter drive signal interlock circuit of claim 1, wherein, The first AND gate driving unit comprises an AND gate one (U1Y) and an AND gate two (U2Y); A first input terminal of the AND gate one (U1Y) is connected with a second input terminal of the first AND gate driving unit, and a second input terminal of the AND gate one (U1Y) is connected with a third input terminal of the first AND gate driving unit; A first input terminal of the AND gate two (U2Y) is connected with an output terminal of the AND gate one (U1Y), a second input terminal of the AND gate two (U2Y) is connected with a first input terminal of the first AND gate driving unit, and an output terminal of the AND gate two (U2Y) is connected with an output terminal of the first AND gate driving unit.

5. The T-1 inverter drive signal interlock circuit of claim 1, wherein, The second AND gate driving unit comprises an AND gate three (U3Y) and an AND gate four (U4Y); A first input terminal of the AND gate three (U3Y) is connected with a second input terminal of the second AND gate driving unit, and a second input terminal of the AND gate three (U3Y) is connected with a third input terminal of the second AND gate driving unit; A first input terminal of the AND gate four (U4Y) is connected with an output terminal of the AND gate three (U3Y), a second input terminal of the AND gate four (U4Y) is connected with a first input terminal of the second AND gate driving unit, and an output terminal of the AND gate four (U4Y) is connected with an output terminal of the second AND gate driving unit.

6. The T-1 inverter drive signal interlock circuit of claim 1, wherein, Further comprising: a third AND gate driving unit and a fourth AND gate driving unit; The third AND gate driving unit, a first input terminal of which receives the third signal, a second input terminal of which is connected with an output terminal of the first NOT gate (U1F), and an output terminal of which outputs the middle tube one driving signal; The fourth AND gate driving unit, a first input terminal of which receives the fourth signal, a second input terminal of which is connected with an output terminal of the second NOT gate (U2F), and an output terminal of which outputs the middle tube two driving signal.

7. The T-1 inverter drive signal interlock circuit of claim 6, wherein, The third AND gate driving unit comprises an AND gate five (U5Y), an AND gate six (U6Y) and a fifth NOT gate (U5F); A first input terminal of the AND gate five (U5Y) is connected with an output terminal of the first NOT gate (U1F), and a second input terminal of the AND gate five (U5Y) receives the second signal; An input terminal of the fifth NOT gate (U5F) is connected with an output terminal of the AND gate five (U5Y); A first input terminal of the AND gate six (U6Y) receives the third signal, a second input terminal of the AND gate six (U6Y) is connected with an output terminal of the fifth NOT gate (U5F), and an output terminal of the AND gate six (U6Y) outputs the middle tube one driving signal; The fourth AND gate driving unit comprises an AND gate seven (U7Y), an AND gate eight (U8Y) and a sixth NOT gate (U6F); The first input end of the AND gate seven (U7Y) is connected with the output end of the second NOT gate (U2F), and the second input end of the AND gate seven (U7Y) receives the first signal; the input end of the sixth NOT gate (U6F) is connected with the output end of the AND gate seven (U7Y); The first input end of the AND gate eight (U8Y) receives the fourth signal, the second input end of the AND gate eight (U8Y) is connected with the output end of the sixth NOT gate (U6F), and the output end of the AND gate eight (U8Y) outputs the middle tube two driving signal.

8. The T-rectifier drive signal interlock circuit of any one of claims 1-7, wherein, Further comprising a signal delay device (1), the signal delay device (1) has an input end and an output end, the signal delay device (1) comprises a resistance, a capacitor and a diode; the cathode of the diode is connected with the input end of the signal delay device (1), and the anode of the diode is connected with the output end of the signal delay device (1); one end of the resistance is connected with the cathode of the diode, the other end of the resistance is connected with the anode of the diode, one end of the capacitor is connected with the anode of the diode, and the other end of the capacitor is grounded; The output end of the first NOT gate (U1F) is connected to the second input end of the second AND gate driving unit through a signal delay device (1); The output end of the second NOT gate (U2F) is connected to the second input end of the first AND gate driving unit through a signal delay device (1); The output end of the third NOT gate (U3F) is connected to the third input end of the first AND gate driving unit through a signal delay device (1); The output end of the fourth NOT gate (U4F) is connected to the third input end of the second AND gate driving unit through a signal delay device (1).

9. The T-1 inverter drive signal interlock circuit of claim 3, wherein, Further comprising a signal delay device (1), the signal delay device (1) has an input end and an output end, the signal delay device (1) comprises a resistance, a capacitor and a diode; the cathode of the diode is connected with the input end of the signal delay device (1), and the anode of the diode is connected with the output end of the signal delay device (1); one end of the resistance is connected with the cathode of the diode, the other end of the resistance is connected with the anode of the diode, one end of the capacitor is connected with the anode of the diode, and the other end of the capacitor is grounded; The output end of the first NOT gate (U1F) is connected to the second input end of the second AND gate driving unit through a signal delay device (1); The output end of the second NOT gate (U2F) is connected to the second input end of the first AND gate driving unit through a signal delay device (1); The output end of the third NOT gate (U3F) is connected to the third input end of the first AND gate driving unit through a signal delay device (1); The output end of the fourth NOT gate (U4F) is connected to the third input end of the second AND gate driving unit through a signal delay device (1). The output end of the fifth NOT gate (U5F) is connected to the first input end of the AND gate five (U5Y) through a signal delay device (1); The output end of the sixth NOT gate (U6F) is connected to the first input end of the AND gate six (U6Y) through a signal delay device (1).

10. An inverter comprising at least one phase T-type inverter circuit, characterized by The T-type inverter drive signal interlock circuit according to any one of claims 1 to 9 is included, and the T-type inverter drive signal interlock circuit is connected to and drives the T-type inverter circuit.

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