Back-to-back type folded and stacked high-integration-level OECT circuit

Abstract

The invention discloses a back-to-back type folded and stacked high-integration-level OECT circuit. The circuit comprises an organic electrochemical transistor OECT, a phase inverter, a NAND gate and a NOR gate, wherein the OECT, the phase inverter, the NAND gate and the NOR gate are packaged on the substrate through the electrode layer, the semiconductor active layer, the electrolyte layer, the gate layer, the through hole, the conductive slurry and the packaging layer, so that a high-integration-level OECT circuit is obtained; in the packaging process, the sampling back-to-back folding and stacking structure breaks through the limitation of plane integration, and three-dimensional high-density arrangement of the OECT device and the circuit thereof is realized in a unit projection area.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and more particularly relates to a high-integration OECT circuit with back-to-back folding stacking. BACKGROUND

[0002] As a new emerging semiconductor device, organic electrochemical transistors (OECTs) have shown great potential in applications such as biosensing, neuromorphic computing, wearable electronics, and flexible display, due to their unique advantages of low operating voltage, high transconductance, biocompatibility, and ion-electron coupling effect. However, a core bottleneck for OECT technology to move from the laboratory to large-scale commercial applications lies in the difficulty of effectively improving the integration density.

[0003] The integration density of traditional OECT circuits, whether based on planar layout or simple vertical stacking, is mainly limited in two dimensions: first, the planar area of the substrate, and second, the complexity of the process and the reliability of the interlayer interconnection. First, in terms of planar layout, in order to improve the functional complexity of the circuit, more OECT units and their interconnecting wires must be arranged on the limited substrate area. This inevitably leads to problems such as crowded wiring, increased signal crosstalk, and increased parasitic capacitance / resistance. When the device density reaches a certain level, further reducing the device spacing or line width and spacing will face huge process challenges and performance degradation risks. Although three-dimensional integration is an effective way to break through the limitations of two-dimensional planar, existing technologies mostly use lamination or layer-by-layer printing / lithography to build multi-layer structures. This method usually requires complex interlayer alignment and via etching and filling processes to achieve electrical connection between different functional layers. This not only increases the manufacturing cost and process steps, but also introduces a large number of vertical interconnections, which are often the weak link of circuit reliability and are prone to failure due to stress or long-term use. Second, the structural design of existing OECT devices usually only utilizes a single surface (front side) of the substrate. The back surface of the substrate is idle in most designs, which wastes valuable space resources.

[0004] Therefore, there is an urgent need in the art for an innovative OECT circuit architecture and preparation technology that can fundamentally break through the existing two-dimensional planar integration density limit without significantly increasing the process complexity and sacrificing device reliability, and efficiently utilize all available spatial dimensions. SUMMARY

[0005] The present application aims to overcome the shortcomings of the prior art and provide a high-integration OECT circuit with back-to-back folding stacking, which breaks through the planar integration limit through a back-to-back folding stacking structure and realizes three-dimensional high-density arrangement of OECT devices and their circuits in a unit projection area to solve the problem of low integration of OECT circuits in the prior art.

[0006] To achieve the above-mentioned objectives, the present invention provides a highly integrated OECT circuit with back-to-back folded stacking, characterized in that it includes: an organic electrochemical transistor (OECT), an inverter, a NAND gate, and a NOR gate.

[0007] The OECT, inverter, NAND gate, and NOR gate are packaged on the substrate through an electrode layer, a semiconductor active layer, an electrolyte layer, a gate layer, a via, a conductive paste, and a packaging layer to obtain a highly integrated OECT circuit.

[0008] Wherein, the substrate is a foldable and stackable flexible substrate;

[0009] The electrode layers include an OECT source layer, an OECT drain layer, an inverter first electrode layer, an inverter second electrode layer, an inverter third electrode layer, a NAND gate first electrode layer, a NAND gate second electrode layer, a NAND gate third electrode layer, a NAND gate fourth electrode layer, a NAND gate fifth electrode layer, a NOR gate first electrode layer, a NOR gate second electrode layer, a NOR gate third electrode layer, a NOR gate fourth electrode layer, and a NOR gate fifth electrode layer;

[0010] In this configuration, the source layer of the OECT is grounded, and the drain layer is connected to the power supply. The first electrode layer of the inverter is grounded, the third electrode layer is connected to the power supply, and the second electrode layer is the voltage output. The first and fourth electrode layers of the NAND gate are connected via electrode connection vias, the second electrode layer is the voltage output, the third electrode layer is connected to the power supply, the fifth electrode layer is grounded, and the third and fourth gate layers are the voltage inputs of the NAND gate. The first and fourth electrode layers of the NOR gate are connected via electrode connection vias, the second electrode layer is the output, the third electrode layer is grounded, the fifth electrode layer is connected to the power supply, and the fifth and sixth gate layers are the voltage inputs of the NOR gate.

[0011] The semiconductor active layer includes an n-type semiconductor active layer and a p-type semiconductor active layer;

[0012] Specifically, an n-type semiconductor active layer is disposed between the drain layer and the source layer of the OECT, isolating them; an n-type semiconductor active layer is disposed between the first electrode layer and the second electrode layer of the inverter, is disposed between the first electrode layer and the second electrode layer of the NAND gate, is disposed between the fourth electrode layer and the fifth electrode layer of the NAND gate, and is disposed between the second electrode layer and the third electrode layer of the NOR gate; additionally, a p-type semiconductor active layer is disposed between the second electrode layer and the third electrode layer of the inverter, is disposed between the second electrode layer and the third electrode layer of the NAND gate, is disposed between the first electrode layer and the second electrode layer of the NOR gate, and is disposed between the fourth electrode layer and the fifth electrode layer of the NOR gate.

[0013] The electrolyte completely covers the working areas of the OECT, inverter, NAND gate, and NOR gate, wherein the n-type and p-type OECTs within the NAND gate and NOR gate share the electrolyte through electrolyte interconnection vias;

[0014] The gate layers are sequentially numbered from the first gate layer to the sixth gate layer, wherein the first gate layer is the voltage input terminal of the OECT, the second gate layer is the voltage input terminal of the inverter, the third gate layer is the first voltage input terminal of the NAND gate, the fourth gate layer is the second voltage input terminal of the NAND gate, the fifth gate layer is the first voltage input terminal of the NOR gate, and the sixth gate layer is the second voltage input terminal of the NOR gate.

[0015] The vias include electrolyte interconnect vias and electrode connection vias;

[0016] The encapsulation layer fully encapsulates OECT, inverters, NAND gates, and NOR gates;

[0017] The conductive paste is a printable paste with high conductivity, and it is printed on the electrode through-holes.

[0018] The objective of this invention is achieved as follows:

[0019] This invention discloses a highly integrated OECT circuit with a back-to-back folded stacking structure, comprising: an organic electrochemical transistor (OECT), an inverter, a NAND gate, and a NOR gate; wherein the OECT, inverter, NAND gate, and NOR gate are packaged on a substrate through an electrode layer, a semiconductor active layer, an electrolyte layer, a gate layer, a via, a conductive paste, and a packaging layer to obtain a highly integrated OECT circuit; during the packaging process, the back-to-back folded stacking structure breaks through the limitations of planar integration, achieving a three-dimensional high-density arrangement of OECT devices and their circuits within a unit projected area.

[0020] Meanwhile, the highly integrated OECT circuit with back-to-back folded stacking of the present invention also has the following beneficial effects:

[0021] (1) Achieving highly integrated OECT devices: This technology unlocks the effective integration space on the reverse side of the substrate through a back-to-back design. Combined with folded stacking technology, it realizes the spatial arrangement of functional units, enabling a geometric increase in device density per unit projected area. Simultaneously, each device can perform its function independently without interference, laying the foundation for the fabrication of complex OECT circuits. Furthermore, the increased integration directly reduces the consumption of single-wafer materials, simplifies the manufacturing process, and effectively reduces manufacturing costs.

[0022] (2) Achieving highly integrated OECT circuits: This technology fully unleashes the layout potential of the substrate through an integration strategy of folded stacking and back-to-back design. Like performing "folding magic," it allows the substrate to accommodate several times the number of OECT devices with the same projected area. Its innovation lies in the fact that complex logic circuits can be realized through three-dimensional construction using only the planar size of a conventional OECT, thus achieving a dual breakthrough in integration density and functional hierarchy.

[0023] (3) Optimized electrical performance and improved operating efficiency: Back-to-back and stacked structures help optimize the electric field distribution and reduce parasitic capacitance and electrical crosstalk between devices, thereby significantly improving the operating stability and noise margin of the inverter. By precisely controlling the interlayer distance and material interface characteristics, the coupling and transport of ions / electrons in the channel can be efficiently managed. More importantly, the increased integration density leads to a significant reduction in interconnect lines, thereby effectively reducing the overall dynamic power consumption and signal transmission delay of the circuit. On this basis, the structure supports lower operating voltage and faster switching response, providing a high-efficiency solution for low-power applications such as mobile devices and implantable devices.

[0024] (4) Extreme compression of physical space and miniaturization: This design significantly reduces the physical space required for the device, providing a feasible integration solution for highly miniaturized electronic systems. It is particularly suitable for size-sensitive applications such as wearable devices, implantable medical devices, and micro-sensing nodes, and helps to realize the development and integration of thinner, more compact, and flexible electronic products. Attached Figure Description

[0025] Figure 1 This is a simplified diagram of the OECT circuit provided in the embodiments of the present invention, including OECT, inverter, NAND gate and NOR gate.

[0026] Figure 2 This is a flowchart illustrating the fabrication process of a highly integrated OECT (Optical Electron Device) with back-to-back folded stacking, as provided in an embodiment of the present invention.

[0027] Figure 3 This is a side view of a highly integrated OECT structure with back-to-back folding and stacking provided in an embodiment of the present invention.

[0028] Figure 4 This is a flowchart illustrating the fabrication process of a highly integrated inverter circuit with back-to-back folded stacking, as provided in an embodiment of the present invention.

[0029] Figure 5 This is a side view of a highly integrated inverter circuit with back-to-back folded stacking, provided as an embodiment of the present invention.

[0030] Figure 6 This is a flowchart illustrating the fabrication process of a highly integrated NAND gate circuit with back-to-back folded stacking, as provided in an embodiment of the present invention.

[0031] Figure 7 This is a side view of a highly integrated NAND gate circuit with back-to-back folding and stacking, as provided in an embodiment of the present invention.

[0032] Figure 8 This is a flowchart illustrating the fabrication process of a highly integrated NOR gate circuit with back-to-back folded stacking, as provided in an embodiment of the present invention.

[0033] Figure 9 This is a side view of a highly integrated NOR gate circuit that is stacked back-to-back in an embodiment of the present invention.

[0034] Figure 10 The transfer characteristic curves and transconductance curves of p / n type OECT provided in the embodiments of the present invention are shown in (a) for p type OECT and (b) for n type OECT.

[0035] Figure 11 The diagram shows the test performance of the OECT circuit provided in the embodiment of the present invention. (a) is an inverter, and (b) is a NAND gate and a NOR gate. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0037] Example

[0038] In this embodiment, as Figure 1 As shown, this invention discloses a highly integrated OECT circuit with back-to-back folded stacking, specifically including an OECT, an inverter, a NAND gate, and a NOR gate. Figures 2-10As shown, it specifically includes: a flexible substrate 1, an OECT source layer 2, p-type semiconductor active layers 3, 11, 19, 20, 40 and 54, an OECT drain layer 4, solid electrolyte layers 5, 13, 22, 23, 35, 45, 46 and 58, a first gate layer 6, encapsulation layers 7, 15, 26, 27, 36, 49, 50 and 59, an inverter first electrode layer 8, n-type semiconductor active layers 9, 17, 31, 42 and 43, an inverter second electrode layer 10, an inverter third electrode layer 12, a second gate layer 14, a NAND gate first electrode layer 16, a NAND gate second electrode layer 18, a NAND gate third electrode layer 21, a third gate layer 24, and so on. 25. Four gate layers, 28. NAND gate internal inverter, 29. NAND gate internal p-type OECT, 30. NAND gate fourth electrode layer, 32. NAND gate fifth electrode layer, 33. NAND gate electrode via, 34. NAND gate electrolyte via, 37 and 60. Conductive paste, 38. NAND gate internal n-type OECT, 39. NOR gate first electrode layer, 41. NOR gate second electrode layer, 44. NOR gate third electrode layer, 47. Fifth gate layer, 48. Sixth gate layer, 51. NOR gate internal inverter, 52. NOR gate internal n-type OECT, 53. NOR gate fourth electrode layer, 55. NOR gate fifth electrode layer, 56. NOR gate electrode via, 57. NOR gate electrolyte via, 61. NOR gate p-type OECT.

[0039] For OECT, such as Figure 2 and 3 As shown, a patterned source layer is disposed on a flexible substrate, a semiconductor active layer is patterned on the source layer, a patterned drain layer is located above the semiconductor active layer and perpendicular to the source, and a patterned electrolyte layer covers the three-layer structure; a first gate layer is disposed on the electrolyte layer and directly opposite the semiconductor active layer; a packaging layer completely encapsulates the aforementioned layers; wherein, the source is grounded (GND), and the drain is connected to a constant voltage power supply terminal (V). D The gate is connected to the voltage input terminal (V). G ).

[0040] For inverters, such as Figure 4 and 5 As shown, the inverter is composed of n-type and p-type OECTs stacked vertically, and the stacking order of the two can be interchanged; starting from the flexible substrate, it consists of the following vertically stacked layers: a first electrode layer serving as the source of the n-type OECT and grounded, a second electrode layer serving as the common drain of the n / p-type OECTs, and a p-type OECT source connected to a constant voltage (V). DD The third electrode layer is separated from each other by corresponding n-type or p-type semiconductor active layers; a patterned electrolyte layer covers the semiconductor active layer, and a second gate layer is provided on its surface facing the active layer. This second gate layer serves as the voltage input terminal (V). IN The second electrode layer serves as the voltage output terminal (V). OUTThe outermost layer of the device is completely covered by the encapsulation layer.

[0041] For NAND gates, such as Figure 6 and 7 As shown, the NAND gate circuit is integrated on a flexible substrate and includes an inverter, an n-type OECT, and a p-type OECT. The inverter and p-type OECT are located on the front side of the substrate, and the second electrode layer of the inverter is connected to the source layer of the p-type OECT to form the second electrode layer of the NAND gate. The third electrode layer of the inverter is connected to the drain layer of the p-type OECT to form the third electrode layer of the NAND gate. The n-type OECT is located on the back side of the substrate, arranged opposite to the p-type OECT. The p-type and n-type OECTs are interconnected via electrolyte vias and share a common gate. The drain of the n-type OECT (the fourth electrode layer of the NAND gate) is connected to the first electrode layer of the inverter (the first electrode layer of the NAND gate) via an electrode via. The fifth electrode layer of the NAND gate is grounded, and the third electrode layer of the NAND gate is connected to the power supply voltage (V). DD The inverter gate layer (third gate layer) within the NAND gate is the first input terminal (V). IN1 The second input terminal (V) is the shared gate layer (fourth gate layer) of the n / p type OECT gate within the NAND gate. IN2 The second electrode layer of the NAND gate serves as the output terminal (V). OUT The outermost layer of the device is completely covered by the encapsulation layer.

[0042] For NOR gates, such as Figure 8 and 9 As shown, the NOR gate circuit is integrated on a flexible substrate and includes an inverter, an n-type OECT, and a p-type OECT. The inverter and the n-type OECT are located on the front side of the substrate, and the second electrode layer of the inverter is interconnected with the source layer of the n-type OECT as the second electrode layer of the NOR gate. The third electrode layer of the inverter is interconnected with the drain of the n-type OECT as the third electrode layer of the NOR gate. The p-type OECT is located on the back side of the substrate, arranged opposite to the n-type OECT. The p-type and n-type OECTs are interconnected via electrolyte vias and share a common gate layer. The source of the p-type OECT (the fourth electrode layer of the NOR gate) is connected to the first electrode layer of the inverter (the first electrode layer of the NOR gate) via an electrode via. The third electrode layer of the NOR gate is grounded (GND); the fifth electrode layer of the NOR gate is connected to a power supply voltage (V). DD The inverter gate layer (fifth gate layer) within the NOR gate serves as the first input terminal (V). IN1 ), or the common gate layer (sixth gate layer) of the non-gate n / p type OECT is used as the second input terminal (V IN2 The second electrode layer of the NOR gate serves as the output terminal (V). OUT The outermost layer of the device is completely covered by the encapsulation layer.

[0043] The substrate is a 5 μm thick flexible substrate that can be freely folded;

[0044] The n-type semiconductor active layer is an organic composite ion-electron semiconductor material with electron transport capability;

[0045] The p-type semiconductor active layer is an organic composite ion-electron semiconductor material with hole transport capability;

[0046] The electrolyte layer is a solid electrolyte that combines high ion mobility and high ion concentration, and has excellent patterning capabilities.

[0047] Furthermore, the substrate is one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), polyurethane (PU), or polyimide (PI).

[0048] Furthermore, the source and drain electrodes are made of one of gold, platinum, carbon paste, carbon nanotubes, or graphene, and the electrode width ranges from 20 to 100 μm and the thickness ranges from 40 to 200 nm.

[0049] Furthermore, the n-type semiconductor active layer is an organic composite ion-electron semiconductor material with good electron transport properties, mainly including: poly(benzimidazole benzopyrroline) (BBL), poly(2,5-dipentanediol-3,6-di(thiophene-2-yl)-2,5-dihydropyrrolo[3,4-c]pyrrole-1,4-dione) (Homo-gDPP), poly(3-hexylthiophene) (P3HT), poly(3-pentylthiophene) (P3PT), poly(3-octylthiophene) (P3OT), poly(3-phenylthiophene) (P3PhT), poly(2,5-dihexylthiophene) (PDHT), poly(pyrrole) (PPy), poly(thiophene-ethylene) (PTV), diethyl perylene glycol (DEPDI), dibutyl perylene glycol (DBPDI), and poly(thiophene-thiophene copolymer) (Polythiophene Materials such as copolymers, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonic acid) (PEDOT:PSS).

[0050] Furthermore, the p-type semiconductor active layer is an organic composite ion-electron semiconductor material with good hole conductivity, mainly including: poly(2,5-dipentanediol-3,6-bis(thiophene-2-yl)-2,5-dihydropyrrolo[3,4-c]pyrrolo-1,4-dione-alternate-2,5-bis(3-triethylene glycoloxythiophene-2-yl))(gDPP-g2T), poly(2(3,30-bis(2-(2-(2-methoxyethoxy)ethoxy)ethoxy)-[2,20-bithiophene]-5)ylthiophene)(p(g2T-T)), poly(diketonepyrrolopyrrolo-alt-dithiophene)(P(DPP-B)). Materials including poly(cyanobenzopyrazine-alt-dithiophene) (PCBB-BT), poly(NDI-2OD-T2), poly(benzimidazole-benzothiadiazole-alt-dithiophene) (P(BBT-T2)), polydiimide conjugated polymer, poly(benzothiadiazole-alt-dithiophene) (P(BT-BT)), poly(perylenetetracarboxyimide-alt-dithiophene) (P(PDI-BT)), poly(perylenediimide-thiophene copolymer), poly(pyridinium pyrazine-alt-dithiophene) (P(PP-BT)), and poly(cyanothiaphene-imidazole-alt-dithiophene) (P(CTI-BT)).

[0051] Furthermore, the encapsulation layer is made of an electrochemically stable insulating material, specifically one of photoresist SU-8, phenelzine-C, polydimethylsiloxane PDMS, or cinnamate-cellulose.

[0052] Furthermore, the electrolyte layer is a patternable solid electrolyte material, mainly including ion gels and polyelectrolytes.

[0053] Furthermore, the material used to prepare the gate is one of gold, silver, silver / silver chloride, poly(3,4-ethylenedioxythiophene):polystyrene sulfonate, carbon nanotubes, graphene, or graphyne.

[0054] The present invention also provides a method for back-to-back folded stacking of highly integrated OECT circuits, the method comprising the following:

[0055] OECT preparation method

[0056] Step S1: Cleaning, drying, and UV ozone treatment of the substrate. Specifically, the PI substrate is ultrasonically cleaned in isopropanol for 15 minutes, then dried with nitrogen and treated in a UV ozone environment for 5 minutes to obtain the pretreated substrate.

[0057] Step S2: A patterned source layer is prepared on the pretreated substrate. Specifically, 50 nm gold is deposited on the pretreated substrate using a mask (deposition speed 0.2-1.0 Å / s) as the source layer, with a width of 30 μm.

[0058] Step S3: Perform ultraviolet ozone cleaning on the substrate with the patterned source layer, specifically by placing it in an ultraviolet ozone environment for 5 minutes.

[0059] Step S4: Prepare a patterned n / p type semiconductor active layer on a substrate with a patterned source layer. Specifically, an organic composite ion-electron semiconductor material solution of n / p type OECT mixed with a photocrosslinking agent (homopolymer-poly(2,5-dipentadiene polyethylene glycol 3,6-di(thiophene-2-yl)-2,5-dihydropyrrolo[3,4-c]pyrrolo-1,4-dione) Homo-gDPP, poly(dithiophene-pyrrolopyrrolodione polymer gDPP-g2T, 20 mg / mL in chloroform) is spin-coated onto the source layer and a blank substrate. The solution volume is 40 μL, the rotation speed is 3000 rpm / s, and the time is 15 s. Then, the semiconductor active layer is patterned by photolithography and development. The photolithography time is 120 s with 365 nm ultraviolet light, and the chloroform development is 2 s followed by nitrogen drying.

[0060] Step S5: Prepare a patterned drain layer on the patterned semiconductor active layer. Specifically, deposit 50 nm gold (evaporation speed 0.2-1.0 Å / s) on the patterned semiconductor active layer using a mask as the drain layer. The width is 30 μm. During this process, the water cooling device of the evaporation system is activated to maintain the system temperature at 5°C to prevent the semiconductor active layer from being damaged due to overheating.

[0061] Step S6: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer. Specifically, prepare a solid electrolyte layer on the patterned semiconductor active layer and electrode structure by spin coating. The electrolyte solution contains poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-co-HFP) and ionic liquid 1-ethyl-3-methylimidazolium tetrafluoroborate [EMIM][TFSI] as a matrix, and adds photocrosslinking agent polyethylene glycol diacrylate (PEGDA) and photoinitiator 2-hydroxy-4'-(2-hydroxyethoxy)-2-methylphenylacetone (Irgacure 2959). The specific process steps are as follows: Spin coat the above electrolyte solution onto the substrate surface in a volume of 200 μL, covering the electrode layer, semiconductor active layer and blank areas; the spin coating parameters are set to a rotation speed of 800 rpm and a time of 60 s. Place the spin-coated substrate on an 80°C hot plate and let it stand for 60 s to allow the solvent acetone to fully evaporate. The electrolyte layer was exposed to ultraviolet light (UV) at a wavelength of 365 nm for 120 s to crosslink and cure the exposed areas. The exposed substrate was then developed with acetone for 5 s to remove uncrosslinked material. The surface was then dried with nitrogen to form a patterned solid electrolyte layer.

[0062] Step S7: A patterned gate layer is prepared on the patterned solid electrolyte layer. Specifically, Ag / AgCl slurry is printed on the patterned solid electrolyte layer using high-precision 3D inkjet printing technology to form a patterned first gate layer. Subsequently, the printed structure is rapidly annealed using a photonic sintering system with a sintering voltage of 800 V and a sintering time of 1 s.

[0063] Step S8: An encapsulation layer is fabricated on the patterned source layer, drain layer, semiconductor active layer, and solid electrolyte layer. Specifically, a photoresist solution of SU-8 (2002) is spin-coated onto the entire device structure surface to form the encapsulation layer. Specific process parameters are: solution volume 100 μL, spin-coating speed 2000 rpm, and spin-coating time 60 s. After coating, the device undergoes photolithography. Exposure conditions are: ultraviolet wavelength 350–400 nm, power density 45 mW / cm², and exposure time 30 s. Subsequently, development is performed using a developer for 20 s to remove photoresist from non-target areas.

[0064] Step S9: Fabricate OECT on the back side of the flexible substrate according to the above steps;

[0065] Step S10: Folding and stacking of highly integrated OECT devices. Specifically, after OECTs are fabricated on both sides of a flexible substrate, crease lines are etched at predetermined positions using a laser etching process. The parameters are: frequency 500 kHz, power 0.15 W, speed 1500 mm / s, and 10 cycles of etching. Then, the flexible substrate is repeatedly folded and stacked on a folding operation platform according to the etched crease lines to complete the highly integrated folded stacked OECT device.

[0066] Inverter fabrication method

[0067] Step S1: Cleaning, drying, and UV ozone treatment of the substrate. Specifically, the PI substrate is ultrasonically cleaned in isopropanol for 15 minutes, then dried with nitrogen and treated in a UV ozone environment for 5 minutes to obtain the pretreated substrate.

[0068] Step S2: Fabricate a patterned first electrode layer on the pretreated substrate. Specifically, a 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the pretreated substrate using a mask as the first electrode layer, with a width of 30 μm.

[0069] Step S3: Perform ultraviolet ozone cleaning treatment on the substrate with the patterned first electrode layer, specifically by placing it in an ultraviolet ozone environment for 5 minutes.

[0070] Step S4: Prepare a patterned n-type semiconductor active layer on the patterned first electrode. Specifically, a solution of n-type OECT organic composite ion-electron semiconductor material (Homo-gDPP, 20 mg / mL in chloroform) mixed with a photocrosslinking agent is spin-coated onto the first electrode and a blank substrate. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the n-type semiconductor active layer is patterned by photolithography and development. The photolithography time is 120 s with 365 nm ultraviolet light, and the chloroform development is 2 s followed by nitrogen drying.

[0071] Step S5: A patterned second electrode layer is prepared on the patterned n-type semiconductor active layer. Specifically, a 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the patterned semiconductor active layer using a mask as the second electrode layer, with a width of 30 μm. During this process, the water cooling device of the evaporation system is activated to maintain the system temperature at 5°C to prevent the semiconductor active layer from being damaged due to overheating.

[0072] Step S6: Prepare a patterned p-type semiconductor active layer on the patterned second electrode layer. Specifically, a p-type OECT organic composite ion-electron semiconductor material solution (gDPP-g2T, 20 mg / mL in chloroform) mixed with a photocrosslinking agent is spin-coated onto the second electrode layer. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the p-type semiconductor active layer is patterned by photolithography and development. The 365 nm ultraviolet photolithography time is 120 s, and the chloroform development is 2 s followed by nitrogen drying.

[0073] Step S7: A patterned third electrode layer is prepared on the patterned p-type semiconductor active layer. Specifically, a 50 nm thick gold layer (evaporation speed 0.2-1.0 Å / s) is deposited on the patterned p-type semiconductor active layer using a mask as the third electrode layer, with a width of 30 μm. During this process, the water cooling device of the evaporation system is activated to maintain the system temperature at 5°C to prevent the semiconductor active layer from being damaged due to overheating.

[0074] Step S8: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer. Specifically, prepare the solid electrolyte layer on the patterned semiconductor active layer and electrode layer by spin coating. The electrolyte solution contains poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-co-HFP) and ionic liquid 1-ethyl-3-methylimidazolium tetrafluoroborate [EMIM][TFSI] as a matrix, and adds photocrosslinking agent polyethylene glycol diacrylate (PEGDA) and photoinitiator 2-hydroxy-4'-(2-hydroxyethoxy)-2-methylphenylacetone (Irgacure 2959). The specific process steps are as follows: Spin coat the above electrolyte solution onto the substrate surface in a volume of 200 μL, covering the electrode layer, semiconductor active layer and blank areas; the spin coating parameters are set to a rotation speed of 800 rpm and a time of 60 s. Place the spin-coated substrate on an 80°C hot stage and let it stand for 60 s to allow the solvent acetone to fully evaporate. The electrolyte layer was exposed to ultraviolet light (UV) at a wavelength of 365 nm for 120 s to crosslink and cure the exposed areas. The exposed substrate was then developed with acetone for 5 s to remove uncrosslinked material. The surface was then dried with nitrogen to form a patterned solid electrolyte layer.

[0075] Step S9: A patterned second gate layer is prepared on the patterned solid electrolyte layer. Specifically, Ag / AgCl slurry is printed on the patterned solid electrolyte layer using high-precision 3D inkjet printing technology to form a patterned second gate layer. Subsequently, the printed structure is rapidly annealed using a photonic sintering system with a sintering voltage of 800 V and a sintering time of 1 s.

[0076] Step S10: An encapsulation layer is prepared on the electrode layer, semiconductor active layer, and solid electrolyte layer. Specifically, a photoresist solution of SU-8 (2002) is spin-coated onto the entire device structure surface to form the encapsulation layer. Specific process parameters are: solution volume 100 μL, spin-coating speed 2000 rpm, and spin-coating time 60 s. After coating, the device undergoes photolithography. Exposure conditions are: ultraviolet wavelength 350–400 nm, power density 45 mW / cm², and exposure time 30 s. Subsequently, development is performed using a developer for 20 s to remove photoresist from non-target areas.

[0077] Step S11: Fabricate an inverter on the back side of the flexible substrate according to the above steps;

[0078] Step S12: Folding and stacking of high-integration inverter circuit. Specifically, after inverters are fabricated on both sides of the flexible substrate, crease lines are processed at predetermined positions on the substrate by laser etching. The laser parameters used are: frequency 500 kHz, power 0.15 W, scanning speed 1500 mm / s, and 10 cycles of etching. Then, the flexible substrate is repeatedly folded and stacked on the folding operation platform according to the etched crease lines to complete the high-integration folded stacked inverter circuit.

[0079] NAND gate preparation method

[0080] Step S1: Cleaning, drying, and UV ozone treatment of the substrate. Specifically, the PI substrate is ultrasonically cleaned in isopropanol for 15 minutes, then dried with nitrogen and treated in a UV ozone environment for 5 minutes to obtain the pretreated substrate.

[0081] Step S2: A patterned first electrode layer is prepared on the front side of the pretreated substrate. Specifically, a 50 nm thick gold layer (evaporation speed 0.2-1.0 Å / s) is deposited on the treated substrate using a mask as the first electrode layer, with a width of 30 μm.

[0082] Step S3: Perform ultraviolet ozone cleaning treatment on the substrate with the patterned first electrode layer, specifically by placing it in an ultraviolet ozone environment for 5 minutes to obtain the treated substrate.

[0083] Step S4: Prepare a patterned n-type semiconductor active layer on the substrate with a patterned first electrode layer after UV ozone treatment. Specifically, a solution of n-type OECT organic composite ion-electron semiconductor material (Homo-gDPP, 20 mg / mL in chloroform) mixed with a photocrosslinking agent is spin-coated onto the first electrode layer. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the n-type semiconductor active layer is patterned by photolithography and development. The 365 nm UV photolithography time is 120 s, and the chloroform development is 2 s followed by nitrogen drying.

[0084] Step S5: A patterned second electrode layer is prepared on the patterned n-type semiconductor active layer. A 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the n-type semiconductor active layer using a mask as the second electrode layer, with a width of 30 μm.

[0085] Step S6: Prepare a patterned p-type semiconductor active layer on the patterned second electrode layer. Specifically, a solution of organic composite ion-electron semiconductor material (gDPP-g2T, 20 mg / mL in chloroform) mixed with a photocrosslinking agent is spin-coated onto the second electrode layer and a blank substrate. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the p-type semiconductor active layer is patterned by photolithography and development. The photolithography time is 120 s with 365 nm ultraviolet light, and the chloroform development is 2 s followed by nitrogen drying.

[0086] Step S7: Prepare a patterned third electrode layer on the patterned p-type semiconductor active layer. Specifically, deposit a 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) on the p-type semiconductor active layer using a mask as the third electrode layer, with a width of 30 μm.

[0087] Step S8: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer. Specifically, prepare a solid electrolyte layer on the patterned semiconductor active layer and electrode layer structure by spin coating. The electrolyte solution contains poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-co-HFP) and ionic liquid 1-ethyl-3-methylimidazolium tetrafluoroborate [EMIM][TFSI] as a matrix, and adds photocrosslinking agent polyethylene glycol diacrylate (PEGDA) and photoinitiator 2-hydroxy-4'-(2-hydroxyethoxy)-2-methylphenylacetone (Irgacure 2959). The specific process steps are as follows: Spin coat the above electrolyte solution onto the substrate surface in a volume of 200 μL, covering the electrode layer, semiconductor active layer and blank areas; the spin coating parameters are set to a rotation speed of 800 rpm and a time of 60 s. Place the spin-coated substrate on an 80°C hot stage and let it stand for 60 s to allow the solvent acetone to fully evaporate. The electrolyte layer was exposed to ultraviolet (UV) light at a wavelength of 365 nm for 120 s to crosslink and cure the exposed areas. The exposed substrate was then developed with acetone for 5 s to remove uncrosslinked material. The surface was then dried with nitrogen to form a patterned solid electrolyte layer.

[0088] Step S9: A patterned gate layer is prepared on the patterned solid electrolyte layer. Specifically, Ag / AgCl slurry is printed on the patterned solid electrolyte layer using high-precision 3D inkjet printing technology to form a patterned third gate layer and a fourth gate layer. Subsequently, the printed structure is rapidly annealed using a photonic sintering system with a sintering voltage of 800 V and a sintering time of 1 s.

[0089] Step S10: An encapsulation layer is prepared on the electrode layer, semiconductor active layer, solid electrolyte layer, and gate layer. Specifically, a photoresist solution of SU-8 (2002) is spin-coated onto the entire device structure surface to form the encapsulation layer. Specific process parameters are: solution volume 100 μL, spin-coating speed 2000 rpm, and spin-coating time 60 s. After coating, the device undergoes photolithography. Exposure conditions are: ultraviolet wavelength 350–400 nm, power density 45 mW / cm², and exposure time 30 s. Subsequently, development is performed using a developer for 20 s to remove photoresist from non-target areas.

[0090] Step S11: A patterned fourth electrode layer is fabricated on the back side of the flexible substrate. Specifically, a 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the back side of the p-type OECT substrate using a mask as the fourth electrode layer, with a width of 30 μm.

[0091] Step S12: Prepare a patterned n-type semiconductor active layer on the patterned fourth electrode layer. Specifically, a solution of n-type OECT organic composite ion-electron semiconductor material (Homo-gDPP, 20 mg / mL in chloroform) mixed with a photocrosslinking agent is spin-coated onto the fourth electrode layer. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the n-type semiconductor active layer is patterned by photolithography and development. The photolithography time is 120 s with 365 nm ultraviolet light, and the chloroform development is 2 s followed by nitrogen drying.

[0092] Step S13: Prepare a fifth electrode layer on the patterned n-type semiconductor active layer. Specifically, deposit 50 nm gold (evaporation rate 0.2-1.0 Å / s) on the n-type semiconductor active layer using a mask as the fifth electrode layer, with a width of 30 μm.

[0093] Step S14: Laser etching is used to etch vias at the left end of the fourth electrode layer and 50 μm to the right of the semiconductor active layer. Specifically, laser etching is used to prepare vias for n / p type OECT electrolyte interconnects and the connection between the first and fourth electrode layers. The specific laser parameters are set as follows: frequency 500 kHz, power 0.2 W, scanning speed 1500 mm / s, and 80 cyclic etching cycles.

[0094] Step S15: Prepare a patterned electrolyte layer on the patterned semiconductor active layer on the back of the flexible substrate and cover the electrolyte vias. Specifically, prepare a solid electrolyte layer on the patterned semiconductor active layer and electrode layer by spin coating. The electrolyte solution contains poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-co-HFP) and ionic liquid 1-ethyl-3-methylimidazolium tetrafluoroborate [EMIM][TFSI] as a matrix, and adds photocrosslinking agent polyethylene glycol diacrylate (PEGDA) and photoinitiator 2-hydroxy-4'-(2-hydroxyethoxy)-2-methylphenylacetone (Irgacure 2959). The specific process steps are as follows: Spin coat the above electrolyte solution onto the substrate surface in a volume of 200 μL, covering the electrode layer, semiconductor active layer and blank areas; the spin coating parameters are set to a rotation speed of 800 rpm and a time of 60 s. Place the spin-coated substrate on an 80℃ hot stage and let it stand for 60 s to allow the solvent acetone to fully evaporate. The electrolyte layer was exposed to ultraviolet (UV) light at a wavelength of 365 nm for 120 s to crosslink and cure the exposed areas. The exposed substrate was then developed with acetone for 5 s to remove uncrosslinked material. The surface was then dried with nitrogen to form a patterned solid electrolyte layer.

[0095] Step S16: Print conductive paste onto the electrode through holes using a 3D printer to ensure the connection between the first electrode layer and the fourth electrode layer. Specifically, print gold nanoparticle ink onto the through holes using a 3D printer to ensure the electrode connection.

[0096] Step S17: An encapsulation layer is fabricated on the electrode layer, semiconductor active layer, and electrolyte layer on the back side of the flexible substrate. Specifically, a photoresist solution of SU-8 (2002) is spin-coated onto the entire device structure surface to form the encapsulation layer. Specific process parameters are: solution volume 100 μL, spin-coating speed 2000 rpm, and spin-coating time 60 s. After coating, the device undergoes photolithography. Exposure conditions are: ultraviolet wavelength 350–400 nm, power density 45 mW / cm², and exposure time 30 s. Subsequently, development is performed using a developer for 20 s to remove photoresist from non-target areas.

[0097] Step S18: Crease lines are etched at predetermined positions using a laser etching process. The laser parameters are: frequency 500kHz, power 0.15 W, scanning speed 1500 mm / s, and 10 cyclic etching cycles. Then, the flexible substrate is repeatedly folded and stacked on a folding platform to complete the fabrication of a highly integrated folded NAND gate circuit.

[0098] OR NOT gate preparation method

[0099] Step S1: Cleaning, drying, and UV ozone treatment of the substrate. Specifically, the PI substrate is ultrasonically cleaned in isopropanol for 15 minutes, then dried with nitrogen and treated in a UV ozone environment for 5 minutes to obtain the pretreated substrate.

[0100] Step S2: A patterned first electrode layer is prepared on the front side of the pretreated substrate. Specifically, a 50 nm thick gold layer (evaporation speed 0.2-1.0 Å / s) is deposited on the treated substrate using a mask as the first electrode layer, with a width of 30 μm.

[0101] Step S3: Perform ultraviolet ozone cleaning treatment on the substrate with the patterned first electrode layer, specifically by placing it in an ultraviolet ozone environment for 5 minutes to obtain the treated substrate.

[0102] Step S4: Prepare a patterned p-type semiconductor active layer on the substrate with a patterned first electrode layer after ultraviolet ozone treatment. Specifically, coat the first electrode layer with a p-type OECT organic composite ion-electron semiconductor material solution (gDPP-g2T, 20 mg / mL in chloroform) mixed with a photocrosslinking agent by spin coating. The solution volume is 40 μL, the rotation speed is 3000 rpm / s, and the time is 15 s. Then, pattern the p-type semiconductor active layer by photolithography and development. The photolithography time is 120 s with 365 nm ultraviolet light, and the chloroform development is 2 s followed by nitrogen drying.

[0103] Step S5: A patterned second electrode layer is prepared on the patterned p-type semiconductor active layer. A 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the p-type semiconductor active layer using a mask as the second electrode layer, with a width of 30 μm.

[0104] Step S6: Prepare a patterned n-type semiconductor active layer on the patterned second electrode layer. Specifically, a solution of n-type OECT organic composite ion-electron semiconductor material mixed with a photocrosslinking agent (gDPP-g2T, 20 mg / mL in chloroform) is spin-coated onto the second electrode and a blank substrate. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the n-type semiconductor active layer is patterned by photolithography and development. The photolithography time is 120 s with 365 nm ultraviolet light, and the chloroform development is 2 s followed by nitrogen drying.

[0105] Step S7: Fabricate a patterned third electrode layer on the n-type patterned semiconductor active layer. A 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the n-type semiconductor active layer using a mask as the third electrode layer, with a width of 30 μm.

[0106] Step S8: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer. Specifically, prepare the solid electrolyte layer on the patterned semiconductor active layer and electrode layer by spin coating. The electrolyte solution contains poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-co-HFP) and ionic liquid 1-ethyl-3-methylimidazolium tetrafluoroborate [EMIM][TFSI] as a matrix, and adds photocrosslinking agent polyethylene glycol diacrylate (PEGDA) and photoinitiator 2-hydroxy-4'-(2-hydroxyethoxy)-2-methylphenylacetone (Irgacure 2959). The specific process steps are as follows: Spin coat the above electrolyte solution onto the substrate surface in a volume of 200 μL, covering the electrode layer, semiconductor active layer and blank areas; the spin coating parameters are set to a rotation speed of 800 rpm and a time of 60 s. Place the spin-coated substrate on an 80°C hot stage and let it stand for 60 s to allow the solvent acetone to fully evaporate. The electrolyte layer was exposed to ultraviolet (UV) light at a wavelength of 365 nm for 120 s to crosslink and cure the exposed areas. The exposed substrate was then developed with acetone for 5 s to remove uncrosslinked material. The surface was then dried with nitrogen to form a patterned solid electrolyte layer.

[0107] Step S9: A patterned gate layer is prepared on the patterned solid electrolyte layer. Specifically, Ag / AgCl slurry is printed on the patterned solid electrolyte layer using high-precision 3D inkjet printing technology to form a patterned fifth gate layer and a sixth gate layer. Subsequently, the printed structure is rapidly annealed using a photonic sintering system with a sintering voltage of 800 V and a sintering time of 1 s.

[0108] Step S10: An encapsulation layer is prepared on the electrode layer, semiconductor active layer, solid electrolyte layer, and gate layer. Specifically, a photoresist solution of SU-8 (2002) is spin-coated onto the entire device structure surface to form the encapsulation layer. Specific process parameters are: solution volume 100 μL, spin-coating speed 2000 rpm, and spin-coating time 60 s. After coating, the device undergoes photolithography. Exposure conditions are: ultraviolet wavelength 350–400 nm, power density 45 mW / cm², and exposure time 30 s. Subsequently, development is performed using a developer for 20 s to remove photoresist from non-target areas.

[0109] Step S11: A patterned fourth electrode layer is fabricated on the back side of the flexible substrate. Specifically, a 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) is deposited on the back side of the n-type OECT using a mask as the fourth electrode layer, with a width of 30 μm.

[0110] Step S12: Prepare a patterned p-type semiconductor active layer on the patterned fourth electrode layer. Specifically, a p-type OECT organic composite ion-electron semiconductor material solution (Homo-gDPP, 20 mg / mL in chloroform) mixed with a photocrosslinking agent is spin-coated onto the fourth electrode layer. The solution volume is 40 μL, the spin speed is 3000 rpm / s, and the time is 15 s. Then, the p-type semiconductor active layer is patterned by photolithography and development. The 365 nm ultraviolet photolithography time is 120 s, and the chloroform development is 2 s followed by nitrogen drying.

[0111] Step S13: Prepare a fifth electrode layer on the patterned p-type semiconductor active layer. Specifically, deposit a 50 nm thick gold layer (evaporation rate 0.2-1.0 Å / s) on the n-type semiconductor active layer using a mask as the source electrode, with a width of 30 μm.

[0112] Step S14: Laser etching is used to etch vias at the left end of the fourth electrode layer and 50 μm to the right of the semiconductor active layer. Specifically, laser etching is used to fabricate electrolyte vias for n / p type OECT electrolyte interconnects and electrode vias connecting the first and fourth electrode layers. Specific laser parameters are set as follows: frequency 500 kHz, power 0.2 W, scanning speed 1500 mm / s, and 80 cyclic etching cycles.

[0113] Step S15: A patterned electrolyte layer is prepared on the patterned semiconductor active layer on the back side of the flexible substrate and the electrolyte vias are covered. Specifically, a solid electrolyte layer is prepared on the patterned semiconductor active layer and the electrode layer by spin coating. The electrolyte solution contains poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-co-HFP) and ionic liquid 1-ethyl-3-methylimidazolium tetrafluoroborate [EMIM][TFSI] as a matrix, and photocrosslinking agent polyethylene glycol diacrylate (PEGDA) and photoinitiator 2-hydroxy-4'-(2-hydroxyethoxy)-2-methylphenylacetone (Irgacure 2959) are added. The specific process steps are as follows: The above electrolyte solution is spin-coated onto the substrate surface in a volume of 200 μL, covering the electrode layer, the semiconductor active layer and the blank area; the spin coating parameters are set to a rotation speed of 800 rpm and a time of 60 s. The spin-coated substrate is placed on an 80°C hot stage and left to stand for 60 s to allow the solvent acetone to evaporate completely. The electrolyte layer was exposed to ultraviolet (UV) light at a wavelength of 365 nm for 120 s to crosslink and cure the exposed areas. The exposed substrate was then developed with acetone for 5 s to remove uncrosslinked material. The surface was subsequently dried with nitrogen gas to form a patterned solid electrolyte layer.

[0114] Step S16: Print conductive paste onto the electrode through holes using a 3D printer to ensure the connection between the first electrode layer and the fourth electrode layer. Specifically, print gold nanoparticle ink onto the through holes using a 3D printer to ensure the electrode connection.

[0115] Step S17: An encapsulation layer is fabricated on the electrode layer, semiconductor active layer, and electrolyte layer on the back side of the flexible substrate. Specifically, a photoresist solution of SU-8 (2002) is spin-coated onto the entire device structure surface to form the encapsulation layer. Specific process parameters are: solution volume 100 μL, spin-coating speed 2000 rpm, and spin-coating time 60 s. After coating, the device undergoes photolithography. Exposure conditions are: ultraviolet wavelength 350–400 nm, power density 45 mW / cm², and exposure time 30 s. Subsequently, development is performed using a developer for 20 s to remove photoresist from non-target areas.

[0116] Step S18: Crease lines are etched at predetermined positions using a laser etching process. The laser parameters are: frequency 500kHz, power 0.15 W, scanning speed 1500 mm / s, and 10 cyclic etching cycles. Then, the flexible substrate is repeatedly folded and stacked on a folding platform to complete the fabrication of a highly integrated folded NOR gate circuit.

[0117] Figure 10 The transfer characteristic curves and transconductance curves of p / n type OECT provided in the embodiments of the present invention are shown in (a) for p type OECT and (b) for n type OECT.

[0118] Figure 11 The diagram shows the test performance of the OECT circuit provided in the embodiment of the present invention. (a) is an inverter, and (b) is a NAND gate and a NOR gate.

[0119] Furthermore, the performance of the fabricated back-to-back folded stacked OECT circuit was tested. The test conditions and results are as follows:

[0120] First, the electrical performance of the OECT was characterized. The test conditions for n-type and p-type OECTs were as follows: the source electrode layer was grounded (GND), and a constant voltage of 0.1 V was applied to the drain electrode layer (V0.1). D The first gate layer serves as the input voltage (V). G The circuit was scanned within a set range (n-type: 0 V to 0.8 V; p-type: 0.2 V to -0.6 V), with a scan step size of 0.01 V. Test results showed that both n-type and p-type OECTs exhibited good transfer characteristics and good transconductance. The test conditions for the inverter circuit were: a constant voltage of 0.6 V applied to the third electrode layer (V... DD The lower electrode is grounded (GND), and the second gate layer serves as the voltage input terminal (V). INA scan voltage from 0 V to 0.6 V is applied in steps of 0.002 V, with the second electrode layer serving as the output terminal (V). OUT This is used to obtain the voltage transfer characteristic curve. In inverter testing, when the input voltage (V) IN When scanning from 0 V to 0.6 V, the output voltage (V) OUT The inverter exhibits complete logic inversion behavior, indicating that it possesses excellent voltage transfer characteristics. The test conditions for the NAND gate circuit are as follows: the fifth electrode layer is grounded (GND); a constant voltage of 0.6 V is applied to the third electrode layer (V). DD The third gate layer serves as the first voltage input terminal (V). IN1 The input frequency is a square wave signal with a frequency of 2.5 Hz and an amplitude of 0-0.6 V; the fourth gate layer serves as the second voltage input terminal (V). IN2 The input frequency is 5 Hz and the amplitude is 0-0.6 V. The second electrode layer serves as the voltage output terminal (V). OUT The test conditions for the NOR gate circuit are: the third electrode layer is grounded (GND); a constant voltage of 0.6 V is applied to the fifth electrode layer. DD The fifth gate layer serves as the first voltage input terminal (V). IN1 The input frequency is a square wave signal with a frequency of 2.5 Hz and an amplitude of 0-0.6 V; the sixth gate layer serves as the second voltage input terminal (V). IN2 The input frequency is 5 Hz and the amplitude is 0-0.6 V. The second electrode layer serves as the voltage output terminal (V). OUT Dynamic tests were conducted by applying square wave signals of different frequencies to the input terminals. The results showed that the voltage output (V) of the NAND gate and the NOR gate... OUT All of them are consistent with their respective logic truth tables, which confirms their good logic operation capabilities and voltage transfer characteristics.

[0121] It should be understood that the above description only relates to specific embodiments of the present invention and is intended to enable those skilled in the art to understand the principles and features of the present invention. However, the present invention is not limited to the described embodiments, but can be applied to various changes and modifications, as long as these changes and modifications are within the scope of the appended claims.

Claims

1. A highly integrated OECT circuit with back-to-back folded stacking, characterized in that, include: Organic electrochemical transistors (OECT), inverters, NAND gates, and NOR gates; The OECT, inverter, NAND gate, and NOR gate are packaged on the substrate through an electrode layer, a semiconductor active layer, an electrolyte layer, a gate layer, a via, a conductive paste, and a packaging layer to obtain a highly integrated OECT circuit. Wherein, the substrate is a foldable and stackable flexible substrate; The electrode layers include an OECT source layer, an OECT drain layer, an inverter first electrode layer, an inverter second electrode layer, an inverter third electrode layer, a NAND gate first electrode layer, a NAND gate second electrode layer, a NAND gate third electrode layer, a NAND gate fourth electrode layer, a NAND gate fifth electrode layer, a NOR gate first electrode layer, a NOR gate second electrode layer, a NOR gate third electrode layer, a NOR gate fourth electrode layer, and a NOR gate fifth electrode layer; In this configuration, the source layer of the OECT is grounded, and the drain layer is connected to the power supply. The first electrode layer of the inverter is grounded, the third electrode layer is connected to the power supply, and the second electrode layer is the voltage output. The first and fourth electrode layers of the NAND gate are connected via electrode connection vias, the second electrode layer is the voltage output, the third electrode layer is connected to the power supply, the fifth electrode layer is grounded, and the third and fourth gate layers are the voltage inputs of the NAND gate. The first and fourth electrode layers of the NOR gate are connected via electrode connection vias, the second electrode layer is the output, the third electrode layer is grounded, the fifth electrode layer is connected to the power supply, and the fifth and sixth gate layers are the voltage inputs of the NOR gate. The semiconductor active layer includes an n-type semiconductor active layer and a p-type semiconductor active layer; Specifically, an n-type semiconductor active layer is disposed between the first and second electrode layers of the inverter to isolate them; an n-type semiconductor active layer is disposed between the first and second electrode layers of the NAND gate to isolate them; an n-type semiconductor active layer is disposed between the fourth and fifth electrode layers of the NAND gate to isolate them; an n-type semiconductor active layer is disposed between the fourth and fifth electrode layers of the NOR gate to isolate them; and an n-type semiconductor active layer is disposed between the first and second electrode layers of the NOR gate to isolate them. A p-type semiconductor active layer is disposed between the drain and source layers of the OECT; a p-type semiconductor active layer is disposed between the second and third electrode layers of the inverter to isolate them; a p-type semiconductor active layer is disposed between the second and third electrode layers of the NAND gate to isolate them; and a p-type semiconductor active layer is disposed between the fourth and second electrode layers of the NOR gate to isolate them. The electrolyte completely covers the working areas of the OECT, inverter, NAND gate, and NOR gate, wherein the n-type and p-type OECTs within the NAND gate and NOR gate share the electrolyte through electrolyte interconnection vias; The gate layers are sequentially numbered from the first gate layer to the sixth gate layer, wherein the first gate layer is the voltage input terminal of the OECT, the second gate layer is the voltage input terminal of the inverter, the third gate layer is the first voltage input terminal of the NAND gate, the fourth gate layer is the second voltage input terminal of the NAND gate, the fifth gate layer is the first voltage input terminal of the NOR gate, and the sixth gate layer is the second voltage input terminal of the NOR gate. The through-holes include electrolyte interconnection through-holes and electrode connection through-holes; The encapsulation layer fully encapsulates OECT, inverters, NAND gates, and NOR gates; The conductive paste is a printable paste with high conductivity, and it is printed on the electrode through-holes.

2. The highly integrated OECT circuit with back-to-back folded stacking as described in claim 1, characterized in that, The OECT encapsulation process on the substrate is as follows: The source layer of the OECT is disposed on a flexible substrate, the semiconductor active layer is patterned on the source layer, the drain layer is located above the semiconductor active layer and is perpendicular to the source layer, and the patterned electrolyte layer covers the three-layer structure; the first gate layer is disposed on the electrolyte layer and faces the semiconductor active layer; the encapsulation layer completely encapsulates the aforementioned layers; wherein, the source is grounded, the drain is connected to a constant voltage, and the gate is connected to the input terminal; The inverter is packaged on the substrate as follows: The inverter is composed of n-type and p-type OECTs stacked vertically, and the stacking order of the two can be interchanged; starting from the flexible substrate, it is vertically stacked with: a first electrode layer serving as the source of the n-type OECT and grounded, a second electrode layer serving as the common drain of the n / p-type OECT, and a third electrode layer serving as the source of the p-type OECT and connected to a constant voltage, with each electrode layer isolated by a corresponding n-type or p-type semiconductor active layer; a patterned electrolyte layer covers the semiconductor active layer, and a second gate layer is provided on its surface facing the active layer, which serves as the voltage input terminal; the second electrode layer serves as the voltage output terminal; the outermost layer of the inverter is completely covered by the encapsulation layer; The NAND gate is packaged on the substrate as follows: The NAND gate is integrated on a flexible substrate, comprising an inverter, an n-type OECT, and a p-type OECT; wherein, the inverter and the p-type OECT are located on the front side of the substrate, and the second electrode layer of the inverter is connected to the source layer of the p-type OECT to form the second electrode layer of the NAND gate, and the third electrode layer of the inverter is connected to the drain layer of the p-type OECT to form the third electrode layer of the NAND gate; the n-type OECT is located on the back side of the substrate, arranged back-to-back with the p-type OECT; the p-type and n-type OECTs are interconnected by an electrolyte via and share a common gate; the drain of the n-type OECT is connected to the first electrode layer of the inverter through an electrode via; the fifth electrode layer of the NAND gate is grounded, the third electrode layer of the NAND gate is connected to the power supply voltage, the third gate layer is the first voltage input terminal, the fourth gate layer is the second voltage input terminal, and the second electrode layer of the NAND gate is the output terminal; the outermost layer of the NAND gate is completely covered by a packaging layer; The NOR gate is packaged on the substrate as follows: The NOR gate circuit is integrated on a flexible substrate, which includes an inverter, an n-type OECT, and a p-type OECT; wherein, the inverter and the n-type OECT are located on the front side of the substrate, and the second electrode layer of the inverter is interconnected with the source layer of the n-type OECT as the second electrode layer of the NOR gate, and the third electrode layer of the inverter is interconnected with the drain of the n-type OECT as the third electrode layer of the NOR gate; the p-type OECT is located on the back side of the substrate and is arranged opposite to the n-type OECT; the p-type and n-type OECTs are interconnected by electrolyte vias and share a gate layer; the source of the p-type OECT is connected to the first electrode layer of the inverter through an electrode via; the third electrode layer of the NOR gate is grounded; the fifth electrode layer of the NOR gate is connected to the power supply voltage; the fifth gate layer serves as the first voltage input terminal, the sixth gate layer serves as the second voltage input terminal; and the second electrode layer of the NOR gate serves as the output terminal.

3. The highly integrated OECT circuit with back-to-back folded stacking as described in claim 1, characterized in that, The method for preparing the OECT is as follows: Step S3.1: Clean, dry, and treat the substrate with ultraviolet ozone; Step S3.2: Fabricate a patterned source layer on the pretreated substrate; Step S3.3: Perform ultraviolet ozone treatment on the substrate with the patterned source layer; Step S3.4: Fabricate a patterned p-type semiconductor active layer on a substrate with a patterned source layer; Step S3.5: Fabricate a patterned drain layer on the patterned semiconductor active layer; Step S3.6: Prepare a patterned solid electrolyte layer on the semiconductor active layer; Step S3.7: Fabricate a patterned first gate layer on the patterned solid electrolyte layer; Step S3.8: Fabricate an encapsulation layer on the patterned electrode layer, semiconductor active layer, solid electrolyte layer, and gate layer; Step S3.9: Fabricate OECT on the back side of the substrate according to the above steps; Step S3.10: A crease line is formed at a predetermined position on the flexible substrate using a laser etching process. Then, the substrate is repeatedly folded along the crease line on the folding operation platform to achieve the folded stacking fabrication of highly integrated OECT devices.

4. The highly integrated OECT circuit with back-to-back folded stacking as described in claim 1, characterized in that, The inverter is prepared by: Step S4.1: Clean, dry, and treat the substrate with ultraviolet ozone; Step S4.2: Fabricate a patterned first electrode layer on the pretreated substrate; Step S4.3: Perform ultraviolet ozone treatment on the substrate with the patterned first electrode layer; Step S4.4: Fabricate a patterned n-type semiconductor active layer on a substrate with a patterned first electrode layer; Step S4.5: Fabricate a patterned second electrode layer on the patterned n-type semiconductor active layer; Step S4.6: Fabricate a patterned p-type semiconductor active layer on the patterned second electrode layer; Step S4.7: Fabricate a patterned third electrode layer on the patterned p-type semiconductor active layer; Step S4.8: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer; Step S4.9: Fabricate a patterned second gate layer on the patterned solid electrolyte layer; Step S4.10: Prepare an encapsulation layer on the inverter electrode layer, the semiconductor active layer, and the solid electrolyte layer; Step S4.11: Fabricate an inverter on the back side of the flexible substrate according to the above steps; Step S4.12: A crease line is formed at a predetermined position on the flexible substrate using a laser etching process. Then, the substrate is repeatedly folded along the crease line on the folding operation platform to achieve the folded stacking fabrication of a highly integrated inverter.

5. A highly integrated OECT circuit with back-to-back folded stacking as described in claim 1, characterized in that, The method for preparing the NAND gate is as follows: Step S5.1: Clean, dry, and treat the substrate with ultraviolet ozone; Step S5.2: Fabricate a patterned first electrode layer on the front side of the pretreated substrate; Step S5.3: Perform ultraviolet ozone treatment on the substrate with the patterned first electrode layer; Step S5.4: Fabricate a patterned n-type semiconductor active layer on the substrate of the patterned first electrode layer; Step S5.5: Fabricate a patterned second electrode layer on the patterned n-type semiconductor active layer; Step S5.6: Fabricate a patterned p-type semiconductor active layer on the patterned second electrode layer; Step S5.7: Fabricate a patterned third electrode layer on the patterned p-type semiconductor active layer; Step S5.8: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer; Step S5.9: Fabricate a patterned third gate layer and a fourth gate layer on the patterned solid electrolyte layer; Step S5.10: Prepare an encapsulation layer on the electrode layer, semiconductor active layer, solid electrolyte layer and gate layer; Step S5.11: Fabricate a patterned fourth electrode layer on the back side of the flexible substrate; Step S5.12: Fabricate a patterned n-type semiconductor active layer on the patterned fourth electrode layer; Step S5.13: Fabricate a patterned fifth electrode layer on the patterned n-type semiconductor active layer; Step S5.14: Use laser etching to etch vias at the left end of the fourth electrode layer and at 50 μm to the right of the semiconductor active layer, respectively; Step S5.15: Prepare a patterned electrolyte layer on the patterned semiconductor active layer on the back side of the flexible substrate and cover the electrolyte vias; Step S5.16: Print conductive paste onto the electrode through-holes using a 3D printer to ensure electrode connection; Step S5.17: Fabricate an encapsulation layer on the electrode layer, semiconductor active layer, and electrolyte layer on the back side of the substrate; Step S5.18: A crease line is formed at a predetermined position on the flexible substrate using a laser etching process. Then, the substrate is repeatedly folded along the crease line on the folding operation platform to achieve the folded stacking fabrication of highly integrated NAND gates.

6. The highly integrated OECT circuit with back-to-back folded stacking as described in claim 1, characterized in that, The method for preparing the NOR gate is as follows: Step S6.1: Clean, dry, and treat the substrate with ultraviolet ozone; Step S6.2: Fabricate a patterned first electrode layer on the front side of the pretreated substrate; Step S6.3: Perform ultraviolet ozone treatment on the substrate with the patterned first electrode layer; Step S6.4: Fabricate a patterned p-type semiconductor active layer on the patterned first electrode layer; Step S6.5: Fabricate a patterned second electrode layer on the patterned p-type semiconductor active layer; Step S6.6: Fabricate a patterned n-type semiconductor active layer on the patterned second electrode layer; Step S6.7: Fabricate a patterned third electrode layer on the patterned n-type semiconductor active layer; Step S6.8: Prepare a patterned solid electrolyte layer on the patterned semiconductor active layer; Step S6.9: Fabricate a patterned fifth gate layer and a sixth gate layer on the patterned solid electrolyte layer; Step S6.10: Prepare an encapsulation layer on the electrode layer, semiconductor active layer, solid electrolyte layer and gate layer; Step S6.11: Fabricate a patterned fourth electrode layer on the back side of the flexible substrate; Step S6.12: Fabricate a patterned p-type semiconductor active layer on the patterned fourth electrode layer; Step S6.13: Fabricate the fifth electrode layer on the patterned p-type semiconductor active layer; Step S6.14: Use laser etching to etch vias at the left end of the fourth electrode layer and at a distance of 50 μm to the right of the semiconductor active layer, respectively; Step S6.15: Prepare a patterned electrolyte layer on the patterned semiconductor active layer on the back side of the flexible substrate and cover the electrolyte vias; Step S6.16: Print conductive paste onto the electrode through-holes using a 3D printer to ensure electrode connection; Step S6.17: Fabricate an encapsulation layer on the electrode layer, semiconductor active layer, and electrolyte layer on the back side of the substrate; Step S6.18: A crease line is formed at a predetermined position on the flexible substrate using a laser etching process. Then, the substrate is repeatedly folded along the crease line on the folding operation platform to achieve the folded stacking fabrication of highly integrated NOR gates.

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