Display module

Abstract

A display module includes: a display panel including a plurality of output pad groups, each of the plurality of output pad groups including a first output pad; a driving circuit chip disposed on the display panel and overlapping the plurality of output pad groups; and a printed circuit board disposed on the display panel, the printed circuit board including a plurality of output terminals electrically connected to the plurality of output pad groups. The plurality of output terminals includes a first output terminal electrically connected to a first output pad of each of the plurality of output pad groups.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0143266 filed in the Korean Intellectual Property Office on October 24, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a display module, and more particularly, to a display module including a printed circuit board having an improved design capable of performing a connection resistance test. Background Art

[0004] An integrated circuit for driving a light-emitting element in a display module may be disposed on a display panel. The integrated circuit may be directly mounted on the display panel in, for example, a chip on glass (COG) structure or a chip on plastic (COP) structure, which may increase the proportion of the display area in the display panel. In addition, a printed circuit board may be disposed on the display panel in a film on plastic (FOP) structure or a film on glass (FOG) structure.

[0005] When an integrated circuit is directly mounted on a display panel in a COP structure, a connection resistance may be generated between the display panel and the integrated circuit. In addition, when a printed circuit board is disposed on the display panel, a connection resistance may be generated between the display panel and the printed circuit board. Summary of the invention

[0006] The embodiment provides a display module including a printed circuit board having an improved design, which is capable of performing a connection resistance test.

[0007] According to aspects of the present disclosure, a display module is provided, including: a display panel including a plurality of output pad groups, each of the plurality of output pad groups including a first output pad; a driving circuit chip disposed on the display panel and overlapping the plurality of output pad groups; and a printed circuit board disposed on the display panel, the printed circuit board including a plurality of output terminals electrically connected to the plurality of output pad groups, wherein the plurality of output terminals include a first output terminal electrically connected to a first output pad of each of the plurality of output pad groups.

[0008] Each of the plurality of output pad groups may further include a second output pad connected to ground.

[0009] The plurality of output terminals may further include a second output terminal electrically connected to a grounded second output pad of each of the plurality of output pad groups. The current supplied to the first output pad of each of the plurality of output pad groups through the first output terminal may flow from the first output terminal to the second output terminal.

[0010] Each of the plurality of output pad groups may further include a third output pad and a fourth output pad. The plurality of output terminals may further include a plurality of third output terminals electrically connected to the third output pad of each of the plurality of output pad groups and a fourth output terminal electrically connected to the fourth output pad of each of the plurality of output pad groups.

[0011] The test device may be electrically connected to the printed circuit board, and the test device may measure resistance between a grounded second output pad of at least one of the plurality of output pad groups and the driving circuit chip.

[0012] The test device can measure a value obtained by dividing a potential difference between at least one of the plurality of fourth output pads of the plurality of output pad groups including the fourth output pad and at least one of the plurality of third output pads of the plurality of output pad groups including the third output pad by current as the resistance.

[0013] The display panel may further include a plurality of input pad groups each including a first input pad. The printed circuit board may include a plurality of input terminals connected to the plurality of input pad groups. The plurality of input terminals may include a plurality of first input terminals electrically connected to a plurality of first input pads of the plurality of input pad groups including the first input pad.

[0014] Current may be supplied to the plurality of first input pads of the plurality of input pad groups through the plurality of first input terminals.

[0015] Each of the input pad groups may include a second input pad that is grounded.

[0016] The plurality of input terminals may further include a second input terminal electrically connected to a grounded second input pad of each of the plurality of input pad groups. Current may flow from the plurality of first input terminals to the second input terminal.

[0017] The second output terminal and the second input terminal may be the same terminal.

[0018] Each of the plurality of input pad groups may include a third input pad and a fourth input pad. The plurality of input terminals may include a plurality of third input terminals electrically connected to a plurality of third input pads of the plurality of input pad groups including the third input pad, and a fourth input terminal electrically connected to a fourth input pad of each of the plurality of input pad groups.

[0019] The test device may be electrically connected to the printed circuit board, and the test device may measure resistance between a grounded second input pad of at least one of the plurality of input pad groups and the printed circuit board.

[0020] The test device can measure a value obtained by dividing the potential difference between at least one of the plurality of fourth input pads of the plurality of input pad groups including the fourth input pad and at least one of the plurality of third input pads of the plurality of input pad groups including the third input pad by the current as the resistance.

[0021] The driving circuit chip may be provided in a chip on plastic (COP) structure or a chip on glass (COG) structure. The printed circuit board may be provided in a film on plastic (FOP) structure or a film on glass (FOG) structure.

[0022] According to another aspect of the present disclosure, a display module is provided, including: a display panel, including a plurality of input pad groups, each including a first input pad and a grounded second input pad; and a printed circuit board, arranged on the display panel, the printed circuit board including a plurality of input terminals connected to the plurality of input pad groups, wherein the plurality of input terminals include a plurality of first input terminals electrically connected to a plurality of first input pads of the plurality of input pad groups including the above-mentioned first input pad, and a second input terminal electrically connected to a grounded second input pad of each of the plurality of input pad groups.

[0023] Each of the plurality of input pad groups may further include a third input pad and a fourth input pad. The plurality of input terminals may further include a plurality of third input terminals electrically connected to a plurality of third input pads of the plurality of input pad groups including the third input pad, and a fourth input terminal electrically connected to a fourth input pad of each of the plurality of input pad groups.

[0024] The test device may be electrically connected to the printed circuit board, and the test device may measure resistance between a grounded second input pad of at least one of the plurality of input pad groups and the printed circuit board.

[0025] According to another aspect of the present disclosure, a display module is provided, including: a display panel, including an input pad group including a first input pad, a grounded second input pad, a third input pad and a fourth input pad; and a printed circuit board, arranged on the display panel, the printed circuit board including a terminal test point structure including a plurality of input terminals connected to the input pad group, wherein the terminal test point structure includes: a first input terminal, electrically connected to a first input pad of the input pad group; a second input terminal, electrically connected to a third input pad of the input pad group and a grounded second input pad; and a third input terminal, electrically connected to a fourth input pad of the input pad group.

[0026] The testing device can be electrically connected to the printed circuit board, and the testing device can measure the magnitude of the current flowing at a measurement point between a first input pad of the input pad group and a second input pad connected to the ground and can measure the voltage between a third input pad and a fourth input pad of the input pad group. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0028] Figure 1 is a plan view showing a display panel according to an embodiment of the present disclosure.

[0029] Figure 2 is a plan view showing a display module testing system according to an embodiment of the present disclosure.

[0030] Figure 3 It is along Figure 1 and Figure 2 A cross-sectional view taken along line II' shown in FIG.

[0031] Figure 4 It is along Figure 2 A cross-sectional view taken along line II-II' is shown in FIG.

[0032] Figure 5 It is along Figure 2 A cross-sectional view taken along line III-III' is shown in FIG.

[0033] Figure 6 is a perspective view showing a terminal test point structure in which a connection resistance may be measured according to an embodiment of the present disclosure.

[0034] Figure 7 It is shown Figure 2 A plan view of a terminal portion of a printed circuit board is shown in FIG.

[0035] Figure 8 is a plan view schematically illustrating a first pad portion and an output terminal according to an embodiment of the present disclosure.

[0036] Fig. 9 is a plan view schematically illustrating a second pad portion and an input terminal according to an embodiment of the present disclosure.

[0037] Fig.10 is a plan view schematically illustrating a first pad portion, a second pad portion, and an input / output terminal according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The inventive concept may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, the embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those of ordinary skill in the art.

[0039] In this specification, elements for understanding the operation according to the present disclosure are described, and descriptions of other elements may be omitted so that the subject matter can be clearly understood.

[0040] In this specification, when an element is referred to as "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or the element may be indirectly connected or coupled to the other element, wherein one or more intermediate elements are between the element and the other element. The technical terms used in this article are used to illustrate the purpose of the embodiment, and are not intended to be restrictive. It will be understood that when a component "includes" an element, it will be understood that the component does not exclude another element, and may further include one or more other elements, unless there is other description to the contrary. It will be understood that for the purpose of this disclosure, "at least one of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purpose of this disclosure, "at least one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z (e.g., XYZ, XY, YZ, XZ).

[0041] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0042] For ease of description, spatially relative terms such as "below" and "above" may be used herein to describe the relationship between one element and another element as shown in the accompanying drawings. It will be understood that, in addition to the orientations described herein and depicted in the accompanying drawings, spatially relative terms and illustrated configurations are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, then the elements described as "below" or "below" other elements or features can be oriented as "above" other elements or features. Therefore, the exemplary term "above" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly.

[0043] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0044] Here, embodiments of the present disclosure are described with reference to the accompanying drawings. Changes in the structures shown in the drawings are expected and may be due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present disclosure should not be limited to the specific structures shown in the drawings. The regions shown in the drawings are schematic in nature, and the shape of the region may not represent the actual shape of the region of the device and may not limit the scope of the present disclosure.

[0045] Figure 1 is a plan view showing a display panel according to an embodiment of the present disclosure. Figure 2 is a plan view showing a display module testing system according to an embodiment of the present disclosure.

[0046] refer to Figure 1 , the display panel DP may be a light-emitting display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel, a quantum dot light-emitting display panel, or other display panels. In the example organic light-emitting display panel, the light-emitting layer includes an organic light-emitting material. In the example quantum dot light-emitting display panel, the light-emitting layer includes quantum dots and quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0047] The display panel DP may include a display area DA and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be an area in which no image is displayed. In an example, the display area DA may be defined as an area in which pixels PX are disposed to provide image information that can be perceived by a user to the outside. The non-display area NDA may be a peripheral area of ​​the display area DA and may surround the display area DA. For example, the non-display area NDA may be defined as an area in which circuits and electronic components for driving the pixels PX are disposed.

[0048] The non-display area NDA may include a first pad portion PDA1 and a second pad portion PDA2. The first pad portion PDA1 may include a plurality of output pads PD1. The second pad portion PDA2 may include a plurality of input pads PD2.

[0049] A plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 forming a plane. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. The pixel PX may display any one of red, green, and blue, for example. However, the present disclosure is not limited thereto, and the pixel PX may display at least one of white, cyan, and magenta. Figure 1 , it is shown that the pixel PX has a quadrangular shape. However, the present disclosure is not limited thereto, and the shape of the pixel PX may be variously changed to have, for example, other polygonal shapes, a circular shape, or an elliptical shape.

[0050] refer to Figure 1 and Figure 2 The display module test system SYS may include a display module DM. In addition, the display module DM may include a test device TD, a display panel DP, a driving circuit chip DIC, and a printed circuit board FPCB.

[0051] The driving circuit chip DIC may be disposed on the display panel DP. For example, the driving circuit chip DIC may be disposed in the non-display area NDA. The driving circuit chip DIC may provide a signal for driving the display panel DP. For example, the driving circuit chip DIC may be a source driver integrated circuit that may provide a data signal to a data line. However, the present disclosure is not limited thereto, and the driving circuit chip DIC may be a combined driver integrated circuit in which both a scan driving circuit and a timing control circuit may be integrated. Figure 2 In some embodiments, one or more driving circuit chips DIC may be disposed on the display panel DP. For example, in some embodiments, a plurality of driving circuit chips DIC may be disposed on the display panel DP.

[0052] In an embodiment of the present disclosure, the driving circuit chip DIC may be disposed on the display panel DP in a chip on glass (COG) structure or a chip on plastic (COP) structure. For example, the driving circuit chip DIC may be disposed on the display panel DP in a COG structure or a COP structure, and may be disposed to overlap with the first pad portion PAD1. In the COP structure, the driving circuit chip DIC and the display area DA may be disposed on the surface of the substrate, and the substrate may be bent where the driving circuit chip DIC may be disposed below the display area DA. In the COG structure, the driving circuit chip DIC and the display area DA may be disposed on the surface of the substrate, and the driving circuit chip DIC may be disposed adjacent to the display area DA. However, the present disclosure is not limited thereto, and the COP structure and the COG structure may be implemented differently.

[0053] The printed circuit board FPCB may be disposed on the display panel DP. For example, the printed circuit board FPCB may be disposed on the display panel DP to overlap with the second pad portion PAD2. The printed circuit board FPCB may be electrically connected to the display panel DP through the second pad portion PAD2. In some embodiments, the printed circuit board FPCB may be electrically connected to the test device TD.

[0054] In this specification, “electrically connected” includes a structure of direct connection between a first electrical component and a second electrical component as well as a structure of connection through another electrical component.

[0055] The printed circuit board FPCB may be connected to an end of the display panel DP. The printed circuit board FPCB may be directly connected to a signal line provided in the display panel DP, or may be connected to a driving circuit chip DIC. The printed circuit board FPCB may transmit a signal received from the outside to the display panel DP or the driving circuit chip DIC.

[0056] The printed circuit board FPCB may be a flexible printed circuit board. Accordingly, the printed circuit board FPCB may be bent in the third direction DR3 or in a direction opposite to the third direction DR3.

[0057] In an embodiment of the present disclosure, the printed circuit board FPCB may be arranged on the display panel DP in a film on plastic (FOP) structure or a film on glass (FOG) structure. For example, the drive circuit chip DIC may be arranged in a COP structure and the printed circuit board FPCB may be arranged in a FOP structure, or the drive circuit chip DIC may be arranged in a COG structure and the printed circuit board FPCB may be arranged in a FOG structure. In the FOP structure, the printed circuit board FPCB and the display area DA may be arranged on the surface of the substrate, and the substrate may be bent at a place where the printed circuit board FPCB may be arranged below the display area DA. In the FOG structure, the printed circuit board FPCB and the display area DA may be arranged on the surface of the substrate, and the printed circuit board FPCB may be bent around the end of the substrate. However, the present disclosure is not limited thereto, and the FOP structure and the FOG structure may be implemented differently.

[0058] In an embodiment of the present disclosure, the display module test system SYS may measure the connection resistance between the first pad portion PDA1 and the driving circuit chip DIC. For example, during a test, the test device TD may be connected to the display panel DP and an electrical signal may be applied to the display panel DP, and the display module test system SYS may measure the connection resistance between the first pad portion PDA1 and the driving circuit chip DIC. In an embodiment of the present disclosure, the display module test system SYS may measure the connection resistance between the second pad portion PDA2 and the printed circuit board FPCB. This will be referred to later. Figure 6 This is described in detail.

[0059] When the test is finished, the printed circuit board FPCB of the display module DM may be connected to a control device that may control the operation of the display panel DP. The test device TD may be disconnected from the display panel DP after the test.

[0060] Figure 3 It is along Figure 1 and Figure 2 A cross-sectional view taken along line II' shown in FIG.

[0061] refer to Figure 3 , the display panel DP may include a first base substrate SUB1, a first layer DP-CL, a second layer DP-OLED and a thin film encapsulation layer TFE.

[0062] The first layer DP-CL may include a plurality of conductive layers and a plurality of insulating layers, and the second layer DP-OLED may include a plurality of conductive layers and a plurality of functional organic layers.

[0063] The display area DA of the display panel DP (see Figure 1) may include an emission region PXA and a non-emission region NPXA. The emission region PXA may be a region in which light generated in the organic light emitting element OLED is emitted in the third direction DR3. The non-emission region NPXA may be adjacent to the emission region PXA and may be a region in which light generated in the organic light emitting element OLED is not emitted in the third direction DR3.

[0064] The semiconductor pattern ALP of the pixel transistor TRP may be disposed on the first base substrate SUB1. The semiconductor pattern ALP may include amorphous silicon. For example, amorphous silicon may be formed at a low temperature. In an embodiment of the present disclosure, the semiconductor pattern ALP may include a metal oxide semiconductor. Although not shown separately, a functional layer may be further disposed on the surface of the first base substrate SUB1. The functional layer may include at least one of a barrier layer and a buffer layer. The semiconductor pattern ALP may be disposed on the barrier layer or the buffer layer.

[0065] The first insulating member ISL1 may cover the pixel transistor TRP and may be disposed on the first base substrate SUB1. The first insulating member ISL1 may include a first insulating layer ISL1-1, a second insulating layer ISL1-2, and a third insulating layer ISL1-3.

[0066] The first insulating layer ISL1-1 may cover the semiconductor pattern ALP and may be disposed on the first base substrate SUB1. The first insulating layer ISL1-1 may include an organic layer and / or an inorganic layer. In particular, the first insulating layer ISL1-1 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0067] The control electrode GEP of the pixel transistor TRP may be disposed on the first insulating layer ISL1 - 1 .

[0068] The second insulating layer ISL1-2 may cover the control electrode GEP and may be disposed on the first insulating layer ISL1-1. The second insulating layer ISL1-2 may include an organic layer and / or an inorganic layer. In particular, the second insulating layer ISL1-2 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0069] The source line and the power line may be disposed on the second insulating layer ISL1-2. The input electrode SEP and the output electrode DEP of the pixel transistor TRP may be disposed on the second insulating layer ISL1-2.

[0070] The input electrode SEP may be connected to the semiconductor pattern ALP through a first penetration hole CH1 penetrating the first insulating layer ISL1-1 and the second insulating layer ISL1-2. The output electrode DEP may be connected to the semiconductor pattern ALP through a second penetration hole CH2 penetrating the first insulating layer ISL1-1 and the second insulating layer ISL1-2. Meanwhile, in an embodiment of the present disclosure, the pixel transistor TRP may be modified into a bottom gate structure.

[0071] The third insulating layer ISL1-3 may cover the input electrode SEP and the output electrode DEP, and may be disposed on the second insulating layer ISL1-2. The third insulating layer ISL1-3 may include an organic layer and / or an inorganic layer. In particular, the third insulating layer ISL-3 may include an organic material to provide a flat surface.

[0072] The pixel defining layer PXL and the organic light emitting element OLED may be disposed on the third insulating layer ISL1-3. An opening OP may be defined in the pixel defining layer PXL. The pixel defining layer PXL may be substantially similar to another insulating layer. The emission region PXA and the non-emission region NPXA may be distinguished from each other by the pixel defining layer PXL.

[0073] The anode AE ​​may be connected to the output electrode DEP through a third penetration hole CH3 penetrating the third insulating layer ISL1-3. The opening OP of the pixel defining layer PXL may expose a portion of the anode AE. The hole control layer HCL may be formed in common in the emission area PXA and the non-emission area NPXA. The organic light-emitting layer EML and the electron control layer ECL may be sequentially formed on the hole control layer HCL. For example, the organic light-emitting layer EML may be formed on the hole control layer HCL, and the electron control layer ECL may be formed on the organic light-emitting layer EML. The cathode CE may be formed in common in the emission area PXA and the non-emission area NPXA. The cathode CE may be formed according to the layer structure by, for example, a deposition process or a sputtering process.

[0074] The thin film encapsulation layer TFE may be disposed over the cathode CE. The thin film encapsulation layer TFE may protect the organic light emitting element OLED from moisture and / or foreign matter.

[0075] Figure 4 It is along Figure 2 A cross-sectional view taken along line II-II' is shown in FIG. Figure 4 Shown along Figure 2 A portion of the cross section taken along line II-II' is shown in FIG.

[0076] refer to Figure 4 The output pad PD1 may be arranged on the display panel DP (see Figure 2). In addition, in the driving circuit chip DIC, the driving pads PD-DIC may be disposed on the bottom of the substrate member SUB-DIC. The output pads PD1 and the driving pads PD-DIC may include metal. Some of the driving pads PD-DIC may be short-circuited to each other.

[0077] The conductive adhesive film ACF may allow the output pad PD1 and the driving circuit chip DIC to be bonded to each other. For example, the conductive adhesive film ACF may be disposed between the output pad PD1 and the driving pad PD-DIC, which may allow the output pad PD1 and the driving circuit chip DIC to be bonded to each other. The conductive adhesive film ACF may be an anisotropic conductive film.

[0078] The conductive adhesive film ACF may include a plurality of conductive balls BL and an insulating adhesive member RN.

[0079] Each of the plurality of conductive balls BL may be a conductive particle. The conductive particles may be capable of performing electrical conduction, and conductive particles such as metal or its oxide or particles obtained by coating a metal or its oxide on a surface and using an insulating material as a core may be used. Nickel (Ni), iron (Fe), copper (Cu), aluminum (Al), tin (Sn), zinc (Zn), chromium (Cr), cobalt (Co), silver (Ag), gold (Au), or the like may be used as the above metal.

[0080] The insulating adhesive member RN may include an insulating polymer. The insulating polymer may include, for example, an epoxy resin or an acrylic resin, etc. The epoxy resin may be configured using a phenoxy polymer that may have an iterative structure of bisphenol A and an ether bond (-CO-C-) and may have an epoxy reactive group at its end. The acrylic resin may be configured using a urethane (meth) acrylate polymer that may have a urethane bond (-NHCO-O) connection structure and may have an acrylate or methacrylate reactive group at its end.

[0081] Display module test system SYS (see Figure 2 ) can measure the connection resistance between the output pad PD1 and the driving circuit chip DIC. For example, the display module test system SYS can measure the connection resistance between the output pad PD1, the conductive ball BL and the driving pad PD-DIC.

[0082] Figure 5 It is along Figure 2 A cross-sectional view taken along line III-III' is shown in FIG. Figure 5 Shown along Figure 2 A portion of a cross section taken along line III-III' is shown in FIG.

[0083] Figure 5The second substrate member SUB2' and the conductive adhesive film ACF' shown in FIG. Figure 4 The second base member SUB2 and the conductive adhesive film ACF shown in FIG. 1 are substantially similar. In addition, Figure 5 The insulating adhesive member RN' shown in FIG. Figure 4 The insulating adhesive member RN shown in FIG. 8 is shown in FIG.

[0084] refer to Figure 5 The input pad PD2 may be arranged on the display panel DP (see Figure 2 The input pad PD2 may include metal.

[0085] The conductive adhesive film ACF' may allow the input pad PD2 and the printed circuit board FPCB to be bonded to each other. In addition, in the printed circuit board FPCB, the printed circuit board pad PD-FPCB may be disposed on the bottom of the printed circuit board base member SUB-FPCB. For example, the conductive adhesive film ACF' may be disposed between the input pad PD2 and the printed circuit board pad PD-FPCB. The conductive adhesive film ACF' may allow the input pad PD2 and the printed circuit board FPCB to be bonded to each other.

[0086] Display module test system SYS (see Figure 2 ) can measure the connection resistance between the input pad PD2 and the printed circuit board FPCB. For example, the display module test system SYS can measure the connection resistance between the input pad PD2, the conductive ball BL' and the printed circuit board pad PD-FPCB.

[0087] Figure 6 is a perspective view showing a terminal test point structure in which a connection resistance can be measured according to an embodiment of the present disclosure.

[0088] Figure 6 An example is shown in which the lower pads PD-D1, PD-D2, PD-D3, and PD-D4 and the upper pads PD-U1, PD-U2, and PD-U3 are bonded to each other through a conductive adhesive film ACF. Figure 6 The lower pads PD-D1, PD-D2, PD-D3 and PD-D4 shown in FIG. Figure 4 The output pad PD1 is shown in Figure 6 The upper pads PD-U1, PD-U2 and PD-U3 shown in FIG. Figure 4 In the embodiment, Figure 6 The lower pads PD-D1, PD-D2, PD-D3 and PD-D4 shown in FIG. Figure 5 The input pad PD2 is shown in FIG. Figure 6 The upper pads PD-U1, PD-U2 and PD-U3 shown in FIG. Figure 5 The printed circuit board pads PD-FPCB are shown.

[0089] refer to Figure 6 , the lower pads PD-D1, PD-D2, PD-D3 and PD-D4 include a first lower pad PD-D1, a second lower pad PD-D2, a third lower pad PD-D3 and a fourth lower pad PD-D4. The upper pads PD-U1, PD-U2 and PD-U3 include a first upper pad PD-U1, a second upper pad PD-U2 and a third upper pad PD-U3. The first lower pad PD-D1 can be connected to the first upper pad PD-U1. The second lower pad PD-D2 and the third lower pad PD-D3 can be connected to the second upper pad PD-U2. The fourth lower pad PD-D4 can be connected to the third upper pad PD-U3.

[0090] Figure 6 The display module test system SYS (see Figure 2 ) An example in which the connection resistance between the second lower pad PD-D2 and the second upper pad PD-U2 can be measured.

[0091] The first lower pad PD-D1 may be a current applying terminal, the second lower pad PD-D2 may be a current detecting terminal, and the third lower pad PD-D3 and the fourth lower pad PD-D4 may be voltage applying terminals. Figure 2 ) can apply current to the first lower pad PD-D1. For example, the test device TD can pass a plurality of output terminals TP (see Figure 8 ) and / or multiple input terminals TP' (see Fig. 9 ) applies current to the first lower pad PD-D1. The second lower pad PD-D2 may be in a ground state, and the current applied to the first lower pad PD-D1 may flow to the second lower pad PD-D2. Accordingly, the display module test system SYS (see Figure 2 ) can measure the magnitude of the current flowing at the measurement point. In addition, the display module test system SYS can measure the voltage between the third lower pad PD-D3 and the fourth lower pad PD-D4.

[0092] In some embodiments, the display module test system SYS can use a multimeter to measure the potential difference between the third lower pad PD-D3 and the fourth lower pad PD-D4, and can measure the voltage at the measurement point (for example, the voltage between the second lower pad PD-D2 and the second upper pad PD-U2). Therefore, the display module test system SYS can measure the current and voltage at the measurement point. The display module test system SYS can calculate the connection resistance at the measurement point, for example, according to the relationship of voltage = current × resistance. For example, the resistance can be a value obtained by dividing the potential difference between the third lower pad PD-D3 and the fourth lower pad PD-D4 by the current flowing at the measurement point.

[0093] Figure 7 It is shown Figure 2 A plan view of a terminal portion of a printed circuit board is shown in FIG.

[0094] refer to Figure 7 The printed circuit board FPCB may include a plurality of terminals TP and TP'. For example, the printed circuit board FPCB may include a plurality of terminals TP and TP' disposed on the terminal portion TPA.

[0095] The plurality of terminals TP and TP' may be connected to the test device TD. Accordingly, the test device TD may provide an electrical signal to the plurality of terminals TP and TP'. For example, the test device TD may apply a test current to the plurality of terminals TP and TP', and may measure a connection resistance between the first pad portion PDA1 and the drive circuit chip DIC or a connection resistance between the second pad portion PDA2 and the printed circuit board FPCB.

[0096] A plurality of terminals TP and TP' may be connected to the first pad portion PDA1 and the second pad portion PDA2. For example, the printed circuit board FPCB may include a plurality of lines EW electrically connecting the terminal portion TPA to the first pad portion PDA1 and the second pad portion PDA2. Accordingly, the plurality of terminals TP and TP' may supply an electrical signal transmitted from the test device TD to the first pad portion PDA1 and the second pad portion PDA2. For example, the plurality of terminals TP and TP' may supply a test current to the first pad portion PDA1 and the second pad portion PDA2.

[0097] The plurality of terminals TP and TP' may include an output terminal TP and an input terminal TP'. The output terminal TP and the input terminal TP' may be arranged in parallel in a certain direction. For example, the output terminal TP may be arranged in a first direction DR1, and the input terminal TP' may be arranged in parallel with the output terminal TP in the first direction DR1. However, the present disclosure is not limited thereto. For example, the output terminal TP and the input terminal TP' may be arranged alternately in the first direction DR1 while alternating with each other in the second direction DR2.

[0098] Figure 8 is a plan view schematically illustrating a first pad portion and an output terminal according to an embodiment of the present disclosure.

[0099] refer to Figure 8 , the first pad portion PDA1 may include a first output pad group PD1-G1 and a second output pad group PD1-G2. Figure 8 Two output pad groups are shown as an example in FIG. 1 , but the present disclosure is not limited thereto.

[0100] Each of the output pad groups PD1-G1 and PD1-G2 may include a plurality of output pads PD1 (see Figure 7 ). For example, the first output pad group PD1-G1 may include first to fourth output pads G1-OD1, G1-OD2, G1-OD3, and G1-OD4, and the second output pad group PD1-G2 may also include first to fourth output pads G2-OD1, G2-OD2, G2-OD3, and G2-OD4.

[0101] The first to fourth output pads G1-OD1, G1-OD2, G1-OD3, and G1-OD4 of the first output pad group PD1-G1 and the first to fourth output pads G2-OD1, G2-OD2, G2-OD3, and G2-OD4 of the second output pad group PD1-G2 may be respectively connected to Figure 6 The lower pads PD-D1, PD-D2, PD-D3 and PD-D4 shown in the figure correspond to each other.

[0102] Output pad groups PD1-G1 and PD1-G2 may include grounded output pads G1-OD2 and G2-OD2, respectively. For example, the first output pad group PD1-G1 may include grounded second output pads G1-OD2, and the second output pad group PD1-G2 may include grounded second output pads G2-OD2.

[0103] The output terminal TP can be provided in the terminal portion TPA (see Figure 7 The output terminal TP may include a first output terminal TP1, a second output terminal TP2, a third output terminal TP3_a, a fourth output terminal TP3_b, and a fifth output terminal TP4.

[0104] The first output terminal TP1 can receive the signal from the test device TD (see Figure 7 For example, the first output terminal TP1 can receive a test current transmitted from the test device TD.

[0105] The first output terminal TP1 may be connected to each of the first output pads G1-OD1 and G2-OD1 of the output pad groups PD1-G1 and PD1-G2. That is, the test device TD may supply a test current to the first output pads G1-OD1 and G2-OD1 through the first output terminal TP1.

[0106] The second output terminal TP2 may be connected to the second output pad G1-OD2 of the first output pad group PD1-G1 and the second output pad G2-OD2 of the second output pad group PD1-G2. The test current supplied to the first output terminal TP1 may flow to the second output terminal TP2. For example, the test current supplied to each of the first output pads G1-OD1 and G2-OD1 of the output pad groups PD1-G1 and PD1-G2 may flow to each of the grounded second output pads G1-OD2 of the first output pad group PD1-G1 and the grounded second output pads G2-OD2 of the second output pad group PD1-G2. The test current may flow to the second output terminal TP2 connected to the second output pads G1-OD2 and G2-OD2.

[0107] The third output terminal TP3_a may be connected to the third output pad G1-OD3 of the first output pad group PD1-G1. The fourth output terminal TP3_b may be connected to the third output pad G2-OD3 of the second output pad group PD1-G2.

[0108] The fifth output terminal TP4 may be connected to the fourth output pad G1 - OD4 of the first output pad group PD1 - G1 and the fourth output pad G2 - OD4 of the second output pad group PD-G2 .

[0109] As reference Figure 6 As described above, the display module test system SYS (see Figure 2 ) can measure the difference between each of the output pad groups PD1-G1 and PD1-G2 and the drive circuit chip DIC (see Figure 7) between the first output terminal TP1 and the second output terminal TP2. For example, the display module test system SYS can measure the magnitude of the test current flowing from the first output terminal TP1 to the second output terminal TP2. After measuring the magnitude of the test current flowing from the first output terminal TP1 to the second output terminal TP2, the display module test system SYS can measure the potential difference between the third output pad G1-OD3 and the fourth output pad G1-OD4. The voltage between the second output pad G1-OD2 and the drive circuit chip DIC can be determined using the potential difference between the third output pad G1-OD3 and the fourth output pad G1-OD4. Accordingly, the display module test system SYS can measure the connection resistance between the second output pad G1-OD2 and the drive circuit chip DIC. For ease of description, a method for measuring the connection resistance between the first output pad group PD1-G1 and the drive circuit chip DIC has been described, but the present disclosure is not limited thereto.

[0110] According to an embodiment of the present disclosure, the design of the printed circuit board FPCB of the display module test system SYS can be improved. For example, the first output terminal TP1 can be connected to the first output pad G1-OD1 of the first output pad group PD1-G1 and the first output pad G2-OD1 of the second output pad group PD1-G2. According to an embodiment of the present disclosure, the number of lines connected from the first output terminal TP1 to the first output pads G1-OD1 and G2-OD1 can be reduced.

[0111] When implementing output terminals connected to eight output pads respectively, a space in which the eight output terminals are to be arranged may be required on the printed circuit board. In addition, the number of lines connecting the eight output terminals and the eight output pads to each other respectively may be relatively large.

[0112] In some embodiments, the output terminal TP may include five output terminals TP1, TP2, TP3_a, TP3_b, and TP4. Accordingly, the printed circuit board FPCB may require a relatively small space in which the output terminal TP is disposed. In addition, a relatively small space in which a line connecting the output terminal TP and the output pad groups PD1-G1 and PD1-G2 to each other is disposed may also be used. Therefore, the printed circuit board FPCB according to an embodiment of the present disclosure may be designed relatively easily.

[0113] Fig. 9 is a plan view schematically illustrating a second pad portion and an input terminal according to an embodiment of the present disclosure.

[0114] refer to Fig. 9 , the second pad portion PDA2 may include a plurality of input pad groups PD2-G1 and PD2-G2. For example, the second pad portion PDA2 may include a first input pad group PD2-G1 and a second input pad group PD2-G2. Fig. 9 Two input pad groups are shown as an example in FIG. 1 , but the present disclosure is not limited thereto.

[0115] Each of the input pad groups PD2-G1 and PD2-G2 may include a plurality of input pads PD2 (see Figure 7 ). For example, the first input pad group PD2-G1 may include first to fourth input pads G1-ID1, G1-ID2, G1-ID3, and G1-ID4, and the second input pad group PD2-G2 may include first to fourth input pads G2-ID1, G2-ID2, G2-ID3, and G2-ID4.

[0116] The first to fourth input pads G1-ID1, G1-ID2, G1-ID3, and G1-ID4 of the first input pad group PD2-G1 and the first to fourth input pads G2-ID1, G2-ID2, G2-ID3, and G2-ID4 of the second input pad group PD2-G2 may be respectively connected to Figure 6 The lower pads PD-D1, PD-D2, PD-D3 and PD-D4 shown in the figure correspond to each other.

[0117] The input pad groups PD2-G1 and PD2-G2 may include grounded input pads G1-ID2 and G2-ID2, respectively. For example, the first input pad group PD2-G1 may include a grounded second input pad G1-ID2, and the second input pad group PD2-G2 may include a grounded second input pad G2-ID2.

[0118] The input terminal TP' can be arranged in the terminal part TPA (see Figure 7 The input terminal TP' may include a first input terminal TP1'_a, a second input terminal TP1'_b, a third input terminal TP2', a fourth input terminal TP3'_a, a fifth input terminal TP3'_b, and a sixth input terminal TP4'.

[0119] The first input terminal TP1 ′_a and the second input terminal TP1 ′_b can receive the data from the test device TD (see Figure 7 For example, the first input terminal TP1'_a and the second input terminal TP1'_b may receive a test current transmitted from the test device TD.

[0120] The first input terminal TP1'_a can be connected to the first input pad G1-ID1 of the first input pad group PD2-G1, and the second input terminal TP1'_b can be connected to the first input pad G2-ID1 of the second input pad group PD2-G2. The test device TD can supply a test current to the first input pads G1-ID1 and G2-ID1 through the first input terminal TP1'_a and the second input terminal TP1'_b, respectively.

[0121] The third input terminal TP2' can be connected to the second input pad G1-ID2 of the first input pad group PD2-G1 and the second input pad G2-ID2 of the second input pad group PD2-G2. The test current supplied to the first input terminal TP1'_a and the second input terminal TP1'_b can flow to the third input terminal TP2'. For example, the test current supplied to each of the first input pads G1-ID1 and G2-ID1 of the input pad groups PD2-G1 and PD2-G2 can flow to each of the grounded second input pads G1-ID2 of the first input pad group PD2-G1 and the grounded second input pads G2-ID2 of the second input pad group PD2-G2. Accordingly, the test current can flow to the third input terminal TP2' connected to the second input pads G1-ID2 of the first input pad group PD2-G1 and the second input pads G2-ID2 of the second input pad group PD2-G2, respectively.

[0122] The fourth input terminal TP3 ′_a may be connected to the third input pad G1 - ID3 of the first input pad group PD2 - G1 , and the fifth input terminal TP3 ′_b may be connected to the third input pad G2 - ID3 of the second input pad group PD2 - G2 .

[0123] The sixth input terminal TP4 ′ may be connected to the fourth input pad G1 - ID4 of the first input pad group PD2 - G1 and the fourth input pad G2 - ID4 of the second input pad group PD2 - G2 .

[0124] As reference Figure 6 As described above, the display module test system SYS (see Figure 2 ) can measure the difference between each of the input pad groups PD2-G1 and PD2-G2 and the printed circuit board FPCB (see Figure 7). For example, the display module test system SYS can measure the magnitude of the test current flowing from the first input terminal TP1'_a to the third input terminal TP2'. After measuring the magnitude of the test current flowing from the first input terminal TP1'_a to the third input terminal TP2', the display module test system SYS can measure the potential difference between the third input pad G1-ID3 and the fourth input pad G1-ID4. The voltage between the second input pad G1-ID2 and the printed circuit board FPCB can be determined using the potential difference between the third input pad G1-ID3 and the fourth input pad G1-ID4. Accordingly, the display module test system SYS can measure the connection resistance between the second input pad G1-ID2 and the printed circuit board FPCB. For ease of description, a method for measuring the connection resistance between the first input pad group PD2-G1 and the printed circuit board FPCB has been described, but the present disclosure is not limited thereto.

[0125] According to an embodiment of the present disclosure, the design of the printed circuit board FPCB of the display module test system SYS can be improved. For example, the design of the printed circuit board FPCB can be simplified. For example, the third input terminal TP2' can be connected to the second input pad G1-ID2 of the first input pad group PD2-G1 and the second input pad G2-ID2 of the second input pad group PD2-G2. Accordingly, the number of lines connected from the third input terminal TP2' to the second input pads G1-ID2 and G2-ID2 can be reduced. Accordingly, the printed circuit board FPCB can use a relatively small space in which the input terminal TP' is set. In addition, a relatively small space in which the line connecting the input terminal TP' to the first input pad group PD2-G1 and the second input pad group PD2-G2 can also be used. Therefore, the printed circuit board FPCB according to an embodiment of the present disclosure can be designed relatively easily.

[0126] Fig.10 is a plan view schematically illustrating a first pad portion, a second pad portion, and an input / output terminal according to an embodiment of the present disclosure.

[0127] refer to Fig.10 , the first pad portion PDA1 may include a plurality of output pad groups PD1-G1 and PD1-G2, and the second pad portion PDA2 may include a plurality of input pad groups PD2-G1 and PD2-G2.

[0128] Fig.10 The first pad portion PDA1 and the second pad portion PDA2 shown in FIG. Figure 8 The first pad portion PDA1 and Fig. 9 The second pad portion PDA2 shown in FIG. 1 is substantially similar.

[0129] in addition, Fig.10 The first input / output terminal MTP1, the third input / output terminal MTP3_a, the fourth input / output terminal MTP3_b and the fifth input / output terminal MTP4 of the first input / output terminal group MTP_O shown in FIG. Figure 8 The first output terminal TP1, the third output terminal TP3_a, the fourth output terminal TP3_b and the fifth output terminal TP4 shown in FIG. 1 are substantially similar.

[0130] also, Fig.10 The first input / output terminal MTP1'_a, the second input / output terminal MTP1'_b, the fourth input / output terminal MTP3'_a, the fifth input / output terminal MTP3'_b and the sixth input / output terminal MTP4' of the second input / output terminal group MTP_I shown in FIG. Fig. 9 The first input terminal TP1 ′_a, the second input terminal TP1 ′_b, the fourth input terminal TP3 ′_a, the fifth input terminal TP3 ′_b and the sixth input terminal TP4 ′ shown in FIG. 1 are substantially similar.

[0131] The input / output terminal group MTP can be set on the printed circuit board FPCB (see Figure 7 ) terminal part TPA (see Figure 7 The input / output terminal group MTP may include a first input / output terminal group MTP_O and a second input / output terminal group MTP_I.

[0132] The first input / output terminal group MTP_O may include a first input / output terminal MTP1 , an input / output terminal MTP2 , a third input / output terminal MTP3_a , a fourth input / output terminal MTP3_b , and a fifth input / output terminal MTP4 .

[0133] The second input / output terminal group MTP_I may include first, second, MTP1'_a, MTP1'_b, MTP2, fourth, MTP3'_a, fifth, and sixth input / output terminals MTP3'_b and MTP4'.

[0134] The first input / output terminal MTP1 of the first input / output terminal group MTP_O may be connected to the first output pads G1-OD1 and G2-OD1 of the output pad groups PD1-G1 and PD1-G2 (see Figure 8 ) Each of the first input / output terminals MTP1'_a of the second input / output terminal group MTP_I may be connected to the first input pad G1-ID1 of the first input pad group PD2-G1 (see Fig. 9 ), and the second input / output terminal MTP1′_b of the second input / output terminal group MTP_I may be connected to the first input pad G2-ID1 of the second input pad group PD2-G2 (see Fig. 9 ).

[0135] The first input / output terminal MTP1 of the first input / output terminal group MTP_O can receive a signal from the test device TD (see Figure 7 For example, the first input / output terminal MTP1 of the first input / output terminal group MTP_O can receive the test current transmitted from the test device TD.

[0136] In addition, the first input / output terminal MTP1'_a and the second input / output terminal MTP1'_b of the second input / output terminal group MTP_I can receive an electrical signal transmitted from the test device TD. For example, the first input / output terminal MTP1'_a and the second input / output terminal MTP1'_b of the second input / output terminal group MTP_I can receive a test current transmitted from the test device TD.

[0137] The input / output terminal MTP2 may be connected to the second output pads G1-OD2 and G2-OD2 of the output pad groups PD1-G1 and PD1-G2 (see Figure 8 ) and the second input pads G1-ID2 and G2-ID2 of the input pad groups PD2-G1 and PD2-G2 (see Fig. 9 ) in each of the .

[0138] The third input / output terminal MTP3_a of the first input / output terminal group MTP_O may be connected to the third output pad G1-OD3 of the first output pad group PD1-G1 (see Figure 8 ), and the fourth input / output terminal MTP3_b of the first input / output terminal group MTP_O may be connected to the third output pad G2-OD3 of the second output pad group PD1-G2 (see Figure 8 ).

[0139] The fifth input / output terminal MTP4 of the first input / output terminal group MTP_O may be connected to the fourth output pad G1-OD4 of the first output pad group PD1-G1 and the fourth output pad G2-OD4 of the second output pad group PD1-G2.

[0140] The fourth input / output terminal MTP3'_a of the second input / output terminal group MTP_I may be connected to the third input pad G1-ID3 of the first input pad group PD2-G1 (see Fig. 9), and the fifth input / output terminal MTP3'_b of the second input / output terminal group MTP_I may be connected to the third input pad G2-ID3 of the second input pad group PD2-G2 (see Fig. 9 ).

[0141] The sixth input / output terminal MTP4' of the second input / output terminal group MTP_I may be connected to the fourth input pad G1-ID4 of the first input pad group PD2-G1 (see Fig. 9 ) and the fourth input pad G2-ID4 of the second input pad group PD2-G2 (see Fig. 9 ).

[0142] According to an embodiment of the present disclosure, the design of the printed circuit board FPCB of the display module test system SYS can be improved. For example, the design of the printed circuit board FPCB can be simplified. In some embodiments, the printed circuit board FPCB can include ten input / output terminals.

[0143] When the input / output terminals are respectively connected to eight output pads provided on the first pad portion PDA1 and eight input pads provided on the second pad portion PDA2, a space in which sixteen input / output terminals and lines respectively extending from the sixteen input / output terminals are provided can be used.

[0144] On the other hand, the input / output terminal group MTP according to the embodiment of the present disclosure includes ten input / output terminals, and therefore, the printed circuit board FPCB may be relatively easily designed.

[0145] According to the present disclosure, a display module including a printed circuit board having an improved design may be provided. For example, a display module including a printed circuit board may have a simplified design.

[0146] Example embodiments have been disclosed herein, and although specific terms are employed, these terms are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Accordingly, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display module, comprising: The display panel comprises a plurality of output pad groups, each of the plurality of output pad groups comprising a first output pad; A driving circuit chip, disposed on the display panel and overlapping the plurality of output pad groups; as well as a printed circuit board disposed on the display panel, the printed circuit board comprising a plurality of output terminals electrically connected to the plurality of output pad groups, The plurality of output terminals include a first output terminal electrically connected to the first output pad of each of the plurality of output pad groups.

2. The display module according to claim 1, wherein: Each of the plurality of output pad groups further includes a second output pad connected to ground.

3. The display module according to claim 2, wherein: The plurality of output terminals further include a second output terminal electrically connected to the grounded second output pad of each of the plurality of output pad groups, and Here, the current supplied to the first output pad of each of the plurality of output pad groups through the first output terminal flows from the first output terminal to the second output terminal.

4. The display module according to claim 3, wherein: Each of the plurality of output pad groups further includes a third output pad and a fourth output pad, and The plurality of output terminals further include a plurality of third output terminals electrically connected to the third output pad of each of the plurality of output pad groups and a fourth output terminal electrically connected to the fourth output pad of each of the plurality of output pad groups.

5. The display module according to claim 4, further comprising: A test device, electrically connected to the printed circuit board, The testing device measures the resistance between the grounded second output pad of at least one output pad group among the plurality of output pad groups and the driving circuit chip.

6. The display module according to claim 5, wherein: The test device measures a value obtained by dividing a potential difference between at least one of a plurality of fourth output pads of the plurality of output pad groups including the fourth output pad and at least one of a plurality of third output pads of the plurality of output pad groups including the third output pad by the current as the resistance.

7. The display module according to any one of claims 1 to 6, wherein: The driving circuit chip is arranged in a chip-on-plastic structure or a chip-on-glass structure, and Wherein, the printed circuit board is provided with a plastic upper film structure or a glass upper film structure.

8. A display module, comprising: The display panel includes a plurality of input pad groups each including a first input pad and a grounded second input pad; as well as a printed circuit board disposed on the display panel, the printed circuit board comprising a plurality of input terminals connected to the plurality of input pad groups, The multiple input terminals include multiple first input terminals electrically connected to multiple first input pads of the multiple input pad groups including the first input pad, and second input terminals electrically connected to the grounded second input pad of each input pad group in the multiple input pad groups.

9. The display module according to claim 8, wherein: Each of the plurality of input pad groups further includes a third input pad and a fourth input pad, and Among them, the multiple input terminals further include multiple third input terminals electrically connected to the multiple third input pads of the multiple input pad groups including the third input pad, and a fourth input terminal electrically connected to the fourth input pad of each input pad group in the multiple input pad groups.

10. The display module according to claim 8, further comprising: A test device, electrically connected to the printed circuit board, The testing device measures the resistance between the grounded second input pad of at least one input pad group among the plurality of input pad groups and the printed circuit board.

11. A display module, comprising: The display panel includes an input pad group including a first input pad, a grounded second input pad, a third input pad, and a fourth input pad; as well as a printed circuit board disposed on the display panel, the printed circuit board comprising a terminal test point structure including a plurality of input terminals connected to the input pad group, Wherein, the terminal test point structure includes: a first input terminal electrically connected to the first input pad of the input pad group; a second input terminal electrically connected to the grounded second input pad and the third input pad of the input pad group; and The third input terminal is electrically connected to the fourth input pad of the input pad group.

12. The display module according to claim 11, further comprising: A test device, electrically connected to the printed circuit board, The test device measures the magnitude of the current flowing at a measurement point between the first input pad of the input pad group and the grounded second input pad, and measures the voltage between the third input pad and the fourth input pad of the input pad group.

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