Method of depositing silicon-based dielectric film

Abstract

A method of forming a high aspect ratio structure within a 3D NAND structure is provided. The method includes delivering a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of diaminosilanes, aminosilanes, and combinations of the above. The method includes delivering an oxygenated compound to the high aspect ratio opening. The precursor and the oxygenated compound cyclically alternate to fill the high aspect ratio opening.

Description

Technical Field

[0001] Embodiments of the present disclosure are generally directed to chemistries and methods for forming high aspect ratio features that are substantially free of voids and seams. Background Art

[0002] Memory devices achieve increased capacity through density scaling involving stacking memory cells vertically in layers. These high aspect ratio structures present various processing challenges, particularly in large area gap filling. Currently, large area gap filling is accomplished using a plasma enhanced chemical vapor deposition process to deposit silicon-containing films. In addition to conformality challenges, conventional PECVD processes tend to create seam and void challenges. The silicon-containing film is then etched to form a memory opening, which is filled with a conductive metal to form a connection. Forming the connection can result in cracking and other defects, which can be problematic in downstream processes.

[0003] Therefore, there is a need for large area gapfill processes and chemistries that achieve high yield and high quality devices with structures that are substantially free of voids and seams. Summary of the invention

[0004] In some embodiments, a method for forming a high aspect ratio structure in a 3D NAND structure is provided. The method includes delivering a precursor to a high aspect ratio opening disposed in a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of: diaminosilane, aminosilane, and a combination of the above items. The method includes delivering an oxygen-containing compound to the high aspect ratio opening. The precursor and the oxygen-containing compound are cyclically alternated to fill the high aspect ratio opening.

[0005] In some embodiments, a method of forming a 3D NAND structure is provided. The method includes delivering a precursor to a high aspect ratio opening disposed in a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of: diaminosilane, aminosilane, and a combination of the above. The method includes delivering an oxygen-containing plasma to the high aspect ratio opening. The precursor and the oxygen-containing plasma are cyclically alternated to fill the high aspect ratio opening with a silicon-containing material. The method includes etching an opening in the silicon-containing material.

[0006] In some embodiments, a method of forming a 3D NAND structure on a substrate is provided. The method includes delivering a precursor to a high aspect ratio opening disposed in a multilayer stack having two or more alternating layers, the precursor including diaminosilane. The method includes delivering an oxygen-containing plasma to the high aspect ratio opening. The precursor and the oxygen-containing plasma are cyclically alternated to fill the high aspect ratio opening with a silicon-containing material. The high aspect ratio opening includes an aspect ratio of about 10:1 or greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order that the above-recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly outlined above may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of their scope, and other equally effective embodiments may be admitted.

[0008] Figure 1 A process flow diagram is depicted of a method according to some embodiments described herein.

[0009] Figure 2 Depicted is a memory device having a staircase structure prior to depositing a gap fill material according to some embodiments described herein.

[0010] Figure 3 Depicted is a first view of a memory device having a staircase structure and a gap-fill material according to some embodiments described herein.

[0011] Figure 4 Depicted is a second view of a memory device having a staircase structure and a gap-fill material according to some embodiments described herein.

[0012] Figure 5 Depicted is a memory device having a stepped structure, a gap-fill material, and a memory opening according to some embodiments described herein.

[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0014] Recently, high-density memory devices including three-dimensional (3D) stacked memory structures have been developed. For example, a 3D NAND stacked memory device can be formed by an array of alternating vertical stacks of dielectric materials and conductive layers (e.g., tungsten-containing layers). An etching method is used to form a stepped structure with alternating vertical stacks of dielectric materials. Large-area, high-aspect ratio openings are formed during the etching method for forming the stepped structure. In some embodiments, the large-area, high-aspect ratio openings have a depth of about 10 μm to about 15 μm and a width of about 1 μm to about 2 μm. In some embodiments, the aspect ratio of the opening is about 5:1 to about 50:1, such as about 10:1 to about 20:1. The high aspect ratio openings are filled with a dielectric material, such as a silicon-containing material.

[0015] The memory opening is formed and extends vertically through the silicon-containing material layer and the dielectric material layer in the alternating stack to expose a portion of the conductive layer. The memory opening has different depths in the alternating stacking structure. The memory opening is eventually filled with a conductive material to form a connection with the exposed portion of each conductive layer in each layer of the alternating stack. The conductive layer in the alternating stack can be used as a word line of a 3D NAND stacked memory device, and the bit line overlying the array of the memory stacking structure can be connected to the drain side of the semiconductor channel. During etching and filling the memory opening with a conductive material, cracks and defects may be formed along the connection, especially at the bottom and top of the connection. Without being bound by theory, it is believed that cracks and defects may be formed if the silicon-containing material has tensile stress. It has been found that using the process described herein to deposit a silicon-containing material can provide a large area gap filling with compressive stress. The compressive nature of the silicon-containing material enables the formation of memory openings and connections without cracking.

[0016] Additionally, filling large areas (e.g., large area gap filling) with silicon-containing materials may form voids and seams, which may lead to quality issues such as cracking and shrinkage of storage devices in downstream processing. The process described herein optimizes large area gap filling while reducing the possibility of shrinkage and stress, and also improves film quality. The method described herein uses a diaminosilane precursor, an aminosilane precursor, or a combination of the above items in an atomic layer deposition process to deposit silicon-containing materials, such as silicon-based dielectric films. In particular, a 3D NAND structure can be formed by stacking alternating films and forming a channel through the stack of alternating films. Conventional methods for filling high aspect ratio openings with silicon-containing materials include using a plasma enhanced chemical vapor deposition (PECVD) process. Films deposited in a conventional manner typically have tensile properties, which leads to device cracking after subsequent processing (such as during etching and metal connection formation). It has been found that the chemical substances and use of atomic layer deposition (ALD) described herein achieve deposition of films with compressive properties and not prone to cracking. The resulting device maintains structural integrity after further processing.

[0017] Figure 1 A process flow chart of an example method 100 according to some embodiments is depicted. Method 100 includes delivering a precursor to a high aspect ratio opening in operation 102. The precursor includes diaminosilane, aminosilane, or a combination of the above items. The precursor is pulsed for about 200 milliseconds (ms) to about 1200 ms, such as about 400 ms to about 1000 ms. In some embodiments, the precursor flows at a rate of about 350 mg / m to about 1400 mg / m (such as about 400 mg / m to about 1200 mg / m, such as about 500 mg / m to about 1000 mg / m, such as about 600 mg / m to about 800 mg / m). In some embodiments, the precursor is delivered as a mixture with a carrier gas (such as argon). The total flow rate of the mixture is about 1500 sccm to about 2500 sccm, such as about 1700 sccm to about 2300 sccm. The temperature of the substrate is maintained at about 350° C. to about 650° C., such as about 450° C. to about 550° C. The pressure is about 2 Torr to about 10 Torr, such as about 4 Torr to about 8 Torr. As used herein, all flow rates and process conditions provided are for a chamber processing a substrate having a substrate diameter of about 300 nm. Other process condition ranges are also contemplated, which can be scaled to suit other processing chamber sizes.

[0018] In operation 106, the method includes delivering an oxygen-containing compound to a high aspect ratio opening. In some embodiments, the oxygen-containing compound is an oxygen-containing plasma delivered from a remote plasma source. Oxygen (O2) gas is provided to the remote plasma source at a flow rate of about 1000sccm to about 3000sccm (such as about 1500sccm to 2500sccm, such as about 2000sccm to 2250sccm). In some embodiments, a carrier gas is delivered to the high aspect ratio opening at a rate of about 0sccm to about 3000sccm (such as about 100sccm to about 2000sccm, such as about 500sccm to about 1000sccm). It has been found that delivering an oxygen-containing compound from a remote plasma source can improve film quality and reduce seams in the filled opening. The oxygen-containing compound may include O3 (e.g., ozone), H2O2 (e.g., peroxide), oxygen plasma, or a combination of the above items.

[0019] In some embodiments, the oxygen-containing compound is pulsed for about 2 seconds to about 10 seconds, such as about 2 seconds to about 8 seconds, such as about 4 seconds to about 6 seconds. In some embodiments, the time pulse ratio of the precursor to the oxygen-containing plasma is about 1:100 to about 1:2, such as about 1:20 to about 1:5, such as about 1:12 to about 1:8, such as about 1:10 to about 1:7. The power source coupled to the remote plasma source excites the gas delivered to the remote plasma source with a power of about 100W to about 300W (such as about 200W to about 250W) and a frequency of about 2MHz to about 60MHz (such as about 13MHz to about 60MHZ, such as 13.56MHz or about 27MHz, or about 40MHz, or about 60MHz). It has been found that tuning the power and frequency applied to the plasma, such as using increased power and frequency during treatment and oxidation, achieves filling of high aspect ratio openings by gap filling with substantially no voids and substantially no seams. Without being bound by theory, it is believed that increasing power and frequency generates more free radicals needed for the reaction to deposit the film, and the concentration of free radicals can be increased to increase the growth per cycle of deposition, such as when the growth per cycle begins to decrease.

[0020] Operations 102 and 106 are cyclically alternated to fill high aspect ratio openings, such as in an atomic layer deposition process. Method 100 can be combined with a PECVD process to increase the gap filling rate of the opening. In some embodiments, PECVD is used to deposit about 10% to about 50% of the total thickness of the gap filling for the opening, such as about 20% to about 30%, and then ALD deposition is used to deposit the remaining thickness. Method 100 can be used in any high aspect ratio opening of a variety of semiconductor devices. In some embodiments, in optional operations 104, 108, a purge gas is supplied to the opening between each pulse. The purge gas can be a non-reactive gas, such as a nitrogen-containing gas (e.g., diatomic nitrogen), an argon-containing gas (e.g., argon), or a combination of the above items. As used herein, a process cycle includes operations 102, 106, and optional operations 104, 108 between each operation of 102 and 106. The process described herein provides a film deposition growth per cycle of about 1.5Å to about 3Å per cycle (such as about 1.75Å to 2.25Å per cycle). In some embodiments, during one or more of operations 102, 104, 106, 108, the substrate is maintained at a temperature of about 100°C to about 450°C (such as about 150°C to about 350°C, such as about 200°C to about 325°C). In some embodiments, the chamber is maintained at a pressure of about 2 Torr to about 10 Torr (such as about 4 Torr to about 8 Torr). Without being bound by theory, it is believed that increasing the temperature of the substrate increases the compressive strength of the deposited silicon-containing gap fill material.

[0021] In some embodiments, the deposited film (e.g., gap fill material) has a film conformality of about 98% to about 100%. In some embodiments, the deposited film has a shrinkage of less than 15% (such as about 0.1% to about 5%, such as about 1% to about 3%, or about 7% to about 10%). As used herein, "shrinkage" refers to the percentage reduction in the dimension (such as width or thickness) of the deposited film after annealing at a temperature of about 850° C. for about 1 hour. Shrinkage can be measured in the horizontal and / or vertical direction.

[0022] Figure 2 A memory device having a stepped structure 200 is depicted before depositing a gap fill material (e.g., a silicon-containing material) according to some embodiments described herein. In some embodiments, a substrate 225 includes a multilayer stack 201 including a plurality of conductive layers 220 and a plurality of intervening dielectric material layers disposed between the plurality of conductive layers. In some embodiments, the multilayer stack 201 includes about 100 layers or more, such as about 150 layers or more, such as for a 3D NAND structure. A large area, high aspect ratio opening 203 is disposed above and adjacent to a portion of the multilayer stack 201.

[0023] In some embodiments, conductive layer 220 disposed in dielectric material 210 of multilayer stack 201 may be composed of tungsten, platinum, titanium, ruthenium, silicon, molybdenum, cobalt, and hafnium. Each of memory openings 215 may be filled using any method known in the industry, such as PECVD or ALD.

[0024] Figure 3 A first view (eg, in an XY plane) of a memory device 300 having a staircase structure after a gap fill material 315 is deposited into the high aspect ratio openings according to some embodiments described herein.

[0025] Figure 4 A second view (e.g., in the YZ plane) of the memory device 300 is depicted after gap fill material 315 is deposited into the high aspect ratio opening 203. As used herein, the term "high aspect ratio opening" refers to an opening having a maximum depth 404 to minimum width 402 ratio of about 2:1 or greater (such as about 10:1 or greater, such as about 20:1 or greater, such as about 30:1 to about 1000:1, such as about 200:1 to about 500:1). In some embodiments, the high aspect ratio opening has a width of about 1 μm to about 2 μm and a depth of about 10 μm to about 12 μm.

[0026] In some embodiments, the gap filling material 315 includes one or more of silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC). The gap filling material 315 is substantially free of voids and seams. The silicon-containing gap filling material 315 may have good compression properties, high conformality, and low shrinkage. The stress may be about 200 MPa to about 350 MPa, such as about 225 MPa to about 325 MPa.

[0027] In some embodiments, the silicon-containing gap fill process 100 described herein achieves deposition of the silicon-containing gap filler 315 to a thickness of about 800 nm using about 3000 cycles to about 4000 cycles. As used herein, growth per cycle refers to the thickness deposited per cycle of operation 102 (optionally 104, 106, and optionally 108). In some embodiments, growth per cycle for a first duration is greater than growth per cycle for a second duration after the first duration. In some embodiments, precursor rates, gas ratios, or a combination of the above can be adjusted to adjust growth per cycle.

[0028] Figure 5 A memory device 500 having a staircase structure, a gap fill material 315, and a memory opening 215 according to some embodiments described herein is depicted. The mask layer 205 includes a pre-etched pattern formed based on a predetermined specification by using lithography and a mask etching process. The patterned mask layer 205 guides the formation of a feature structure (such as a memory opening 215 passing through the gap fill material 315). The multilayer stack 201 includes a plurality of conductive layers 220, and the conductive layers 220 form a staggered arrangement so that each of the memory openings 215 reaches a different depth ( Figure 4 Each of the memory openings 215 is formed using a plasma etching process according to a pattern formed in the mask layer 205, and has a different depth and contacts a different conductive layer 220. Each of the memory openings 215 formed during the plasma etching process also does not extend through the corresponding conductive layer 220. In some embodiments, the memory openings 215 are formed using a fluorocarbon radical plasma etching process. Although not depicted in the drawings, the memory openings 215 may be filled with a conductive material to form a connection, such as copper, tungsten, or a combination of the above. The connection is substantially free of cracks and defects.

[0029] In some embodiments, diaminosilane and / or aminosilane precursors are delivered to the high aspect ratio opening 203. The diaminosilane and / or aminosilane precursors may be co-reacted with an oxygen-containing gas such as ozone, peroxide, oxygen-containing plasma, or a combination thereof. In some embodiments, the precursor comprises a component having the formula R2-Si-Si-R2, wherein each R is independently a group comprising: a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, one or more R independently comprises an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor comprises monosilane, disilane, trisilane, butadienesilane, and a combination thereof. In some embodiments, one or more R independently comprises an isopropylamine group and a silane group, such as N-triisopropylsilane-1-amine having a structure depicted by Formula I.

[0030] Formula I

[0031] In some embodiments, one or more R groups independently include a diisopropylamine group, such as 1,2-bis(diisopropylamine)disilane (eg, BDIPADS).

[0032] Formula II

[0033] Without being bound by theory, it is believed that additional silicon atoms (such as two, three or four silicon atoms) in the precursor can achieve enhanced growth per cycle by increasing the reactivity of the precursor. Due to the additional molar concentration of silicon in the precursor molecule, a reduced amount of precursor is used to deposit the film.

[0034] In some embodiments, the precursor includes a compound having the formula (R3Si)3N, wherein each R is independently a group including a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, each R independently includes a propyl group, an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor includes tris(trialkylsilyl)amine, such as tris(trimethylsilyl)amine, trisilaneamine, or a combination thereof.

[0035] In some embodiments, the precursor includes a component having the formula SiR4, wherein each R is independently a group including: a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination thereof. In some embodiments, each R independently includes hydrogen, a propyl group, an isopropyl group, a butyl group, an amine group, or a combination thereof. In some embodiments, the precursor includes tetraethyl orthosilicate (TEOS) (e.g., tetraethyl silicate), monosilane, disilane, trisilane, butasilane, or a combination thereof.

[0036] In some embodiments, the precursor includes a component having the formula R2Si-NR2, such as silanamine, wherein each R is independently a group including: a carbon-containing group such as a branched or linear group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination of the above. In some embodiments, one or more R independently includes hydrogen, a propyl group, an isopropyl group, a butyl group, an amine group, or a combination of the above. In some embodiments, the precursor includes one or more of the following compounds: N-isopropyltrisilane-1-amine, N-isopropyl-N',N'-disilylsilane diamine, 1,1,-dimethoxy-N,N,N',N'-tetramethylsilane diamine, 1,1,-diethoxy-N,N,N',N'-tetramethylsilane diamine, N,N-dimethylsilane amine, N,N-diethyl ... -Dipropylsilaneamine, N,N-diisopropylsilaneamine, N,N-dibutylsilaneamine, N,N-di-tert-butylsilaneamine, tetramethylsilanediamine, N,N,N',N'-tetraethylsilanediamine, N,N,N',N'-tetraisopropylsilanediamine, N,N,N',N'-tetrapropylsilanediamine, N,N,N',N'-tetrabutylsilanediamine, N,N,N',N'-tetra-tert-butylsilanediamine.In some embodiments, the precursor includes N,N-di-sec-butylsilane amine, N,N'-dimethylsilane diamine, N,N'-diethylsilane diamine, N,N'-dibutylsilane diamine, N,N'-dipropylsilane diamine, N,N'-diisopropylsilane diamine, N,N'-di-tert-butylsilane diamine, N,N,N',N',N'',N''-hexaethylsilane triamine, N,N,N',N',N'',N''-hexaisopropylsilane triamine, N,N, N',N',N'',N''-hexapropylsilanetriamine, N,N,N',N',N'',N''-hexamethylsilanetriamine, N,N,N',N'',N''-hexabutylsilanetriamine, N,N,N',N'',N''-hexatertiarybutylsilanetriamine, N,N',N''-tripropylsilanetriamine, N,N',N''-tributylsilanetriamine, N,N',N''-triethylsilanetriamine, N,N',N''-triisobutylsilanetriamine Propylsilane triamine, N,N',N''-tri-tert-butylsilane triamine, N,N',N''-trimethylsilane triamine, N,N,N',N',N'',N'',N''',N'''-octamethylsilane tetraamine, N,N,N',N',N'',N'',N''',N'''-octaisopropylsilane tetraamine, N,N,N',N',N'',N'',N''',N'''-octa-tert-butylsilane tetraamine, N,N,N',N',N',N' '',N'',N''',N'''-octapropylsilanetetramine, N,N',N'',N'''-tetraethylsilanetetramine, N,N,N',N'',N'',N''',N'''-octabutylsilanetetramine, N,N',N'',N'''-tetra-tert-butylsilanetetramine, N,N,N',N'',N'',N''',N'''-octaethylsilanetetramine, N,N',N'',N''',N'''-tetramethylsilanetetramine, N,N',N'',N'''-tetraisopropylsilanetetraamine, N,N',N'',N'''-tetrapropylsilanetetraamine and N,N',N'',N'''-tetrabutylsilanetetraamine. In some embodiments, the precursor includes the compound N,N-di-sec-butylsilylamine having the structure depicted by Formula III.

[0037] Formula III

[0038] The methods and precursor chemicals described herein enable large area gap filling for 3D NAND devices. The deposited large area gap filling material includes a compressed silicon-containing film that is substantially free of voids and seams. The compressive properties of the film can be etched to form an opening, which is then filled with a conductive material to form a connection. The connection is formed within the silicon-containing film without cracking and is substantially defect-free. Compared to conventional methods, the method also reduces the amount of precursor required to fill the large area gap filling.

[0039] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, the scope of which is to be determined by the appended claims.

Claims

1. A method of forming a high aspect ratio structure within a 3D NAND structure, the method comprising: delivering a precursor selected from the group consisting of: diaminosilane, aminosilane, and combinations thereof to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers; as well as An oxygen-containing compound is delivered to the high aspect ratio opening, wherein the precursor and the oxygen-containing compound are cyclically alternated to fill the high aspect ratio opening.

2. The method of claim 1, wherein the multilayer stack comprises a plurality of conductive layers alternating with a plurality of dielectric layers.

3. The method of claim 1, wherein the precursor comprises a compound having the following structure: 。 4. The method of claim 1, wherein the precursor comprises a compound having the following structure: 。 5. The method of claim 1, wherein the precursor further comprises a component having the formula R2-Si-Si-R2, wherein each R is independently a group comprising: a carbon-containing group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, or a combination of the above.

6. The method of claim 1, wherein the precursor further comprises a component having the formula R2-Si-Si-R2, wherein one or more R independently comprises an isopropyl group, a butyl group, an amine group, or a combination thereof.

7. The method of claim 1, wherein the precursor further comprises monosilane, disilane, trisilane, tetrasilane, and combinations thereof.

8. The method of claim 1, wherein the high aspect ratio openings have a ratio of about 10:1 or greater.

9. The method of claim 1, wherein filling the high aspect ratio opening further comprises forming a silicon-containing material selected from the group consisting of silicon germanium (SiGe), silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and combinations thereof.

10. The method of claim 1, wherein the oxygen-containing compound is selected from the group consisting of: O3 (eg, ozone), H2O2 (eg, peroxide), oxygen plasma, and combinations thereof.

11. A method of forming a 3D NAND structure, the method comprising: delivering a precursor selected from the group consisting of: diaminosilane, aminosilane, and combinations thereof to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers; as well as delivering an oxygen-containing plasma to the high aspect ratio opening, wherein the precursor and the oxygen-containing plasma are cyclically alternating to fill the high aspect ratio opening with a silicon-containing material; and An opening is etched into the silicon-containing material.

12. The method of claim 11, wherein the oxygen-containing plasma is pulsed for about 2 seconds to about 10 seconds.

13. The method of claim 11, wherein a time pulse ratio of the precursor to the oxygen-containing plasma is about 1:20 to about 1:

5.

14. The method of claim 11, wherein the oxygen-containing plasma is provided from a remote plasma source coupled to a power source to excite a gas delivered to the remote plasma source at a power of about 100 W to about 300 W and a frequency of about 13 MHz to about 60 MHz.

15. The method of claim 11, wherein etching the opening in the silicon-containing material comprises a fluorocarbon radical plasma etch process.

16. A method of forming a 3D NAND structure on a substrate, the method comprising: delivering a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers, the precursor comprising diaminosilane; as well as An oxygen-containing plasma is delivered to the high aspect ratio opening, wherein the precursor and the oxygen-containing plasma are cyclically alternating to fill the high aspect ratio opening with a silicon-containing material, the high aspect ratio opening having an aspect ratio of about 10:1 or greater.

17. The method of claim 16, further comprising maintaining a substrate temperature of about 100°C to about 450°C.

18. The method of claim 16, wherein delivering the precursor and the oxygen-containing plasma is an atomic layer deposition process having a growth per cycle of about 1.5 Å per cycle to about 3 Å per cycle.

19. The method of claim 16, wherein the precursor comprises a component having the formula R2Si-NR2, wherein each R is independently selected from the group consisting of: a carbon-containing group such as a branched or linear group, a hydrogen-containing group, an oxygen-containing group, a nitrogen-containing group, a silicon-containing group, and combinations thereof.

20. A memory device, comprising: a multilayer stack comprising a plurality of conductive layers alternating with a plurality of dielectric layers; A gap-fill material disposed over and at least partially adjacent to the multilayer stack, the gap-fill material having one or more of the following: Stress of about 200 MPa to about 350 MPa; about 98% to about 99% conformality; Shrinkage properties of about 0.01% to about 10%; and A plurality of conductive connections are disposed within the gap-fill material.

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