Multilayer ceramic capacitor

Abstract

Provided is a laminated ceramic capacitor which is capable of suppressing the occurrence of cracks in the laminated ceramic capacitor and which has excellent reliability. A laminated ceramic capacitor (1) is provided with: a laminated body (2) including dielectric layers (14) and internal electrode layers (15) that are alternately laminated, the substrate has two main surfaces (A) that face each other in a stacking direction (T), two end surfaces (C) that face each other in a longitudinal direction (L) that is orthogonal to the stacking direction (T), and two side surfaces (B) that face each other in a width direction (W) that is orthogonal to both the stacking direction (T) and the longitudinal direction (L). And external electrodes (3) disposed on both end surfaces (C) of the laminate (2), respectively. The external electrode (3) has: a base electrode layer (31); a first plating layer (32) disposed on the base electrode layer (31); a second plating layer (33) disposed on the first plating layer (32) and in contact with the first plating layer; and a bonding force relieving layer (35) disposed between the first plating layer (32) and the second plating layer (33).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] When a flexural stress such as bending is applied to a circuit board in a state where a multilayer ceramic capacitor is mounted, the stress is transmitted to the capacitor body through the external electrodes, and cracks may be generated in the capacitor body.

[0003] In order to suppress such cracks, for example, in Patent Document 1, a close contact relief film is arranged between the sintered metal film and the plated metal film in the external electrode. The close contact relief film is used to relieve the close contact force of the plated metal film on the surface formed by the plated metal film. Thus, when the circuit substrate is deflected, the plated metal film can be peeled off from the sintered metal, thereby suppressing the transmission of stress to the capacitor body.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-203910 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] However, when the plated metal film is peeled off from the baked metal film, the baked metal film is exposed to the outside air, and thus there is a concern about deterioration of the capacitor body and the like due to moisture or the like that penetrates into the baked metal film.

[0009] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the multilayer ceramic capacitor and has excellent reliability.

[0010] Technical solutions to solve problems

[0011] In order to solve the above-mentioned problems, the present invention provides a stacked ceramic capacitor, comprising: a stacked body, comprising alternately stacked dielectric layers and internal electrode layers, and having two main surfaces opposite to each other in a stacking direction, two end surfaces opposite to each other in a length direction orthogonal to the stacking direction, and two side surfaces opposite to each other in a width direction orthogonal to either the stacking direction and the length direction; and external electrodes, respectively arranged on the two end surfaces of the stacked body, wherein the external electrodes have: a base electrode layer; a first plating layer, arranged on the base electrode layer; a second plating layer, arranged on the first plating layer and in contact with the first plating layer; and a close contact relief layer, arranged between the first plating layer and the second plating layer.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the multilayer ceramic capacitor and has excellent reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic perspective view of a state where a multilayer ceramic capacitor according to an embodiment of the present invention is mounted on a circuit board.

[0015] Figure 2 The multilayer ceramic capacitor according to one embodiment of the present invention is mounted on a circuit board. Figure 1 Partially enlarged views of the cross section along the II-II line in FIG. 1 , (a) is a view showing the periphery of the first external electrode in a state where the first plating layer and the second plating layer are bonded together, and (b) is a view showing the periphery of the second external electrode in a state where the first plating layer and the second plating layer are peeled off.

[0016] Figure 3 FIG. 1 is a diagram showing the structure of a multilayer ceramic capacitor according to a modified example of the present invention. Figure 2 The corresponding figure of (a).

[0017] Figure 4 FIG. 1 is a diagram showing the structure of a multilayer ceramic capacitor according to a modified example of the present invention. Figure 2 The corresponding figure of (a). DETAILED DESCRIPTION

[0018] The following is based on Figure 1 as well as Figure 2 Embodiments of the present invention will be described.

[0019] (Multilayer ceramic capacitor 1)

[0020] like Figure 1 as well as Figure 2 As shown, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer ceramic capacitor 1 is mounted on a circuit board 50.

[0021] In the following description, as terms indicating directions of the multilayer ceramic capacitor 1, in the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is referred to as the length direction L. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is referred to as the stacking direction T. The direction intersecting either the length direction L or the stacking direction T is referred to as the width direction W. In the embodiment, the width direction W is orthogonal to either the length direction L or the stacking direction T.

[0022] In addition, in the following description, Figure 1Among the six outer peripheral surfaces of the stacked body 2 shown, a pair of outer surfaces opposite to each other in the stacking direction T are set as two main surfaces A, a pair of outer surfaces opposite to each other in the width direction W are set as two side surfaces B, and a pair of outer surfaces opposite to each other in the length direction L are set as two end surfaces C. One of the two main surfaces A is set as the first main surface AA, and the other is set as the second main surface AB (refer to Figure 2 ). One of the two end faces C is set as the first end face CA, and the other is set as the second end face CB. When there is no need to distinguish the first main face AA and the second main face AB, they are collectively described as the main face A. When there is no need to distinguish the first end face CA and the second end face CB, they are collectively described as the end face C. In addition, the circuit substrate 50 is arranged on the second main face AB side of the multilayer ceramic capacitor 1.

[0023] (Laminate 2)

[0024] The laminated body 2 includes a laminated body main body portion 10 and a side margin portion 20 .

[0025] (Laminate body main body 10)

[0026] The laminate body 10 includes an inner layer portion 11 and an outer layer portion 12 disposed on both principal surfaces A sides of the inner layer portion 11 .

[0027] (Inner layer portion 11)

[0028] The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 .

[0029] (Dielectric layer 14)

[0030] The dielectric layer 14 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic having BaTiO3 as a main component can be used. In addition, as the ceramic material, a material in which at least one of the auxiliary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds is added to these main components can also be used.

[0031] (Internal electrode layer 15)

[0032] The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are alternately arranged. In addition, when it is not necessary to distinguish them in particular, the first internal electrode layers 15A and the second internal electrode layers 15B are collectively described as the internal electrode layer 15.

[0033] The internal electrode layer 15 is preferably formed of a metal material represented by Ni, Cu, Ag, Pd, Ag—Pd alloy, Au, or the like.

[0034] The first internal electrode layer 15A includes a first opposing portion 152a opposing the second internal electrode layer 15B and a first lead portion 151a led out from the first opposing portion 152a toward the first end surface CA. The end of the first lead portion 151a is exposed at the first end surface CA and is electrically connected to a first external electrode 3A described later.

[0035] The second internal electrode layer 15B includes a second opposing portion 152b opposing the first internal electrode layer 15A and a second lead portion 151b led from the second opposing portion 152b to the second end surface CB. The end of the second lead portion 151b is electrically connected to a second external electrode 3B described later.

[0036] According to the internal electrode layer 15 described above, electric charges are accumulated in the first opposing portion 152a of the first internal electrode layer 15A and the second opposing portion 152b of the second internal electrode layer 15B, and capacitor characteristics are exhibited.

[0037] (Outer layer 12)

[0038] The outer layer portion 12 is made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11 .

[0039] (Side margin 20)

[0040] Side margins 20 are provided on both side surfaces B of the portion where the inner layer portion 11 and the outer layer portion 12 are stacked. The side margins 20 cover the ends of the internal electrode layers 15 exposed on both side surfaces of the laminate body 10 in the width direction W. The side margins 20 are made of the same dielectric ceramic material as the dielectric layer 14.

[0041] (External electrode 3)

[0042] The external electrode 3 includes a first external electrode 3A provided on the first end surface CA of the stacked body 2 and a second external electrode 3B provided on the second end surface CB of the stacked body 2. In addition, when it is not necessary to distinguish them in particular, the first external electrode 3A and the second external electrode 3B are collectively described as the external electrode 3. The external electrode 3 covers not only the end surface C but also a part of the main surface A and the side surface B on the end surface C side.

[0043] The external electrode 3 includes a base electrode layer 31 , a first plating layer 32 disposed on the base electrode layer 31 , a second plating layer 33 disposed on the first plating layer 32 , and an adhesion relaxation layer 35 disposed between the first plating layer 32 and the second plating layer 33 .

[0044] The base electrode layer 31 is formed by, for example, applying a conductive paste containing a conductive metal and glass and then baking it. As the conductive metal of the base electrode layer 31, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. can be used.

[0045] The first plating layer 32 is a Cu plating layer. This can appropriately suppress the infiltration of moisture into the base electrode layer 31 .

[0046] The second plating layer 33 includes an inner second plating layer 331 and an outer second plating layer 332 . The outer second plating layer 332 is disposed on the inner second plating layer 331 and is in contact with the inner second plating layer 331 .

[0047] The inner second plating layer 331 is a Ni plating layer. Thus, when the multilayer ceramic capacitor 1 is mounted on the circuit board 50, it is possible to suppress corrosion of the base electrode layer 31 and the adhesion relief layer 35 by the solder.

[0048] The outer second plating layer 332 is a Sn plating layer. Thus, when the multilayer ceramic capacitor 1 is mounted on the circuit board 50, the wettability of the solder is improved, so that the multilayer ceramic capacitor 1 can be easily mounted.

[0049] The adhesion relief layer 35 can relieve the adhesion between the first plating layer 32 and the second plating layer 33 (specifically, the inner second plating layer 331). Thus, when the circuit substrate 50 is bent, the first plating layer 32 can be properly peeled off from the second plating layer 33 in the area where the adhesion relief layer 35 is arranged. The adhesion relief layer 35 contains an organic silicon compound. The organic silicon compound is preferably a multifunctional alkoxysilane Si-(C n H 2n＋1 )3. Thus, the adhesion relief layer can be more reliably arranged on the surface of the first plating layer 32, and the generation of cracks in the laminate 2 can be appropriately suppressed. In addition, plating defects and the falling off of the laminated ceramic capacitor 1 can be suppressed.

[0050] In detail, the close contact relief layer 35 is configured in the region between the first plating layer 32 and the second plating layer 33, where the first plating layer 32 and the second plating layer 33 cover the region of the main surface A. Although not shown, the close contact relief layer 35 is annular, and is also configured in the region between the first plating layer 32 and the second plating layer 33, where the first plating layer 32 and the second plating layer 33 cover the region of the side B. In addition, the close contact relief layer 35 is only required to be configured at least in the region where the first plating layer 32 and the second plating layer 33 cover the second main surface AB, and in the region where the first plating layer 32 and the second plating layer 33 cover the first main surface AA, and in the region where the first plating layer 32 and the second plating layer 33 cover the side B, the close contact relief layer 35 is not necessarily required to be configured.

[0051] The close contact force relief layer 35 has a plurality of gaps that penetrate in the thickness direction of the layer. The close contact force relief layer 35 can also be said to be a layer constituting a porous structure. The first plating layer 32 and the second plating layer 33 become a state of contact with each other in the part of the gap. Therefore, the first plating layer 32 and the second plating layer 33 become able to be energized by the contact portion.

[0052] In addition, the first plating layer 32 preferably has a surface roughness of at least 0.10 μm to 0.27 μm on the side facing the adhesion relief layer 35. This allows the first plating layer 32 and the second plating layer 33 to have an appropriate peeling property when peeling.

[0053] Here, if Figure 2 As shown in (b), if the circuit substrate 50 is bent, the first plating layer 32 and the second plating layer 33 can be in a peeled state (hereinafter, sometimes simply referred to as a "peeled state") in the area where the adhesion relief layer 35 is arranged. Even in the peeled state, the base electrode layer 31 is covered by the first plating layer 32. As a result, it is possible to suppress the infiltration of moisture into the base electrode layer 31 and the like, and thus it is possible to suppress the degradation of the multilayer ceramic capacitor 1.

[0054] In addition, in the peeled state, for example, the following situation can be imagined, that is, the adhesion relief layer 35 becomes a torn state, and each fragment of the adhesion relief layer 35 is respectively attached to the first plating layer 32 and the second plating layer 33. However, the state of the adhesion relief layer 35 in the peeled state is not particularly limited, and the following situation can also be imagined, that is, the entire adhesion relief layer 35 is attached to either the first plating layer 32 or the second plating layer 33.

[0055] (Method for manufacturing multilayer ceramic capacitor)

[0056] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 1. The manufacturing process of the multilayer ceramic capacitor 1 includes a multilayer body manufacturing process and an external electrode forming process.

[0057] (Laminate manufacturing process)

[0058] First, a ceramic green sheet for lamination is prepared by molding a ceramic slurry into a sheet shape. A conductive paste is placed on the ceramic green sheet for lamination, and a pattern of each internal electrode layer 15 is printed. In this way, a raw material sheet can be obtained.

[0059] Next, a plurality of raw material sheets are stacked so that the internal electrode patterns are staggered by half a pitch in the length direction between adjacent raw material sheets. Furthermore, ceramic green sheets for outer layer portions, which are to be outer layer portions, are stacked so that the stacked raw material sheets are sandwiched and thermally pressed. Thus, a mother block component can be obtained.

[0060] Next, the mother block member is divided along the cutting line corresponding to the size of the stacked body. Thus, a plurality of stacked chips are obtained. Then, the plurality of stacked chips may be rounded at the corners and ridges by roller grinding or the like.

[0061] Next, the plurality of laminated small pieces are fired to obtain a laminate 2 having a laminate body 10 and side margins 20. The firing temperature at this time depends on the materials of the dielectric layer 14 and the internal electrode layer 15, but is preferably 900°C or higher and 1400°C or lower.

[0062] (External electrode forming process)

[0063] First, the base electrode layer 31 is formed on the end surface C of the stack 2. The end surface C of the stack 2 is sequentially immersed in a conductive paste as an electrode material for the base electrode. Thus, the conductive paste is applied to the end surfaces C of the stack 2. Then, these conductive pastes are fired together with the stack 2. Thus, the base electrode layer 31 is formed on the end surfaces C of the stack 2. The firing temperature is preferably 600° C. or more and 900° C. or less. In addition, the firing of the stack 2 and the firing of the external electrode 3 may be performed simultaneously.

[0064] Next, the first plating layer 32 is formed on the base electrode layer 31. The first plating layer 32 is formed so that the end portions on the principal surface A and the side surface B of the first plating layer 32 cover the end portions on the principal surface A and the side surface B of the base electrode layer 31. The first plating layer 32 can be formed, for example, by electrolytic plating or electroless plating.

[0065] Next, a close contact relief layer 35 is arranged on the first plating layer 32. In the formation of the close contact relief layer 35, a first organic treatment liquid and a second organic treatment liquid are used. First, the first organic treatment liquid is applied to the first plating layer 32. The first organic treatment liquid contains an organosilicon compound. The organosilicon compound is a silane coupling agent. The organosilicon compound (silane coupling agent) is, for example, decyltrimethoxysilane, n-propyltrimethoxysilane, octyltriethoxysilane, etc. The first organic treatment liquid can be applied, for example, by screen printing. Then, the first organic treatment liquid is dried at a temperature of 100°C to 200°C.

[0066] Then, after the first organic treatment liquid is dried, a second organic treatment liquid is applied. The second organic treatment liquid contains an organic silicon compound, preferably a multifunctional alkoxysilane Si-(C n H 2n＋1 )3. The second organic treatment liquid can be applied, for example, by screen printing. Then, the second organic treatment liquid is dried at a temperature of 100°C to 200°C. The dried first organic treatment liquid and the second organic treatment liquid are arranged on the first plating layer 32 as a close contact relief layer 35. In addition, the method of applying the first organic treatment liquid and the second organic treatment liquid is not limited to the screen printing method. For example, an immersion method of immersing the object in the organic treatment liquid can also be used. In addition, the close contact relief layer arranged in an area where the close contact relief layer is not desired to be arranged can be removed by grinding or the like. In addition, the number and size of the gaps in the close contact relief layer 35 can be adjusted by the application amount of the first organic treatment liquid and the second organic treatment liquid. When the application amount of the first organic treatment liquid and the second organic treatment liquid is large, the number of gaps decreases and the size of the gaps decreases. When the application amount of the first organic treatment liquid and the second organic treatment liquid is small, the number of gaps increases and the size of the gaps increases.

[0067] Next, the inner second plating layer 331 is formed on the first plating layer 32 and the adhesion relief layer 35. The inner second plating layer 331 is formed so that the end portions on the main surface A and the side B side of the inner second plating layer 331 cover the end portions on the main surface A and the side B side of the first plating layer 32 and the adhesion relief layer 35. The inner second plating layer 331 can be formed, for example, by electrolytic plating.

[0068] Next, the outer second plating layer 332 is formed on the inner second plating layer 331. The outer second plating layer 332 is formed so that the end of the main surface A and the side B side of the outer second plating layer 332 covers the end of the main surface A and the side B side of the adhesion relief layer 35. The outer second plating layer 332 can be formed, for example, by an electrolytic plating method. By the above, the external electrode 3 is formed.

[0069] (Effect)

[0070] According to the above-described embodiment, the following effects can be obtained.

[0071] According to the above embodiment, the external electrode 3 includes a base electrode layer 31, a first plating layer 32 disposed on the base electrode layer 31, a second plating layer 33 disposed on and in contact with the first plating layer 32, and a close contact relief layer 35 disposed between the first plating layer 32 and the second plating layer 33. The close contact relief layer 35 can relieve the close contact between the first plating layer 32 and the second plating layer 33. Thus, when the multilayer ceramic capacitor 1 is mounted on the circuit substrate 50 and the circuit substrate 50 is bent, the first plating layer 32 and the second plating layer 33 can be peeled off by the stress. Therefore, the generation of cracks in the multilayer ceramic capacitor 1 can be suppressed.

[0072] Furthermore, even when the first plating layer 32 and the second plating layer 33 are peeled off, the base electrode layer 31 is covered by the first plating layer 32. Thus, it is possible to suppress the intrusion of moisture into the base electrode layer 31 and the like, thereby suppressing the degradation of the multilayer ceramic capacitor 1. Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0073] According to the above embodiment, the first plating layer 32 is a Cu plating layer. This can appropriately suppress the infiltration of moisture into the base electrode layer 31 .

[0074] Furthermore, according to the above embodiment, the inner second plating layer 331 is a Ni plating layer. Thus, when the multilayer ceramic capacitor 1 is mounted on the circuit board 50, it is possible to suppress corrosion of the base electrode layer 31 and the adhesion relief layer 35 by solder.

[0075] Furthermore, according to the above embodiment, the outer second plating layer 332 is a Sn plating layer. This improves the wettability of solder when the multilayer ceramic capacitor 1 is mounted on the circuit board 50, so that the multilayer ceramic capacitor 1 can be easily mounted.

[0076] According to the above embodiment, the adhesion relaxation layer 35 contains an organic silicon compound. This can appropriately suppress the occurrence of cracks in the laminated body 2. In addition, plating defects and the peeling of the laminated ceramic capacitor 1 can be suppressed.

[0077] According to the above embodiment, the organosilicon compound is a polyfunctional alkoxysilane. This can more appropriately suppress the occurrence of cracks in the laminate 2, and can suppress plating defects and the fall-off of the laminated ceramic capacitor 1.

[0078] According to the above embodiment, the surface roughness Sa of the first plating layer 32 is 0.10 μm or more and 0.27 μm or less.

[0079] Thereby, the peeling ease of the first plating layer 32 and the second plating layer 33 when peeling off can be set to appropriate peeling ease.

[0080] According to the above embodiment, the adhesion relief layer 35 is disposed in the region between the first plating layer 32 and the second plating layer 33, in the region outside the main surface A and the region outside the side surface B, and is not disposed in the region outside the end surface C. Thus, the adhesion between the first plating layer 32 and the second plating layer 33 can be set to an appropriate strength, so that the falling off of the multilayer ceramic capacitor 1 can be appropriately suppressed.

[0081] (Deformation method)

[0082] As mentioned above, although the preferred embodiment and the modification of this invention were described, it is not limited to these, and this invention includes the following scope.

[0083] In the above embodiment, the adhesion relief layer 35 is disposed in the region between the first plating layer 32 and the second plating layer 33, in the region outside the main surface A of the laminate 2 and in the region outside the side surface B, and is not disposed in the region outside the end surface C, but is not limited thereto. Figure 3 As shown, the stacked ceramic capacitor 100 is provided with a close contact relief layer 135. The close contact relief layer 135 is configured to span and cover the entire area of ​​the area between the first plating layer 32 and the second plating layer 33. In this case, for example, it is possible to easily configure the close contact relief layer by using an immersion method. However, from the aspect of being able to appropriately suppress the second plating layer from detaching from the stacked ceramic capacitor, the structure of the above embodiment is preferred.

[0084] In addition, the adhesion relief layer may also extend to the outside of the region between the first plating layer 32 and the second plating layer 33. For example, Figure 4 As shown, the stacked ceramic capacitor 200 is provided with a close contact relief layer 235. The close contact relief layer 235 is configured to span and cover the entire area of ​​the outer surface of the first plating layer 32, and span and cover the entire area of ​​each outer surface of the main surface A and side B of the stacked body 2. In this case, for example, it is possible to more easily configure the close contact relief layer by using an immersion method. However, from the aspect of being able to appropriately suppress the second plating layer from detaching from the stacked ceramic capacitor, the structure of the preferred embodiment is preferred.

[0085] In the above embodiment, the adhesion relief layer 35 includes an organic silicon compound, but the present invention is not limited thereto. The adhesion relief layer may be, for example, a metal. However, from the perspective of being able to more appropriately suppress the occurrence of cracks in the multilayer ceramic capacitor, the structure of the above embodiment is preferred.

[0086] In the above embodiment, the first plating layer 32 has a single-layer structure, but may have multiple layers. When the first plating layer has multiple layers, the surface roughness Sa of the outer surface of the outermost layer is preferably set to 0.10 μm or more and 0.27 μm or less.

[0087] In the above embodiment, the second plating layer 33 includes the inner second plating layer 331 and the outer second plating layer 332 , but may be a single-layer structure or may include three or more layers.

[0088] As mentioned above, although the preferred embodiment and the modification of this invention were described, it is not limited to these, and this invention includes the following scope.

[0089] <1>

[0090] A multilayer ceramic capacitor comprising:

[0091] A laminate comprising dielectric layers and internal electrode layers alternately laminated, and having two main surfaces opposed to each other in the lamination direction, two end surfaces opposed to each other in the length direction orthogonal to the lamination direction, and two side surfaces opposed to each other in the width direction orthogonal to either the lamination direction or the length direction; and

[0092] External electrodes are respectively arranged on the two end surfaces of the stacked body,

[0093] in,

[0094] The external electrode has:

[0095] Base electrode layer;

[0096] A first plating layer is disposed on the base electrode layer;

[0097] a second plating layer disposed on the first plating layer and in contact with the first plating layer; and

[0098] The adhesion relaxation layer is arranged between the first plating layer and the second plating layer.

[0099] <2>

[0100] The multilayer ceramic capacitor according to <1>,

[0101] The second plating layer includes an inner second plating layer and an outer second plating layer disposed on the inner second plating layer.

[0102] <3>

[0103] The multilayer ceramic capacitor according to <2>,

[0104] The first plating layer is a Cu plating layer, the inner second plating layer is a Ni plating layer, and the outer second plating layer is a Sn plating layer.

[0105] <4>

[0106] The multilayer ceramic capacitor according to any one of <1> to <3>,

[0107] The adhesion relief layer comprises an organic silicon compound.

[0108] <5>

[0109] The multilayer ceramic capacitor according to <4>,

[0110] The organic silicon compound is a multifunctional alkoxysilane.

[0111] <6>

[0112] The multilayer ceramic capacitor according to any one of <1> to <5>,

[0113] The surface roughness Sa of the first plating layer is greater than or equal to 0.10 μm and less than or equal to 0.27 μm.

[0114] <7>

[0115] The multilayer ceramic capacitor according to any one of <1> to <6>,

[0116] The adhesion relief layer is arranged in a region between the first plating layer and the second plating layer, in a region outside the main surface and in a region outside the side surface, and is not arranged in a region outside the end surface.

[0117] Description of Reference Numerals

[0118] 1, 100, 200: multilayer ceramic capacitors;

[0119] 2: laminate;

[0120] 3: External electrode;

[0121] 3A: 1st external electrode;

[0122] 3B: 2nd external electrode;

[0123] 14: dielectric layer;

[0124] 15: internal electrode layer;

[0125] 31: base electrode layer;

[0126] 32: 1st plating layer (Cu plating layer);

[0127] 33: second plating layer;

[0128] 35, 135, 235: close contact relief layer;

[0129] 331: inner second plating layer (Ni plating layer);

[0130] 332: outer second plating layer (Sn plating layer);

[0131] A: Main side;

[0132] AA: 1st main side;

[0133] AB: 2nd main side;

[0134] B: side view;

[0135] C: end face;

[0136] CA: 1st end face;

[0137] CB: 2nd end face.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising dielectric layers and internal electrode layers alternately laminated, and having two main surfaces facing each other in a lamination direction, two end surfaces facing each other in a length direction orthogonal to the lamination direction, and two side surfaces facing each other in a width direction orthogonal to either the lamination direction or the length direction; and External electrodes are respectively arranged on the two end surfaces of the stacked body, in, The external electrode has: Base electrode layer; A first plating layer is disposed on the base electrode layer; a second plating layer disposed on the first plating layer and in contact with the first plating layer; as well as The adhesion relaxation layer is arranged between the first plating layer and the second plating layer.

2. The multilayer ceramic capacitor according to claim 1, wherein The second plating layer includes an inner second plating layer and an outer second plating layer disposed on the inner second plating layer.

3. The multilayer ceramic capacitor according to claim 2, wherein: The first plating layer is a Cu plating layer, The inner second plating layer is a Ni plating layer, The outer second plating layer is a Sn plating layer.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The adhesion relief layer comprises an organic silicon compound.

5. The multilayer ceramic capacitor according to claim 4, wherein: The organic silicon compound is a multifunctional alkoxysilane.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein The surface roughness Sa of the first plating layer is greater than or equal to 0.10 μm and less than or equal to 0.27 μm.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein The adhesion relief layer is arranged in a region between the first plating layer and the second plating layer, in a region outside the main surface and in a region outside the side surface, and is not arranged in a region outside the end surface.

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