Substrate for forming semiconductor device, semiconductor laminated structure, semiconductor device, method for manufacturing substrate for forming semiconductor device, method for manufacturing semiconductor laminated structure, and method for manufacturing semiconductor device

Abstract

The present invention relates to a substrate (1) for forming a semiconductor device, the substrate (1) having a diamond substrate (10) and a silicon carbide layer (20) positioned on a part or all of one surface (10a) of the diamond substrate (10), the thickness of the silicon carbide layer (20) being 20 nm or less, and the arithmetic average roughness (Ra) of the surface (20a) of the silicon carbide layer (20) being 0.5 nm or less.

Description

Technical Field

[0001] The present invention relates to a substrate for forming a semiconductor device, a semiconductor stacked structure, a semiconductor device, a method for manufacturing a substrate for forming a semiconductor device, a method for manufacturing a semiconductor stacked structure, and a method for manufacturing a semiconductor device.

[0002] This application claims the priority of Japanese Patent Application No. 2022-144364 filed in Japan on September 12, 2022, the entire contents of which are incorporated herein by reference. Background Art

[0003] In recent years, with the high output, high speed and high integration of semiconductor devices (semiconductor devices), a substrate with high thermal conductivity is required for forming semiconductor devices. As such a substrate for forming semiconductor devices, diamond substrates with high thermal conductivity of more than 500W / mK are attracting attention. Generally, the surface of the diamond substrate is rough, and there is a problem that it is difficult to bond with the semiconductor layer.

[0004] To address these problems, for example, Non-Patent Document 1 proposes a semiconductor stacked structure in which thin films of silicon are deposited on the surfaces of a diamond substrate and gallium nitride, respectively, and the silicon elements are bonded to each other, thereby bonding the diamond substrate and gallium nitride together.

[0005] For example, Non-Patent Document 2 proposes a semiconductor stacked structure in which a gallium nitride element is fabricated on a silicon carbide substrate, the silicon carbide substrate is polished to a thickness of 50 μm, and the silicon carbide substrate and a diamond substrate are bonded together via a titanium thin film.

[0006] For example, Patent Document 1 proposes a semiconductor device in which a silicon carbide substrate implanted with hydrogen ions is bonded to a diamond substrate, the silicon carbide substrate is smart-cut by heat treatment, and a gallium nitride crystal is grown on the thinned silicon carbide substrate.

[0007] Prior art literature

[0008] Non-patent literature

[0009] Non-patent literature 1: Z.Cheng, et al., "Interfacial Thermal Conductance across Room-Temperature Bonded GaN-Diamond Interfaces for GaN-on-Diamond Devices," ACS Appl.Mater.Interfaces 12, pp.8376-8384 (2020).

[0010] Non-patent document 2: Yuichi Minoura, et al., "Surface activated bonding ofSiC / diamond for thermal management of high-output power GaN HEMTs," Jpn.J.Appl.Phys.59, SGGD03(2020).

[0011] Patent Literature

[0012] Patent Document 1: (Japanese) Patent Publication No. 2016-139655 Summary of the invention

[0013] Technical problem to be solved by the invention

[0014] However, in the case of the semiconductor stacked structure of non-patent document 1, if heat treatment is performed at a high temperature of 800°C or higher, a reaction called melt back occurs at the interface between gallium nitride and silicon elements, forming voids, which leads to a problem of reduced reliability when forming a semiconductor element (semiconductor device).

[0015] In the semiconductor stacked structure of Non-Patent Document 2, the silicon carbide substrate and the diamond substrate are bonded via a thin film of titanium. However, the thermal conductivity of titanium is lower than that of silicon carbide, so there is a problem that heat dissipation is poor.

[0016] It is unclear whether a gallium nitride crystal can be grown on a silicon carbide substrate after smart lift-off in the semiconductor device of Patent Document 1. Furthermore, the silicon carbide substrate is relatively thick, which causes a problem of poor heat dissipation.

[0017] Therefore, an object of the present invention is to provide a substrate for forming a semiconductor device, a semiconductor stacked structure, a semiconductor device and a method for manufacturing the same, which can easily bond a diamond substrate and a semiconductor layer and have excellent heat dissipation and heat resistance.

[0018] Technical solutions for solving technical problems

[0019] The present invention has the following aspects.

[0020] [1] A substrate for forming a semiconductor device, comprising: a diamond substrate and a silicon carbide layer located on a part or the whole of one surface of the diamond substrate,

[0021] The thickness of the silicon carbide layer is less than 20 nm,

[0022] The silicon carbide layer has a surface with an arithmetic mean roughness Ra of 0.5 nm or less.

[0023] [2] The substrate for forming a semiconductor device according to [1], wherein a part or all of silicon carbide contained in the silicon carbide layer is amorphous.

[0024] [3] A semiconductor stacked structure comprising:

[0025] Diamond substrate;

[0026] A semiconductor layer located on a part or the whole of a surface of the diamond substrate;

[0027] a silicon carbide layer located between the diamond substrate and the semiconductor layer,

[0028] The semiconductor layer includes nitride or oxide,

[0029] The silicon carbide layer is a single layer,

[0030] The thickness of the silicon carbide layer is less than 20 nm.

[0031] [4] The semiconductor stacked structure according to [3], wherein an arithmetic mean roughness Ra of the surface of the silicon carbide layer at the interface between the silicon carbide layer and the semiconductor layer is 0.5 nm or less.

[0032] [5] The semiconductor stacked structure according to [3] or [4], wherein part or all of the silicon carbide contained in the silicon carbide layer is amorphous.

[0033] [6] A semiconductor device comprising the semiconductor stacked structure according to any one of [3] to [5], wherein part or all of the silicon carbide contained in the silicon carbide layer is polycrystalline.

[0034] [7] A method for manufacturing a substrate for forming a semiconductor device, comprising: a deposition step of depositing silicon carbide on a portion or all of a surface of a diamond substrate to form a silicon carbide layer having a thickness of less than 20 nm and an arithmetic mean roughness Ra of less than 0.5 nm.

[0035] [8] A method for manufacturing a semiconductor stacked structure, comprising:

[0036] A step of manufacturing a substrate for forming a semiconductor device, wherein the substrate for forming a semiconductor device is manufactured by the method for manufacturing a substrate for forming a semiconductor device according to [7]; and

[0037] In the bonding step, the surface of the silicon carbide layer is then bonded to a semiconductor layer including a nitride or an oxide.

[0038] [9] A method for manufacturing a semiconductor device, comprising:

[0039] a step of manufacturing a semiconductor stacked structure, comprising manufacturing the semiconductor stacked structure by the method for manufacturing a semiconductor stacked structure according to [8]; and

[0040] The heat treatment step is to perform a heat treatment at 800° C. or higher on the semiconductor stacked structure.

[0041] Effects of the Invention

[0042] According to the substrate for forming a semiconductor device, the semiconductor stacked structure, the semiconductor device and the method for manufacturing the same of the present invention, a diamond substrate and a semiconductor layer can be easily bonded, and the semiconductor device has excellent heat dissipation and heat resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a cross-sectional view of a substrate for forming a semiconductor device according to one embodiment of the present invention.

[0044] Figure 2 This is a cross-sectional view of a semiconductor stacked structure according to one embodiment of the present invention.

[0045] Figure 3 It is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0046] Figure 4 This is a flowchart showing a part of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0047] Figure 5 This is a flowchart showing a part of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0048] Figure 6 This is a flowchart showing a part of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0049] Figure 7 This is a transmission electron microscope (TEM) photograph of a cross section of the semiconductor stacked structure before heat treatment according to one embodiment of the present invention.

[0050] Figure 8 This is a TEM photograph of a cross section of the semiconductor stacked structure after heat treatment according to one embodiment of the present invention. DETAILED DESCRIPTION

[0051] [Substrate for forming a semiconductor device]

[0052] A substrate for forming a semiconductor device according to the present invention comprises a diamond substrate and a silicon carbide layer located on a part or the whole of one surface of the diamond substrate.

[0053] Hereinafter, a substrate for forming a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

[0054] like Figure 1 As shown, a substrate 1 for forming a semiconductor device includes a diamond substrate 10 and a silicon carbide layer 20 located on one surface 10 a of the diamond substrate 10 .

[0055] The thickness T1 of the substrate 1 for forming the semiconductor device is preferably 1 to 500 μm, more preferably 10 to 400 μm, and even more preferably 50 to 300 μm. If the thickness T1 is greater than the lower limit, the physical strength of the semiconductor device can be further improved. If the thickness T1 is less than the upper limit, the size of the semiconductor device can be more compact.

[0056] For example, the thickness T1 can be measured by a digital vernier caliper or the like.

[0057] In this specification, "thickness T1" is the arithmetic mean value of thicknesses of 10 randomly selected locations.

[0058] The thickness T of the diamond substrate 10 10 For example, it is preferably 10 to 500 μm, more preferably 30 to 400 μm, and even more preferably 50 to 300 μm. 10 If the thickness T is greater than the above lower limit, the physical strength of the semiconductor device can be further improved. 10 When the value is equal to or less than the above upper limit, the size of the semiconductor device can be further compacted.

[0059] For example, the thickness T can be measured by a digital vernier caliper, etc. 10 .

[0060] In this specification, "thickness T 10 ” is the arithmetic mean of the thickness of 10 randomly selected locations.

[0061] The diamond substrate 10 has high thermal conductivity, and the heat dissipation performance of a semiconductor device including the diamond substrate 10 can be further improved.

[0062] The thermal conductivity of the diamond substrate 10 is, for example, preferably 500 W / m·K or more, more preferably 700 W / m·K or more, and further preferably 1000 W / m·K or more. If the thermal conductivity of the diamond substrate 10 is greater than the above lower limit, the heat dissipation of the semiconductor device can be further improved. The upper limit of the thermal conductivity of the diamond substrate 10 is not particularly limited, and is, for example, 3000 W / m·K. The thermal conductivity of the diamond substrate 10 is preferably 500 to 3000 W / m·K, more preferably 700 to 3000 W / m·K, and further preferably 1000 to 3000 W / m·K.

[0063] For example, the thermal conductivity of the diamond substrate 10 can be measured by a temperature gradient method, a circular plate heat flow meter method, or the like.

[0064] The thermal conductivity of the diamond substrate 10 can be adjusted according to the purity, degree of crystallization, type of crystal, density, and combination of these of the diamond constituting the diamond substrate 10 .

[0065] The thickness T of the silicon carbide layer 20 is 20 The thickness T is 20 nm or less, preferably 1 nm or more and 18 nm or less, more preferably 2 nm or more and 16 nm or less, and still more preferably 5 nm or more and 15 nm or less. 20 If the thickness T is greater than or equal to the above lower limit, the arithmetic mean roughness Ra of the surface 20 a of the silicon carbide layer 20 can be further reduced. 20 When the value is equal to or less than the above upper limit, the heat dissipation property of the semiconductor device can be further improved.

[0066] For example, the thickness T can be obtained by observing a cross section in the thickness direction of the substrate 1 for forming a semiconductor device using an electron microscope or the like. 20 As the electron microscope, for example, a transmission electron microscope (TEM) can be used.

[0067] In this specification, "thickness T 20 ” is the arithmetic mean of the thickness of 10 randomly selected locations.

[0068] The silicon carbide layer 20 has a higher thermal conductivity than a layer made of silicon alone. Therefore, a semiconductor device including the silicon carbide layer 20 can further improve heat dissipation compared to a semiconductor device including a layer made of silicon alone of the same thickness.

[0069] The thermal conductivity of the silicon carbide layer 20 is, for example, preferably 100 W / m·K or more, more preferably 150 W / m·K or more, and further preferably 200 W / m·K or more. If the thermal conductivity of the silicon carbide layer 20 is greater than the above lower limit, the heat dissipation of the semiconductor device can be further improved. The upper limit of the thermal conductivity of the silicon carbide layer 20 is not particularly limited, and is, for example, 450 W / m·K. The thermal conductivity of the silicon carbide layer 20 is preferably 100 to 450 W / m·K, more preferably 150 to 450 W / m·K, and further preferably 200 to 450 W / m·K.

[0070] For example, the thermal conductivity of the silicon carbide layer 20 can be measured by a temperature gradient method, a circular plate heat flow meter method, or the like.

[0071] The thermal conductivity of the silicon carbide layer 20 can be adjusted by the purity, degree of crystallization, type of crystals, density, and a combination of these of the silicon carbide constituting the silicon carbide layer 20 .

[0072] The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is less than 0.5nm, preferably less than 0.45nm, and more preferably less than 0.4nm. If the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is less than the above upper limit value, the bonding property with the semiconductor layer in the semiconductor stacked structure described later can be further improved. Therefore, the heat dissipation and heat resistance of the semiconductor device are further improved. The lower limit value of the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is not particularly limited, for example, it is set to 0.01nm. The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is preferably 0.01~0.5nm, more preferably 0.01~0.45nm, and further preferably 0.01~0.4nm.

[0073] For example, the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is determined by analysis using an atomic force microscope (AFM). The measurement conditions of the atomic force microscope (AFM) may be those described in the later-described embodiments.

[0074] It is preferable that part or all of the silicon carbide contained in the silicon carbide layer 20 is amorphous. If the silicon carbide is amorphous, the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 can be further reduced.

[0075] Whether silicon carbide is amorphous can be determined by observing a cross section in the thickness direction of the substrate 1 for forming a semiconductor device through an electron microscope. For example, when no stripe structure is observed in the silicon carbide layer 20 of the substrate 1 for forming a semiconductor device, and the silicon carbide does not conform to any of cubic, hexagonal, and rhombohedral crystals, it is determined that "at least a portion of the silicon carbide contained in the silicon carbide layer 20 is amorphous." As the electron microscope, for example, a transmission electron microscope (TEM) can be used.

[0076] [Semiconductor stacked structure]

[0077] A semiconductor stacked structure according to the present invention comprises a diamond substrate, a semiconductor layer located on a part or the whole of one surface of the diamond substrate, and a silicon carbide layer located between the diamond substrate and the semiconductor layer.

[0078] The semiconductor layer includes nitride or oxide, the silicon carbide layer is a single layer, and the thickness of the silicon carbide layer is 20 nm or less.

[0079] Hereinafter, a semiconductor stacked structure according to an embodiment of the present invention will be described with reference to the drawings.

[0080] like Figure 2 The semiconductor stacked structure 2 comprises: a diamond substrate 10, a silicon carbide layer 20 located on one surface 10a of the diamond substrate 10, and a semiconductor layer 30 located on the surface 20a of the silicon carbide layer 20. That is, the semiconductor stacked structure 2 comprises: a diamond substrate 10, a semiconductor layer 30 located on one surface 10a of the diamond substrate 10, and a silicon carbide layer 20 located between the diamond substrate 10 and the semiconductor layer 30.

[0081] The following is about Figure 1 The same structures are denoted by the same reference numerals, and description thereof will be omitted.

[0082] The thickness T2 of the semiconductor stacked structure 2 is preferably 2 to 1000 μm, more preferably 5 to 700 μm, and even more preferably 10 to 500 μm. If the thickness T2 is greater than the lower limit, the physical strength of the semiconductor device can be further improved. If the thickness T2 is less than the upper limit, the size of the semiconductor device can be more compact.

[0083] For example, the thickness T2 can be measured by a digital vernier caliper or the like.

[0084] In this specification, "thickness T2" is the arithmetic mean value of thicknesses of 10 randomly selected locations.

[0085] The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 at the interface between the silicon carbide layer 20 and the semiconductor layer 30 is preferably 0.5 nm or less, more preferably 0.45 nm or less, and even more preferably 0.4 nm or less. If the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is below the above upper limit, the bonding property with the semiconductor layer 30 can be further improved. Therefore, the heat dissipation and heat resistance of the semiconductor device are further improved. The lower limit of the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is not particularly limited, for example, it is set to 0.01 nm. The arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 is preferably 0.01 to 0.5 nm, more preferably 0.01 to 0.45 nm, and even more preferably 0.01 to 0.4 nm.

[0086] For example, the arithmetic mean roughness Ra of the surface 20a of the silicon carbide layer 20 can be determined by analyzing using an atomic force microscope (AFM) after removing the semiconductor layer 30. The measurement conditions of the atomic force microscope (AFM) can be the measurement conditions described in the embodiment described later.

[0087] The silicon carbide layer 20 is a single layer. Here, "single layer" means a single layer formed in one process, which does not include a bonding interface inside and may include amorphous silicon carbide, and is formed in a layer or stripe shape.

[0088] Whether the silicon carbide layer 20 is a single layer can be determined by, for example, observation of a cross section in the thickness direction of the semiconductor stacked structure 2 using a transmission electron microscope (TEM) and element distribution analysis using an energy dispersive X-ray spectrometer (EDX) attached to the TEM. When the silicon carbide layer 20 is not a single layer, that is, a boundary line (bonding interface) parallel to the interface between the silicon carbide layer 20 and the semiconductor layer 30 is confirmed within the silicon carbide layer-silicon carbide layer, and an element derived from bonding (e.g., iron) is detected at this position.

[0089] By forming the silicon carbide layer 20 as a single layer, a semiconductor stacked structure 2 having a small number of bonding interfaces is realized, compared with a case where silicon carbide layers are formed on the bonding surface of the diamond substrate 10 and the bonding surface of the semiconductor layer 30 and these silicon carbide layers are bonded to each other. As a result, the thermal resistance caused by the bonding interface can be reduced, and the heat dissipation and heat resistance can be further improved.

[0090] The semiconductor layer 30 includes nitride or oxide. Examples of nitride include gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and mixed crystals thereof. The semiconductor layer 30 may be a multilayer structure composed of these nitrides.

[0091] Examples of the oxide include gallium oxide (Ga2O3), aluminum oxide (Al2O3), and mixed crystals thereof. The semiconductor layer 30 may have a multilayer structure composed of these oxides.

[0092] The thickness T of the semiconductor layer 30 30 For example, it is preferably 0.1 to 50 μm, more preferably 0.2 to 20 μm, and even more preferably 0.5 to 10 μm. 30 If the thickness T is greater than the above lower limit, the output of the semiconductor device can be further improved. 30 If it is below the upper limit, the temperature rise of the semiconductor device due to the thermal resistance of the nitride or oxide contained in the semiconductor layer 30 is suppressed, and the bonding property with the diamond substrate 10 is further improved. Therefore, the heat dissipation and heat resistance of the semiconductor device can be further improved.

[0093] The thickness T can be obtained by observing a cross section of the semiconductor stacked structure 2 in the thickness direction using an electron microscope or the like, for example. 30 As the electron microscope, for example, a transmission electron microscope (TEM) can be used.

[0094] In this specification, "thickness T 30 ” is the arithmetic mean of the thickness of 10 randomly selected locations.

[0095] [Semiconductor devices]

[0096] The semiconductor device of the present invention includes the semiconductor stacked structure of the present invention, and part or all of the silicon carbide contained in the silicon carbide layer is polycrystalline.

[0097] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

[0098] like Figure 3 As shown, the semiconductor device 3 includes a diamond substrate 10 , a semiconductor layer 30 located on a portion of one surface 10 a of the diamond substrate 10 , and a silicon carbide layer 20 located between the diamond substrate 10 and the semiconductor layer 30 .

[0099] In the semiconductor device 3, the semiconductor layer 30 and a portion of the silicon carbide layer 20 in the semiconductor stacked structure 2 are removed. Of the silicon carbide layer 20 and the semiconductor layer 30 remaining on the diamond substrate 10, a gate electrode 41, a source electrode 42, and a drain electrode 43 are formed on the surface of the semiconductor layer 30.

[0100] The following is about Figure 2 The same structures are denoted by the same reference numerals, and description thereof will be omitted.

[0101] A known material can be used as a material constituting the gate electrode 41. Examples of the material constituting the gate electrode 41 include nickel, gold, palladium, and the like.

[0102] A known material can be used as a material constituting source electrode 42. Examples of the material constituting source electrode 42 include titanium, aluminum, nickel, gold, and the like, and multilayer structures thereof.

[0103] A known material can be used as a material constituting the drain electrode 43. Examples of the material constituting the drain electrode 43 include titanium, aluminum, nickel, gold, and the like, and multilayer structures thereof.

[0104] The thickness of the gate electrode 41 is, for example, preferably 0.1 to 20 μm, more preferably 0.5 to 15 μm, and even more preferably 1 to 10 μm. If the thickness of the gate electrode 41 is the above lower limit, the output of the semiconductor device 3 can be further improved. If the thickness of the gate electrode 41 is below the above upper limit, the gate electrode 41 can be miniaturized, thereby increasing the operating frequency of the semiconductor device 3. In addition, if the thickness of the gate electrode 41 is below the above upper limit, the production efficiency of the semiconductor device 3 can be further improved.

[0105] The thickness of the source electrode 42 is the same as the thickness of the gate electrode 41 .

[0106] The thickness of the drain electrode 43 is the same as the thickness of the gate electrode 41 .

[0107] The thickness of the electrode can be measured, for example, using a digital vernier caliper, etc. The thickness of the electrode is the arithmetic mean of the thicknesses of 10 randomly selected locations.

[0108] The shapes of the patterns of the gate electrode 41 , the source electrode 42 , and the drain electrode 43 are not particularly limited and may be appropriately determined according to the purpose of the semiconductor device 3 and the like.

[0109] In the semiconductor stacked structure 2 , the shape of the pattern of the semiconductor layer 30 and the silicon carbide layer 20 to be removed is not particularly limited and may be appropriately determined according to the purpose of the semiconductor device 3 and the like.

[0110] In semiconductor device 3 , part or all of silicon carbide included in silicon carbide layer 20 is polycrystalline.

[0111] When silicon carbide is polycrystalline, it is possible to further improve the bonding strength between silicon carbide layer 20 and semiconductor layer 30. Therefore, it is possible to further improve the heat dissipation and heat resistance of semiconductor device 3.

[0112] Whether silicon carbide is polycrystalline can be determined by observing a cross section in the thickness direction of the semiconductor device 3 using an electron microscope or the like. For example, if a stripe structure is seen in a portion of the silicon carbide layer, it means that the atoms in that portion are periodically arranged, that is, they have been crystallized. Thus, when a stripe structure is seen in at least a portion of the silicon carbide layer, it is determined that "at least a portion of the silicon carbide contained in the silicon carbide layer 20 is polycrystalline." As an electron microscope, for example, a transmission electron microscope (TEM) can be used.

[0113] [Method for manufacturing a substrate for forming a semiconductor device]

[0114] The manufacturing method of the substrate for forming a semiconductor device of the present invention has a deposition step, in which silicon carbide is deposited on a part or all of a surface of a diamond substrate to form a silicon carbide layer with a thickness of less than 20nm and an arithmetic mean roughness Ra of less than 0.5nm.

[0115] The deposition step is a step of depositing silicon carbide on a part or all of one surface of the diamond substrate to form a silicon carbide layer having a thickness of 20 nm or less and a surface arithmetic mean roughness Ra of 0.5 nm or less.

[0116] Examples of a method for depositing silicon carbide include sputtering, vacuum deposition, chemical deposition, and physical deposition.

[0117] As a method of depositing silicon carbide, a sputtering method is preferable because the thickness of the silicon carbide layer can be made uniform and thinner.

[0118] Examples of the sputtering method include a bipolar method, a magnetron method, reactive sputtering, ion beam sputtering, and electron cyclotron resonance (ECR) sputtering. As the sputtering method, the magnetron method is preferred because silicon carbide can be stably deposited and the arithmetic mean roughness Ra of the surface is easily 0.5 nm or less.

[0119] [Method for producing semiconductor stacked structure]

[0120] The manufacturing method of the semiconductor stacked structure of the present invention includes: a process of manufacturing a substrate for forming a semiconductor device, manufacturing a substrate for forming a semiconductor device by the manufacturing method of a substrate for a semiconductor device of the present invention; and a bonding process, then bonding the surface of the silicon carbide layer to a semiconductor layer including a nitride or an oxide.

[0121] The process of manufacturing a substrate for forming a semiconductor device is the same as the above-mentioned method of manufacturing a substrate for forming a semiconductor device.

[0122] The bonding step is a step of bonding the surface of the silicon carbide layer to the semiconductor layer including nitride or oxide after the step of manufacturing the substrate for forming the semiconductor device.

[0123] Examples of a method for bonding the silicon carbide layer and the semiconductor layer include a surface activated bonding (SAB) method, a high pressure bonding method, and a high vacuum bonding method.

[0124] The SAB method is a method of cleaning the surface to be bonded with a chemical solution and pure water, activating it with plasma, ions, etc. in a vacuum chamber, and then bonding in a low-temperature atmosphere ranging from room temperature (e.g., 25°C) to 400°C.

[0125] The high pressure bonding method is a method of bonding by washing the surfaces to be bonded with a chemical solution and pure water, and then applying a high pressure of 0.1 MPa to 10 MPa in a heated state in the atmosphere.

[0126] High vacuum bonding is a process where the surfaces to be bonded are cleaned with chemical solutions and pure water, and then -6 Pa to 10 -3 The bonding method is carried out in a high vacuum atmosphere of Pa.

[0127] As a method for bonding the silicon carbide layer and the semiconductor layer, surface activated bonding is preferable because bonding can be performed at room temperature (eg, 5 to 30° C.) and bonding can be performed more easily.

[0128] For example, from the viewpoint of suppressing degradation of the silicon carbide layer and the semiconductor layer, the temperature in the bonding step (bonding temperature) is preferably 0 to 400° C., more preferably 0 to 100° C., and even more preferably 5 to 30° C. (normal temperature).

[0129] [Method for manufacturing semiconductor device]

[0130] The method for manufacturing a semiconductor device of the present invention comprises: a step of manufacturing a semiconductor stacked structure by the method for manufacturing a semiconductor stacked structure of the present invention; and a heat treatment step of subjecting the semiconductor stacked structure to a heat treatment at 800° C. or higher.

[0131] Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to the drawings.

[0132] like Figures 4 to 6 As shown, the method for manufacturing a semiconductor device according to the present embodiment includes step A-1, step A-2, step A-3, step B-1, step B-2, step B-3, and step B-4.

[0133] like Figure 4As shown, step A-1 is a step of growing a nitride or oxide crystal on a crystal growth substrate to obtain a semiconductor layer and obtain a first stacked body.

[0134] Examples of the crystal growth substrate include a silicon substrate, a silicon carbide substrate, and a sapphire substrate. From the viewpoint of cost, a silicon substrate is preferable.

[0135] As a method for crystal growth, for example, metal organic chemical vapor phase growth method (MOCVD), molecular beam epitaxy method (MBE), hydride vapor phase epitaxy (HVPE), sublimation method and flux method can be cited. As a method for crystal growth, MOCVD is preferred from the viewpoint of crystal quality.

[0136] Step A-2 is a step of bonding the surface of the semiconductor layer of the first stacked body to a supporting substrate to obtain a second stacked body.

[0137] The supporting substrate is not particularly limited as long as it is suitable for supporting the semiconductor layer during the period from removing the crystal growth substrate from the semiconductor layer in the subsequent process to bonding the silicon carbide layer to the semiconductor layer. Examples of the supporting substrate include silicon substrates, silicon carbide substrates, molybdenum substrates, glass substrates, and the like.

[0138] The method for bonding the semiconductor layer to the supporting substrate is not particularly limited, but from the viewpoint of easy detachment and sufficient support of the semiconductor layer, adhesion using wax, brazing material, solder, or the like is preferred.

[0139] Step A-3 is a step of removing the crystal growth substrate from the second stacked body obtained in step A-2 and polishing the back surface of the semiconductor layer to obtain a third stacked body.

[0140] The method for removing the crystal growth substrate is not particularly limited, and examples thereof include dicing, grinding, polishing, and etching.

[0141] As a method of polishing the back surface of the semiconductor layer, chemical mechanical polishing (CMP) or the like can be cited, for example.

[0142] like Figure 5 As shown, step B-1 is a step of depositing silicon carbide on a diamond substrate to form a silicon carbide layer to obtain a fourth stacked body (a substrate for forming a semiconductor device).

[0143] Examples of methods for depositing silicon carbide on a diamond substrate include sputtering, vacuum evaporation, chemical evaporation, and physical evaporation. Sputtering is preferred because the thickness of the silicon carbide layer is uniform and can be thinner.

[0144] Step B-2 is a step of bonding the semiconductor layer of the third stacked body obtained in step A-3 and the silicon carbide layer of the fourth stacked body obtained in step B-1 to obtain a fifth stacked body.

[0145] As a method for bonding the semiconductor layer of the third stack and the silicon carbide layer of the fourth stack, for example, the SAB method, the high pressure bonding method, and the high vacuum bonding method can be cited. As a method for bonding the semiconductor layer of the third stack and the silicon carbide layer of the fourth stack, the SAB method is preferred because bonding can be performed at room temperature and bonding can be performed more easily.

[0146] like Figure 6 As shown, step B-3 is a step of removing the supporting substrate from the fifth stacked body obtained in step B-2 to obtain a sixth stacked body (semiconductor stacked structure).

[0147] Examples of a method for removing the supporting substrate from the fifth stacked body include peeling, separation, grinding, polishing, and etching.

[0148] Step B-4 is a step of applying a treatment including a mesa formation treatment and a heat treatment to the sixth stacked body to apply an element structure to the semiconductor layer. Here, the element structure refers to a structure having a buffer layer, a channel layer, a barrier layer, and a contact layer from the side close to the silicon carbide layer.

[0149] The heating temperature when performing the heat treatment is, for example, preferably 800°C or more, more preferably 850°C or more, and even more preferably 900°C or more. If the heating temperature is equal to or greater than the above lower limit, the element structure can be fully applied to the semiconductor layer. The upper limit of the heating temperature is not particularly limited, but from the viewpoint of suppressing the degradation of the semiconductor layer, it is, for example, set to 1200°C. The heating temperature when performing the heat treatment is preferably 800-1200°C, more preferably 850-1200°C, and even more preferably 900-1200°C.

[0150] By subjecting the sixth stack to heat treatment, polycrystallization of silicon carbide contained in the silicon carbide layer of the sixth stack is promoted. When the silicon carbide is polycrystalline, the bonding strength between the silicon carbide layer and the semiconductor layer can be further improved. Therefore, the heat dissipation and heat resistance of the semiconductor device can be further improved.

[0151] After the sixth stack is subjected to heat treatment, the stack is subjected to photolithography, the silicon carbide layer and the semiconductor layer on the diamond substrate are processed into desired shapes, and then a gate electrode, a source electrode, and a drain electrode are stacked to obtain a semiconductor element (semiconductor device).

[0152] As materials constituting the gate electrode, the source electrode, and the drain electrode, for example, known metals such as nickel, gold, titanium, aluminum, palladium, and multilayer structures thereof can be used.

[0153] The gate electrode, source electrode, and drain electrode are obtained by forming a metal stack film by vacuum evaporation or the like. When the source electrode and the drain electrode are formed, after the metal stack film is formed, heat treatment is performed to react with the nitride or oxide contained in the semiconductor layer. The heating temperature for this purpose is preferably 650° C. or more, more preferably 700° C. or more, and even more preferably 800° C. or more, for example.

[0154] Through the above steps, the silicon carbide layer on the surface of the diamond substrate is bonded to the semiconductor layer, thereby obtaining a semiconductor element (semiconductor device) having a gate electrode, a source electrode, and a drain electrode formed on the surface of the semiconductor layer.

[0155] Example

[0156] Hereinafter, the present invention will be described in further detail using examples, but the present invention is not limited to these examples.

[0157] A rectangular substrate with a length of 4 mm, a width of 4 mm, and a thickness of 350 μm was prepared as a diamond substrate. One surface of the diamond substrate was analyzed using an atomic force microscope (AFM), and its arithmetic mean roughness Ra was found to be 0.77 nm. Silicon carbide was deposited on one surface of the diamond substrate by sputtering to form a silicon carbide layer with a thickness of 13 nm, thereby obtaining a fourth stack (process B-1).

[0158] When the surface of the silicon carbide layer of the fourth stacked body was analyzed by AFM, it was found that the arithmetic mean roughness Ra was 0.37 nm. The measurement conditions of the arithmetic mean roughness Ra are as follows.

[0159] ·Measurement device: SPM-9600 (manufactured by Shimadzu Corporation)

[0160] · Measurement probe: NCHR (manufactured by NanoWorld)

[0161] Measuring range: 1μm 2

[0162] Next, a silicon substrate with a diameter of 4 inches (101.6 mm) and a thickness of 500 μm is prepared as a substrate for crystal growth, and gallium nitride as a nitride is grown on one surface of the silicon substrate by MOCVD to form a semiconductor layer with a thickness of 1 μm, thereby obtaining a first stack (process A-1). Then, the semiconductor layer of the first stack is cut into a rectangle with a length of 10 mm and a width of 12 mm. As a supporting substrate, a rectangle with a length of 20 mm, a width of 20 mm, and a thickness of 500 μm is bonded to the silicon substrate with wax to obtain a second stack (process A-2). Then, the crystal growth substrate of the second stack is removed by etching with a hydrofluoric acid-nitric acid mixture, and the back of the semiconductor layer is polished by CMP to obtain a third stack (process A-3).

[0163] Next, the semiconductor layer of the third stack and the silicon carbide layer of the fourth stack are bonded by the SAB method to obtain a fifth stack (process B-2). The supporting substrate of the obtained fifth stack is removed by etching with a hydrofluoric acid-nitric acid mixture to obtain a sixth stack (semiconductor stack structure) (process B-3).

[0164] The cross section of the obtained sixth laminate in the thickness direction was observed by TEM. Figure 7 shown.

[0165] like Figure 7 As shown, it can be confirmed that a 13 nm thick silicon carbide thin layer (SiC thin layer) is formed between the diamond substrate and the semiconductor layer (gallium nitride, GaN). No stripe structure is observed in the silicon carbide thin layer, and it can be confirmed that at least a portion of the silicon carbide contained in the silicon carbide layer is amorphous.

[0166] Then, the sixth stack was heat treated at 1000°C for 3 minutes (step B-4). The cross section of the semiconductor stack structure after the heat treatment in the thickness direction was observed by TEM. Figure 8 shown.

[0167] like Figure 8 As shown, in the image obtained by magnifying a part of the silicon carbide layer (SiC thin layer) by 1.5 times, a stripe-like structure is seen, and it can be confirmed that a part of the silicon carbide contained in the silicon carbide layer is polycrystalline.

[0168] In addition, if Figure 8 As shown, meltback did not occur at the interface between the silicon carbide layer and the semiconductor layer, and it was confirmed that the semiconductor stacked structure had sufficient heat resistance.

[0169] Description of Reference Numerals

[0170] 1Substrate for forming a semiconductor device

[0171] 2 Semiconductor stacked structure

[0172] 3 Semiconductor devices

[0173] 10 Diamond substrate

[0174] 10a One surface of a diamond substrate

[0175] 20 Silicon carbide layer

[0176] 20a Surface of silicon carbide layer

[0177] 30 Semiconductor layer

[0178] 41 Gate electrode

[0179] 42 Source electrode

[0180] 43 Drain electrode

Claims

1. A substrate for forming a semiconductor device, comprising: a diamond substrate, and a silicon carbide layer located on a part or the whole of one surface of the diamond substrate, The thickness of the silicon carbide layer is less than 20 nm, The silicon carbide layer has a surface with an arithmetic mean roughness Ra of 0.5 nm or less.

2. The substrate for forming a semiconductor device according to claim 1, wherein A part or all of silicon carbide included in the silicon carbide layer is amorphous.

3. A semiconductor stacked structure, comprising: Diamond substrate; A semiconductor layer located on a part or the whole of one surface of the diamond substrate; as well as a silicon carbide layer located between the diamond substrate and the semiconductor layer, The semiconductor layer includes nitride or oxide, The silicon carbide layer is a single layer, The thickness of the silicon carbide layer is less than 20 nm.

4. The semiconductor stacked structure according to claim 3, wherein: An arithmetic mean roughness Ra of a surface of the silicon carbide layer at an interface between the silicon carbide layer and the semiconductor layer is 0.5 nm or less.

5. The semiconductor stacked structure according to claim 3 or 4, wherein: A part or all of silicon carbide included in the silicon carbide layer is amorphous. 6 . A semiconductor device comprising the semiconductor stacked structure according to claim 3 , wherein a part or all of the silicon carbide contained in the silicon carbide layer is polycrystalline.

7. A method for manufacturing a substrate for forming a semiconductor device, comprising: In the deposition step, silicon carbide is deposited on a part or the whole of one surface of the diamond substrate to form a silicon carbide layer having a thickness of 20 nm or less and an arithmetic mean roughness Ra of the surface of 0.5 nm or less.

8. A method for manufacturing a semiconductor stacked structure, wherein: A substrate for forming a semiconductor device is manufactured by the method for manufacturing a substrate for forming a semiconductor device according to claim 7, Next, the surface of the silicon carbide layer is bonded to a semiconductor layer including nitride or oxide.

9. A method for manufacturing a semiconductor device, wherein: A semiconductor stacked structure is manufactured by the method for manufacturing a semiconductor stacked structure according to claim 8, and a heat treatment at 800°C or higher is performed on the semiconductor stacked structure.

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