Electrostatic carrier, processing system and processing method

Abstract

A processing method is a processing method of a chip using an electrostatic carrier having a main body portion having conductivity and having a plurality of through-holes in a thickness direction of the main body portion, and an insulating layer formed on a surface of the main body portion, the processing method comprises the following steps: arranging a plurality of chips on a holding surface of the electrostatic bearing part; a power supply unit that supplies power to the main body unit and charges the main body unit; and bringing a ground wire into contact with the chip to generate an electrostatic force between the chip and the main body portion.

Description

Technical Field

[0001] The present disclosure relates to an electrostatic bearing component, a processing system and a processing method. Background Art

[0002] Patent document 1 discloses a chip on wafer (CoW) bonding method for mounting chips on a wafer. In the chip on wafer bonding method, before a plurality of chips are formally bonded to corresponding bonding portions of a substrate, the bonding surfaces on the chip side are subjected to surface activation treatment and hydrophilization treatment to temporarily bond the plurality of chips to the substrate.

[0003] Patent document 2 discloses a reinforcing member made of a thin plate material such as a silicon wafer. The reinforcing member has a reinforcing member main body having a thin plate-shaped electrostatic holding portion, and the electrostatic holding portion is formed by burying an electrode portion inside an electrical insulating layer (polyimide layer). Moreover, by applying a high voltage to the electrode portion and supplying a charge having a polarity opposite to the polarity of the voltage applied to the electrode portion to the reinforcing object, the electrostatic holding portion exerts an adsorption force to adsorb the reinforcing object, so that the reinforcing member main body functions as a reinforcing member.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 6337400

[0007] Patent Document 2: Japanese Patent Application Publication No. 2009-099674 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] The technology disclosed herein provides an electrostatic carrier capable of appropriately transferring diced chips to a wafer in a chip-on-wafer manufacturing process.

[0010] Solutions for solving problems

[0011] One embodiment of the present disclosure is an electrostatic carrier used in a chip-on-wafer manufacturing process, comprising: a main body portion having conductivity and a plurality of through holes in a thickness direction of the main body portion; and an insulating layer formed on a surface of the main body portion.

[0012] Effects of the Invention

[0013] According to the present disclosure, it is possible to provide an electrostatic carrier capable of appropriately transferring diced chips to a wafer in a chip-on-wafer manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is an explanatory diagram schematically showing the structure of a chip attached to a dicing sheet.

[0015] Figure 2 It is a cross-sectional view schematically showing the structure of the electrostatic carrier according to the present embodiment.

[0016] Figure 3 It is a plan view schematically showing the structure of the electrostatic carrier according to the present embodiment.

[0017] Figure 4 It is a cross-sectional view schematically showing another structure of the electrostatic bearing member.

[0018] Figure 5 It is a plan view schematically showing another structure of the electrostatic bearing member.

[0019] Figure 6 It is a cross-sectional view schematically showing the structure of a wafer to be bonded with a chip.

[0020] Figure 7 It is a plan view schematically showing the structure of the processing system according to the present embodiment.

[0021] Figure 8 It is a cross-sectional view schematically showing the structure of a chip arrangement device.

[0022] Fig. 9 It is an explanatory diagram showing another configuration example of the static eliminating unit.

[0023] Fig.10 It is an explanatory diagram showing another configuration example of the static eliminating unit.

[0024] Fig.11 It is a cross-sectional view schematically showing the structure of the bonding device.

[0025] Fig.12 1 is a flowchart showing main steps of a chip-on-wafer manufacturing process according to the present embodiment.

[0026] Fig.13 It is an explanatory diagram showing a side view of main steps of the chip-on-wafer manufacturing process according to the present embodiment.

[0027] Fig.14 This is an explanatory diagram showing a side view of a state in which a chip in a chip arrangement device is electrostatically attracted to an electrostatic bearing member.

[0028] Fig.15 It is an explanatory diagram showing a state in which a chip is detached from an electrostatic bearing member in a bonding apparatus.

[0029] Fig.16 It is an explanatory diagram showing a state in which a chip is detached from an electrostatic bearing member in a bonding apparatus.

[0030] Fig.17 It is a cross-sectional view showing another structural example of the bonding device.

[0031] Fig.18 It is a cross-sectional view showing another structural example of the bonding device.

[0032] Fig.19 It is a cross-sectional view showing another structural example of the bonding device. DETAILED DESCRIPTION

[0033] In recent years, in the manufacturing process of semiconductor devices, in response to the demand for further performance and high density of the devices, research on chip-on-wafer (CoW) manufacturing processes has been conducted as a form of three-dimensional mounting technology. As an example, the manufacturing of chip-on-wafer is carried out by the method described in Patent Document 1.

[0034] In the chip-on-wafer manufacturing process, as also described in Patent Document 1, before a semiconductor chip (hereinafter, simply referred to as a "chip") is formally mounted on a semiconductor substrate (hereinafter, referred to as a "wafer"), a series of treatments including surface activation, hydrophilization, and removal of a protective film are required on the bonding surface of the chip. These series of treatments on the chip are performed, for example, in a state where the chip is arranged on a dicing tape fixed to a dicing frame. However, when a series of treatments are performed in such a state, the dicing tape on which the chip is arranged is damaged and cannot be reused.

[0035] Therefore, the inventors have conducted in-depth research and found the possibility of suppressing the loss of the dicing tape in the chip-on-wafer manufacturing process by applying an electrostatic holding mechanism. Specifically, in the chip-on-wafer manufacturing process, the above series of processes are performed while the chip is held on a carrier substrate having an adsorption holding function based on electrostatic (Coulomb) force (hereinafter referred to as "electrostatic carrier (ESW: Electro Static Carrier Wafer: electrostatic carrier wafer)"), instead of performing the above series of processes on the chip on the dicing tape.

[0036] Moreover, although Patent Document 2 discloses an electrostatic strengthening device for holding and strengthening thin plate materials such as silicon wafers, it does not record the process of formally mounting the chips on the wafer to be mounted after holding multiple chips on a carrier wafer by electrostatic adsorption and performing the above-mentioned series of processes.

[0037] In addition, as disclosed in Patent Document 2, in an electrostatic carrier used for transferring a thin plate material such as a silicon wafer, an insulating layer (e.g., a polyimide layer) covering the periphery of the electrode portion for insulation is a necessary structure. However, if the insulating layer covering the electrode portion is hard (having a large elastic modulus), there is a possibility that the charge leaks through the conductive liquid used in the above series of processes, and the electrostatic adsorption force of the thin plate material to the electrostatic carrier is lost.

[0038] Furthermore, Patent Document 2 does not describe the reduction in electrostatic adsorption force caused by the leakage of electric charges through the conductive liquid.

[0039] The technology disclosed herein provides an electrostatic carrier that can appropriately transfer the cut chips to the wafer in the chip manufacturing process on the wafer. Below, the processing system and processing method involved in this embodiment are described with reference to the accompanying drawings. In addition, in this specification and the accompanying drawings, the same figure marks are marked on the elements with substantially the same functional structure, thereby omitting repeated descriptions.

[0040] In the processing system 10 described later involved in this embodiment, a plurality of chips C arranged and pasted on the adhesive surface of the dicing tape T described later are arranged on the electrostatic carrier Cw described later, and the plurality of chips C on the electrostatic carrier Cw are further bonded to the wafer W as the mounting object (chip-on-wafer manufacturing process). Hereinafter, among the plurality of chips C, the surface on the side where the device layer D described later is formed is referred to as the surface Ca (or "device surface"), and the surface on the side opposite to the surface Ca (device surface) and pasted to the dicing tape T is referred to as the back side Cb.

[0041] like Figure 1 As shown, on the chip C, a silicon layer Si, a device layer D including a plurality of devices, and a protective film P for protecting the device layer D are sequentially formed from the back surface Cb side to the front surface Ca side. The silicon layer Si on the back surface Cb side of the chip C is attached to a dicing tape T.

[0042] In addition, when the cutting tape T is transported in the processing system 10 described later, Figure 1 Shown is fixed to the cutting frame F.

[0043] The electrostatic carrier Cw has an adsorption surface on the upper surface for electrostatically adsorbing and vacuum adsorbing the plurality of chips C. Figure 2 As shown in FIG. 1 , the electrostatic carrier Cw has a structure in which an insulating layer 2 is formed on the surface of a main body 1. Therefore, in the electrostatic carrier Cw according to the technology disclosed in the present invention, an electrode portion (electrode wiring pattern) for electrostatically adsorbing the chip C is not formed on the main body 1. Figure 2 The silicon layer Si on the back surface Cb side of the chip C is held by suction.

[0044] The main body 1 has a diameter substantially the same as that of a wafer W to be installed on the chip C, and a thickness substantially the same as that of the wafer W to be installed on the chip C. The main body 1 is made of any conductive material, such as silicon, aluminum, aluminum alloy, stainless steel, or titanium. In other words, a silicon substrate as a conductor substrate may be used as the main body 1. Alternatively, the main body 1 may have a diameter substantially the same as that of the wafer W to be installed on the chip C, and a thickness different from that of the wafer W (e.g., 500 μm to 1000 μm).

[0045] In addition, if Figure 2 and Figure 3 As shown, the main body 1 is formed with a plurality of through holes 1a penetrating in the thickness direction of the main body 1 in a manner corresponding to the holding position of the holding chip C in the adsorption surface of the electrostatic carrier Cw. In one example, the holding position of the holding chip C in the adsorption surface of the electrostatic carrier Cw is configured in a manner corresponding to the bonding position of the bonding chip C on the mounting surface of the wafer W (the mounting position of the mounting chip C).

[0046] The plurality of through holes 1 a can be formed at arbitrary positions within the adsorption surface of the electrostatic carrier Cw.

[0047] In one example, the plurality of through holes 1a may be Figure 2 and Figure 3 As shown, they are formed in one-to-one correspondence with each of the plurality of chips C held on the electrostatic bearing member Cw, in other words, they are formed in the same number as the plurality of chips C held on the electrostatic bearing member Cw.

[0048] Alternatively, in one example, the plurality of through holes 1a may also be Figure 4 and Figure 5 As shown, a plurality of through holes 1a are formed corresponding to each of the plurality of chips C held on the electrostatic carrier Cw, in other words, more than the plurality of chips C held on the electrostatic carrier Cw. In this case, there is no particular limitation on the number, size, interval and arrangement of the through holes 1a, but it is expected that the number, size and interval of the through holes 1a are determined by ensuring the strength (rigidity) that does not cause deformation such as bending in the electrostatic carrier Cw. In one example, the size of the through hole 1a is The formation interval (the grid width of the metal portion remaining between the through holes 1a) is 0.5 mm to 1.0 mm.

[0049] The insulating layer 2 is a layer formed on the surface of the main body 1, and is made of a flexible and insulating material, such as polyimide, EVA (ethylene-vinyl acetate copolymer), etc. Figure 2As shown, the insulating layer 2 constitutes an adsorption surface for adsorbing the chip C in the electrostatic carrier Cw. The thickness of the insulating layer 2 is a thickness that can hold the chip on the electrostatic carrier Cw by electrostatic adsorption, for example, 10 μm. Figure 2 and Figure 3 As shown, in the insulating layer 2, a plurality of through holes 2a (second through holes) are formed at positions corresponding to the positions of the through holes 1a formed in the main body 1 at the positions where the chip C is held within the adsorption surface of the electrostatic carrier Cw. The plurality of through holes 2a are preferably smaller in diameter than the plurality of through holes 1a formed in the main body 1.

[0050] In the technology disclosed herein, “the insulating layer 2 has flexibility” means that the elastic modulus of the insulating layer 2 on the main body 1 is 2 GPa or less, and preferably 0.5 GPa or less.

[0051] In the technology disclosed herein, “the insulating layer 2 has insulating properties” means that the insulation breakdown voltage of the insulating layer 2 on the main body 1 is 30 kV or more, preferably 40 kV or more.

[0052] In addition, depending on the purpose of processing the chip C on the electrostatic carrier Cw, the plurality of through holes 2a may not be formed in the insulating layer 2 (see also the above-mentioned Figure 4 and Figure 5 ), or a plurality of through holes 2a may be formed with the same diameter as the plurality of through holes 1a formed in the main body 1.

[0053] In other words, in the electrostatic carrier Cw according to the technology disclosed herein, it is sufficient that at least the insulating layer 2 having insulating properties is formed on the surface of the main body 1 having conductivity and having a plurality of through holes 1 a formed therein.

[0054] The insulating layer 2 is formed on the main body 1 by any method. For example, the insulating layer 2 may be a film formed by applying polyimide by spin coating on the surface of the main body 1. In addition, for example, the insulating layer 2 may be an insulating film formed by attaching an insulating film (e.g., a polyimide film, a back grinding (BG) tape) on the surface of the main body 1.

[0055] The through holes 1 a and 2 a of the main body portion 1 and the insulating layer 2 are formed by any method and at any timing.

[0056] For example, when forming both the through hole 1a of the main body 1 and the through hole 2a of the insulating layer 2, the through hole 1a and the through hole 2a may be simultaneously formed by laser irradiation or the like after the insulating layer 2 is formed on the surface of the silicon substrate corresponding to the main body 1. Alternatively, the through hole 1a of the main body 1 and the through hole 2a of the insulating layer 2 may be formed independently, and then the insulating layer 2 may be attached to the main body 1 while the through hole 1a and the through hole 2a are aligned.

[0057] For example, when forming through hole 1a only in body 1 and not through hole 2a in insulating layer 2, an insulating film may be attached to body 1 after forming through hole 1a in body 1 by laser irradiation, punching or the like.

[0058] The electrostatic carrier Cw involved in the disclosed technology is configured as described above, and the chip C is adsorbed and held on the adsorption surface by generating an electrostatic (Coulomb) force between the electrostatic carrier Cw and the chip C. The details of the method of holding the chip C by the electrostatic carrier Cw will be described later.

[0059] The wafer W on which the chip C is mounted is a semiconductor wafer such as a silicon substrate or a glass substrate used in the manufacturing process of a semiconductor device. Figure 6 As shown, a device layer Dw including a plurality of devices is formed on the surface Wa side as the mounting surface of the chip C. In one example, the thickness of the wafer W is configured to be the same as or slightly larger than the above-mentioned electrostatic carrier Cw, for example, 800 μm.

[0060] The device layer Dw is, for example, Figure 6 The device layers Dw are cut into pieces having substantially the same size as the mounted chips C. In other words, on the mounting surface of the wafer W, the device layers Dw cut into pieces become bonding positions for bonding the chips C in the wafer W (mounting positions for mounting the chips C).

[0061] In addition, a protective film Pw is formed on the surface Wa side of the wafer W, and the thickness of the protective film Pw is substantially the same as the thickness of the device layer Dw. In other words, on the surface Wa side of the wafer W, portions where the device layers Dw are exposed after being cut into pieces and portions where the protective film Pw is exposed between the device layers Dw are formed.

[0062] In addition, the size of the device layer Dw does not necessarily need to be substantially the same as that of the mounted chip C, and may be larger than the chip C, or may be smaller than the chip C.

[0063] In addition, the wafer W is bonded to the chip C as described later, but before bonding to the chip C, various pretreatments for bonding are performed on the surface Wa side of the wafer W. More specifically, a series of pretreatments including surface activation and hydrophilization are pre-performed on the surface Wa side of the wafer W in one or more pretreatment devices described later configured in the processing system 10.

[0064] like Figure 7 As shown, the processing system 10 has a structure in which a loading and unloading station 11 and a processing station 12 are connected as one body. In the loading and unloading station 11, for example, front-opening wafer transfer boxes Ff, Fc, and Fw capable of accommodating a plurality of dicing frames F, a plurality of electrostatic carriers Cw, and a plurality of wafers W are loaded and unloaded respectively between the outside. The processing station 12 is equipped with various processing devices for realizing a series of wafer chip manufacturing processes described later.

[0065] A front-opening pod stage 20 is provided at the loading / unloading station 11. In the example shown in the figure, a plurality of, for example, three front-opening pods Ff, Fc, and Fw are placed in a row in the Y-axis direction on the front-opening pod stage 20. The number and arrangement of the front-opening pods Ff, Fc, and Fw placed on the front-opening pod stage 20 are not limited to the present embodiment and can be determined arbitrarily.

[0066] A conveying device 30 is provided adjacent to the front-opening wafer transfer box loading platform 20 on the positive direction side of the X-axis of the front-opening wafer transfer box loading platform 20. The conveying device 30 is configured to be movable on a conveying path 31 extending in the Y-axis direction. In addition, the conveying device 30 has, for example, two conveying arms 32, 32 for holding and conveying a cutting frame F, an electrostatic bearing member Cw, and a wafer W (hereinafter, sometimes collectively referred to as "cutting frame F, etc."). Each conveying arm 32 is configured to be movable in a horizontal direction, a vertical direction, around a horizontal axis, and around a vertical axis. In addition, the structure of the conveying arm 32 is not limited to the present embodiment, and any structure can be adopted. Moreover, the conveying device 30 is configured to be able to convey the cutting frame F, etc. to the front-opening wafer transfer boxes Ff, Fc, Fw of the front-opening wafer transfer box loading platform 20 and the conveying device 40 described later.

[0067] In the loading / unloading station 11 , a conveyor device 40 for transferring the dicing frame F and the like to and from the processing station 12 is provided adjacent to the conveying device 30 on the positive side of the X-axis direction of the conveying device 30 .

[0068] The processing station 12 is provided with a transfer device 50, a chip placement device 60, a protective film removal device 70, a surface modification device 80, a surface hydrophilization device 90, a pretreatment device 100, and a bonding device 110. The number and arrangement of these various processing devices are not limited to the present embodiment and can be determined arbitrarily.

[0069] The conveying device 50 is provided on the positive X-axis direction side of the conveyor device 40. The conveying device 50 is configured to be movable on a conveying path 51 extending in the X-axis direction. In addition, the conveying device 50 has, for example, two conveying arms 52, 52 for holding and conveying the dicing frame F and the like. Each conveying arm 52 is configured to be movable in the horizontal direction, the vertical direction, around the horizontal axis, and around the vertical axis, and is configured to be able to convey the dicing frame F and the like to the conveyor device 40 carried in and out of the station 11 and the various processing devices of the processing station 12.

[0070] In the chip placement device 60, a plurality of chips C attached to the dicing tape T on the back surface Cb side are arranged on the adsorption surface of the electrostatic carrier Cw, which is a relay member when the chips C are mounted on the wafer W, in such a manner that the protective film P on the front surface Ca side is on the upper side. That is, in the chip placement device 60, the chip C is transferred from the dicing tape T to the electrostatic carrier Cw in such a manner that the front and back surfaces of the chip C are not reversed.

[0071] like Figure 8 As shown, a pickup region 60a and an arrangement region 60b are formed inside the chip arrangement device 60. In the pickup region 60a, chips C are picked up from the dicing frame F. In the arrangement region 60b, chips C are arranged on the electrostatic carrier Cw.

[0072] The pickup region 60 a is provided with a frame holding portion 61 , a push-up portion 62 , and a collet 63 .

[0073] The frame holding portion 61 has a holding surface for holding the dicing frame F on the upper surface, and holds the dicing frame F conveyed by the conveying device 50 in a state where the plurality of chips C attached to the dicing tape T face upward.

[0074] The lifting portion 62 is disposed below the frame holding portion 61 and is configured to be movable in the horizontal direction relative to the frame holding portion 61. If the frame holding portion 61 and the lifting portion 62 are movable in the horizontal direction relative to each other, at least one of the frame holding portion 61 and the lifting portion 62 may be configured to be movable. Thus, the lifting portion 62 selectively lifts one chip C from the bottom of the plurality of chips C on the dicing tape T to make it rise.

[0075] The collet 63 is disposed above the frame holding portion 61 , holds one chip C lifted up by the lifting portion 62 from above, and transports the held chip C between the pickup area 60 a and the arrangement area 60 b .

[0076] The arrangement region 60 b is provided with a carrier holding portion 64 , a power supply portion 65 , a static elimination portion 66 , and an alignment mechanism 67 .

[0077] The carrier holding portion 64 has a holding surface for holding the electrostatic carrier Cw on its upper surface, and holds the electrostatic carrier Cw conveyed by the conveying device 50 in a state where the insulating layer 2 serving as the adsorption surface for adsorbing the chip C faces upward.

[0078] In one example, the power supply unit 65 includes: a power supply pin 65a, which is arranged below the carrier holding unit 64 and contacts the back side of the electrostatic carrier Cw on the carrier holding unit 64, that is, the main body 1 to apply voltage; a power supply source 65b, which supplies power to the power supply pin 65a; and a ground line 65c. In the chip placement device 60, the chip C is adsorbed and held on the adsorption surface of the electrostatic carrier Cw by using the Coulomb force generated by supplying power from the power supply pin 65a to the main body 1. In addition, the details of the adsorption principle of the electrostatic carrier Cw adsorbing the chip C will be described later.

[0079] The arrangement of the power supply unit 65 is not limited thereto, and the power supply unit 65 may be arranged outside the carrier holding unit 64, for example, on the side or above, as long as a voltage can be appropriately applied to the electrostatic carrier Cw.

[0080] In addition, in the present embodiment, the case where the power supply unit 65 includes one power supply pin 65 a is described as an example, but the power supply unit 65 may include a plurality of power supply pins 65 a .

[0081] In one example, the static eliminating unit 66 has a grounding line 66 b disposed above the carrier holding unit 64 and facing a holding surface holding the electrostatic carrier Cw, for performing static elimination (grounding) of the chip C held on the electrostatic carrier Cw of the carrier holding unit 64 .

[0082] In one example, the static eliminating unit 66 is configured to be movable above the carrier holding unit 64 and to be able to contact and ground the chip C disposed at an arbitrary position on the static carrier Cw.

[0083] The arrangement and structure of the static eliminating unit 66 are not limited thereto, and the static eliminating unit 66 may be arranged at any location as long as it can appropriately eliminate static electricity from the chip C.

[0084] For example, the static elimination unit 66 may be Fig. 9 As shown, the collet 63 is configured such that a grounding wire 66b is embedded in the collet 63. In other words, the collet 63 for holding and conveying the chip C and the static eliminating section 66 for grounding the chip C may be integrally configured.

[0085] In addition, for example, the static elimination unit 66 may also be Fig.10 The structure shown covers the entire surface of the electrostatic carrier Cw on the carrier holding portion 64, and is configured to be able to simultaneously perform static elimination (grounding) of a plurality of chips C on the electrostatic carrier Cw.

[0086] In addition, for example, the static elimination portion 66 may be formed by the collet 63 by forming the pad portion of the collet 63 for holding and conveying the chip C with a conductor and combining the collet 63 with the grounding wire 66b. In this case, it is desirable that the pad member of the collet 63 is formed of a material having a resistance value (for example, 10e6Ω to 10e9Ω) that can properly eliminate the static electricity of the chip C. In the case where the resistance value is too low (less than 10e6Ω), the static elimination of the chip C may not be properly performed. On the other hand, in the case where the resistance value is too high (more than 10e9Ω), abnormal discharge may occur when the chip C is held (de-electrified) and damage may be caused to the chip C and the collet 63 that are the objects to be held.

[0087] The alignment mechanism 67 performs alignment between the electrostatic carrier Cw held by the carrier holding portion 64 and the chip C held by the collet 63. More specifically, the alignment is performed between one chip C held by the collet 63 and the adsorption holding position of the adsorption holding chip C on the adsorption surface of the electrostatic carrier Cw. In addition, the adsorption holding position of the adsorption holding chip C on the adsorption surface of the electrostatic carrier Cw can be determined, for example, based on the through hole 2a formed in the insulating layer 2, or can also be determined based on a process acquired in advance.

[0088] Furthermore, the alignment mechanism 67 can detect whether the chip C is properly arranged on the suction surface of the electrostatic bearing member Cw. More specifically, the position of the chip C actually arranged on the suction surface of the electrostatic bearing member Cw can be aligned with the set position of the suction and holding chip C in the suction surface of the electrostatic bearing member Cw.

[0089] As an example, the alignment mechanism 67 includes a camera, a sensor, and the like.

[0090] In addition, Figure 8 In the example shown, the structure in which the chip C on the dicing tape T is transferred to the electrostatic carrier Cw in a single piece is described as an example, but the chip placement device 60 may be configured to simultaneously transfer a plurality of chips C to the electrostatic carrier Cw. In this case, a plurality of collets 63 may be arranged above the frame holding portion 61, or a chip transfer mechanism capable of picking up a plurality of chips C simultaneously may be provided.

[0091] The protective film removal device 70 removes the protective film P formed on the surface side of the chip C. The structure of the protective film removal device 70 is arbitrary, and in one example, the protective film removal device 70 can remove the protective film P formed on the chip C by supplying a chemical solution for etching (wet etching process) and irradiating the protective film P with a laser beam (ablation process).

[0092] In the surface modification device 80, oxygen or nitrogen as a processing gas is excited to be plasma-formed and ionized, for example, in a reduced pressure atmosphere. The oxygen ions or nitrogen ions are irradiated onto the surface (device surface) of the device layer D exposed by removing the protective film P, and the device surface is plasma-treated to be modified.

[0093] In the surface hydrophilizing device 90, pure water is supplied onto the electrostatic carrier Cw, more specifically onto the surface of the device subjected to surface modification, while rotating the electrostatic carrier Cw held on a rotating holding plate, for example. The supplied pure water diffuses on the device surface to hydrophilize the device surface.

[0094] In the pretreatment device 100, the surface of the wafer W (the surface of the device layer Dw) before the chip C is bonded is pretreated for bonding with the chip C, such as surface activation and hydrophilization. The pretreatment method of the surface of the wafer W is, for example, the same as the pretreatment method performed on the chip C in the surface modification device 80 and the surface hydrophilization device 90.

[0095] In addition, in the processing system 10 involved in the present embodiment, the pretreatment for the chip C and the pretreatment for the wafer W are performed in different devices as described above, but the pretreatment for the chip C and the pretreatment for the wafer W can also be performed in the same processing device. That is, for example, the pretreatment for the wafer W can also be performed in the surface modification device 80 and the surface hydrophilization device 90.

[0096] In addition, in the processing system 10 involved in the present embodiment, only one pretreatment device 100 for pretreatment of the wafer W is configured, and the surface activation treatment and hydrophilization treatment are performed in the pretreatment device 100, but these surface activation treatments and hydrophilization treatments can also be performed in different devices. That is, in the processing system 10, a surface modification device (not shown) and a surface hydrophilization device (not shown) for pretreatment of the wafer W can also be configured to replace the pretreatment device 100. Similarly, the surface modification device 80 and the surface hydrophilization device 90 for pretreatment of the chip C can also be configured as a whole.

[0097] In the bonding apparatus 110 , a plurality of chips C held by suction on the electrostatic carrier Cw are bonded to the mounting surface of the wafer W to be mounted on.

[0098] like Fig.11 As shown, the bonding device 110 is provided with a carrier holding portion 111 , an air supply portion 112 , a wafer holding portion 113 , and an alignment mechanism 114 .

[0099] The carrier holding portion 111 serving as a second carrier holding portion has a holding surface for holding an electrostatic carrier Cw on its upper surface, and holds the electrostatic carrier Cw, which is transported by the transport device 50 and for adsorbing and holding the chip C subjected to the above-mentioned removal of the protective film P, surface modification treatment and surface hydrophilization treatment, with the chip C facing upward.

[0100] The air supply unit 112 has a supply port 112a formed on the holding surface of the carrier holding unit 111, and an air supply source 112b connected to the end portion on the opposite side of the supply port 112a. The air supply unit 112 supplies air from the lower side of the carrier holding unit 111 through the through hole 1a and the through hole 2a toward the back side Cb side of the chip C held by the electrostatic carrier Cw. In the bonding device 110, by supplying air to the back side Cb side of the chip C in this way, the chip C is lifted from the adsorption surface of the electrostatic carrier Cw, thereby detaching the chip C from the adsorption surface of the electrostatic carrier Cw. In addition, the details of the detachment method of the chip C will be described later.

[0101] The wafer holding part 113 as a substrate holding part has a holding surface on the lower surface for holding the wafer W as the mounting target of the chip C, and holds the wafer W transported by the transport device 50 in a state where the mounting surface on which the chip C is mounted faces downward. In addition, in one example, the wafer holding part 113 is configured to be movable in the horizontal direction, the vertical direction, and around the horizontal axis, and can flip the upper and lower surfaces of the held wafer W, and can move the held wafer W relative to the electrostatic bearing member Cw.

[0102] The alignment mechanism 114 performs alignment between the electrostatic carrier Cw held by the carrier holding part 111 and the wafer W held by the wafer holding part 113. More specifically, the alignment is performed between the plurality of chips C held by adsorption on the electrostatic carrier Cw and the bonding positions of the bonding chips C on the mounting surface of the wafer W, that is, the positions corresponding to the device layer Dw after being cut into pieces on the surface Wa of the wafer W. As an example, the alignment mechanism 114 includes a camera, a sensor, and the like.

[0103] In the example shown in the figure, the carrier holding part 111 is fixedly arranged on the bottom surface side of the bonding device 110, and the wafer holding part 113 is arranged above the bonding device 110, but the carrier holding part 111 may be fixedly arranged on the top surface side of the bonding device 110, and the wafer holding part 113 may be arranged below the bonding device 110. In other words, in the bonding device 110, the carrier holding part 111 may hold the plurality of chips C held by adsorption to the adsorption surface of the electrostatic carrier Cw in a state facing downward, and the wafer holding part 113 may hold the wafer W in a state where the mounting surface of the chips C is mounted faces upward.

[0104] The above processing system 10 is provided with a control device 120. The control device 120 is, for example, a computer having a CPU, a memory, etc., and has a program storage unit (not shown). The program storage unit stores a program for controlling the chip manufacturing process on the wafer in the processing system 10. In addition, the above program can also be recorded in a computer-readable storage medium H, and installed from the storage medium H to the control device 120. In addition, the above storage medium H can be transient or non-transient.

[0105] The processing system 10 according to one embodiment is configured as described above, but other processing devices may be further arranged in the processing system 10 according to the purpose, and some processing devices may be arranged outside the processing system 10 according to the purpose.

[0106] Specifically, for example, the processing system 10 may be further provided with various devices for thinning the silicon layer Si formed on the back surface Cb side of the chip C.

[0107] In addition, for example, the pretreatment device 100 for pretreatment of the wafer W may be omitted from the processing system 10, and the wafer W that has been pretreated (surface activation treatment and hydrophilization treatment) outside the processing system 10 may be moved into the processing system 10 via a front-opening wafer transfer box Fw.

[0108] Next, a chip manufacturing process on a wafer performed in the processing system 10 configured as described above will be described. Fig.12 Flowchart showing the main steps of the chip manufacturing process on a wafer. Fig.13 This is an explanatory diagram schematically showing a side view of a part of the process of manufacturing chips on a wafer.

[0109] First, the front-opening FOUPs Ff, Fc, and Fw respectively storing a plurality of dicing frames F, electrostatic carriers Cw, and wafers W are placed on the front-opening FOUP placement table 20 of the loading / unloading station 11 .

[0110] like Fig.13 As shown in (a) of FIG. 1 , a dicing tape T to which a plurality of chips C are attached is fixed to a dicing frame F housed in a front-opening FOUP Ff. The silicon layers Si on the back surfaces Cb of the plurality of chips C are attached to the dicing tape T.

[0111] Next, the dicing frame F in the front-opening FOUP Ff is taken out by the transfer device 30 and transferred to the transfer device 40. The dicing frame F transferred to the transfer device 40 is transferred to the chip placement device 60 by the transfer device 50. In addition, at the same time or thereafter, the electrostatic bearing member Cw in the front-opening FOUP Fc is transferred to the chip placement device 60.

[0112] In the chip arrangement device 60, the chip C with the back surface Cb side attached to the adhesive surface of the dicing tape T is as follows. Fig.13 As shown in (b), the back surface Cb is arranged at a position corresponding to the holding position within the adsorption surface of the electrostatic carrier Cw so as to face the lower side, and adsorption and holding are performed ( Fig.12 Step St1).

[0113] Next, an example of the operation of arranging the chip C with respect to the electrostatic bearing member Cw in the chip arranging device 60 will be described (see also FIG. 1 ). Figure 8 ).

[0114] First, the frame holding portion 61 and the lifting portion 62 are relatively moved in the horizontal direction, and the lifting portion 62 is moved below one chip C among the plurality of chips C attached to the dicing tape T. Then, the lifting portion 62 is used to selectively lift one chip C from below (back surface Cb side) to raise it.

[0115] Next, the top surface Ca of one chip C that has been lifted up is held from above by the collet 63. At this time, since the protective film P is formed on the top surface Ca side of the chip C, the device layer D is not damaged by holding, for example, suction holding, by the collet 63.

[0116] Next, the collet 63 holding the chip C is moved to a position corresponding to an adsorption holding position in the electrostatic carrier Cw on the carrier holding portion 64, the chip C is arranged (mounted) on the adsorption surface of the electrostatic carrier Cw, and the collet 63 releases the holding, such as adsorption, of the chip C.

[0117] Next, the alignment mechanism 67 is used to detect whether the chip C is properly arranged at one of the suction holding positions. If the result of the detection is that the chip C is properly arranged, the arrangement operation of the next chip C on the dicing tape T is started. On the other hand, if it is determined that the chip C is not properly arranged, the collet 63 re-holds the arranged chip C and re-arranges the chip C to one of the suction holding positions.

[0118] Finally, the power supply pin 65a of the power supply unit 65 is brought into contact with the main body 1 of the electrostatic carrier Cw, and a voltage is applied to the electrostatic carrier Cw via the power supply pin 65a. The chip C is attracted and held on the attraction surface of the electrostatic carrier Cw by the generated Coulomb force.

[0119] The electrostatic attraction of the chip C by the electrostatic bearing member Cw will be described in more detail.

[0120] When all the chips C are arranged at the suction holding position of the electrostatic carrier Cw by the collet 63, as shown in FIG. Fig.14As shown in (a), a voltage (positive (+) charge in the example shown in the figure) is applied to the electrostatic carrier Cw via the power supply pin 65a, so that the main body 1 of the electrostatic carrier Cw is positively charged (+).

[0121] When the main body 1 is positively charged (+), Fig.14 As shown in (b), charges of opposite polarity (i.e., negative (-)) to the charges accumulated in the main body 1 are accumulated on the back side Cb of the chip C via the insulating layer 2, and charges of the same polarity (i.e., positive (+)) as the charges accumulated in the main body 1 are accumulated on the surface Ca side of the chip C.

[0122] Next, the grounding wire of the static eliminating portion 66 is brought into contact with the surface Ca side (the side facing the back surface Cb as the holding surface) of the chip C. Fig.14 As shown in (c), negative charges attracted to the positive charges of the main body 1 remain in the chip C, while the positive charges on the surface Ca side are removed (grounded).

[0123] Thereafter, when the static eliminating unit 66 is retracted, a potential difference is generated between the main body 1 of the static carrier Cw and the chip C via the insulating layer 2, generating an electrostatic force that attracts each other, and the chip C is attracted to the attraction surface of the static carrier Cw by the electrostatic force.

[0124] As described above, in the technology disclosed in the present invention, the main body 1 of the electrostatic carrier Cw functions as a unipolar electrode in a simulated manner, and the chip C can be adsorbed and held on the adsorption surface via the insulating layer 2 without forming an electrode wiring pattern inside the main body 1. That is, the insulating layer 2 is used to maintain the charge accumulated in the main body 1 by insulating the charge applied to the main body 1.

[0125] In addition, in the electrostatic carrier Cw according to the technology disclosed herein, the insulating layer 2 is formed of a flexible material having a small elastic modulus.

[0126] After the chip C is placed on the electrostatic carrier Cw and before the chip C is held by electrostatic force, a gap is formed between the silicon layer Si of the chip C and the insulating layer 2 of the electrostatic carrier Cw. Due to the softness of the insulating layer 2, when the chip C is held by electrostatic force in the electrostatic carrier Cw, the force of the chip C being held by the insulating layer 2 causes air to escape from between the silicon layer Si of the chip C and the insulating layer 2 that serves as the holding surface, thereby forming a simulated vacuum state between the chip C and the insulating layer 2.

[0127] Thus, in addition to electrostatic attraction due to electrostatic force, vacuum attraction force due to a simulated vacuum state is also exerted between the electrostatic carrier Cw and the chip C, thereby achieving a strong holding state using both electrostatic attraction force and vacuum attraction force.

[0128] The electrostatic adsorption of the chip C by the electrostatic bearing member Cw is performed as described above.

[0129] Furthermore, the operation of placing the chip C on the electrostatic carrier Cw may be performed successively one by one on each of the plurality of chips C attached to the dicing tape T, or the plurality of chips C on the dicing tape T may be placed on the electrostatic carrier Cw simultaneously.

[0130] In addition, the timing of applying voltage to the main body 1 and the timing of grounding the chip C are not limited to the above-mentioned examples. That is, for example, the voltage may be applied to the main body 1 before the chip C is arranged on the adsorption surface (in a state where there is no chip C on the electrostatic carrier Cw), or Fig.14 As shown, voltage is applied after chip C is arranged on the adsorption surface (after all chips C are arranged on the electrostatic carrier Cw). In addition, in the case where multiple chips C are arranged on the electrostatic carrier Cw at the same time, voltage can also be applied to the main body 1 at the same time as chip C is arranged on the adsorption surface. In addition, the de-electrification (grounding) of the chip C on the electrostatic carrier Cw can be performed at the same time as chip C is arranged on the adsorption surface and voltage is applied, or it can be performed after chip C is arranged on the adsorption surface and voltage is applied to adsorb and hold the chip C.

[0131] However, when voltage is applied to the main body 1 without the chip C being arranged on the adsorption surface, the generated electrostatic force may attract and attach particles to the adsorption surface. In view of this, it is preferred that voltage is applied to the main body 1 after the chip C is arranged on the adsorption surface, or at the same time as the chip C is arranged on the adsorption surface. More preferably, voltage is applied to the main body 1 after all the chips C are arranged on the electrostatic carrier Cw.

[0132] In addition, in the chip configuration device 60, as described above, the alignment mechanism 67 may be used to confirm whether the chip C is properly configured and to reconfigure the chip C. However, for example, in the case where the chip C is bonded to the wafer W in a monolithic manner in the bonding device 110 described later, high alignment accuracy is not required in the chip configuration device 60, as long as at least the chips C do not interfere with each other. That is, in the case where the chip C is bonded in a monolithic manner in the bonding device 110, as long as the chip C can be aligned with the mounting position on the wafer W with high accuracy and bonded in the bonding process described later in the bonding device 110, alignment accuracy in the chip configuration device 60 is not required.

[0133] When the chip C is placed on the electrostatic carrier Cw, the electrostatic carrier Cw holding the chip C by adsorption is then transported to the protective film removing device 70 by the transport device 50. Fig.13As shown in (c), the protective film P formed on the device layer D of the chip C is removed. Fig.12 Step St2).

[0134] Here, when a conductive liquid (for example, an etching solution in the protective film removal device 70) is used to remove the protective film P, as described above, the charge accumulated on the electrostatic carrier Cw or the chip C may leak through the conductive liquid, causing the electrostatic adsorption force of the chip C to the electrostatic carrier Cw to be lost.

[0135] In this regard, in the electrostatic carrier Cw involved in the technology disclosed in the present invention, as described above, in addition to the electrostatic adsorption force, a vacuum adsorption force is generated between the electrostatic carrier Cw and the chip C to adsorb and hold the chip. Therefore, in the electrostatic carrier Cw involved in the technology disclosed in the present invention, even if the electrostatic adsorption force between the electrostatic carrier Cw and the chip C is lost, the adsorption and holding of the chip C can be maintained by the vacuum adsorption force.

[0136] This effect also applies to the surface modification treatment and hydrophilization treatment described later.

[0137] In addition, when the protective film P is removed while the chip C is adhered to the dicing tape T as in the previous method, particularly because the dicing tape T holds the chip C with the adhesive surface facing upward, there is a problem as described above that the dicing tape T is damaged and the chip C cannot be maintained by the dicing tape T and cannot be reused.

[0138] In this regard, according to the chip-on-wafer manufacturing process involved in the technology disclosed in the present invention, the protective film P of the chip C held on the electrostatic carrier Cw is removed instead of removing the protective film P of the chip C held on the dicing tape T. In the present embodiment, the electrostatic carrier Cw is composed of a chemically resistant main body 1 of silicon, aluminum, etc. and a chemically resistant insulating layer 2 of a polyimide film, a back grinding tape, etc. Therefore, the loss of the electrostatic carrier Cw can be suppressed compared to the loss of the dicing tape T when the protective film P is removed, and the dicing tape T fixed to the dicing frame F can be reused, and the electrostatic carrier Cw can also be reused.

[0139] This effect also applies to the surface modification treatment and hydrophilization treatment described later.

[0140] Next, the electrostatic carrier Cw holding the chip C from which the protective film P has been removed is transported to the surface modification device 80 by the transport device 50. In the surface modification device 80, as shown in FIG. Fig.13 As shown in (d), the device surface exposed on the surface Ca side of the chip C is modified by plasma treatment ( Fig.12 Step St3).

[0141] Next, the electrostatic carrier Cw holding the chip C with the device surface modified is transported to the surface hydrophilization device 90 by the transport device 50. In the surface hydrophilization device 90, Fig.13 As shown in (e), hydroxyl groups (silanol groups) are attached to the device surface of the chip C after the surface modification device 80 is modified to make the device surface hydrophilic. In addition, the electrostatic bearing member Cw and the chip C ( Fig.12 Step St4).

[0142] In addition, after, at the same time as, or before the surface modification treatment of the chip C in the surface modification device 80 in step St3 and the hydrophilization treatment of the chip C in the surface hydrophilization device 90 in step St4, the wafer W in the front-opening wafer pod Fw is transported to the pre-treatment device 100. In the pre-treatment device 100, the device layer Dw on the surface Wa side of the wafer W is subjected to surface modification treatment and hydrophilization treatment in the same manner as the surface modification treatment and hydrophilization treatment of the chip C ( Fig.12 Step St3-2 and Step St4-2).

[0143] Next, the electrostatic carrier Cw holding the chip C with the device surface hydrophilized is transported to the bonding apparatus 110 by the transport apparatus 50. Simultaneously or thereafter, the wafer W with the surface Wa side (device layer Dw) hydrophilized is transported to the bonding apparatus 110.

[0144] In the joining device 110, as Fig.13 As shown in (f), the plurality of chips C on the electrostatic carrier Cw are overlapped with the mounting surface (pre-processed surface Wa) of the wafer W as the mounting target of the chips C, and pressed from the top and bottom directions, thereby bonding the chips C and the wafer W (so-called fusion bonding) ( Fig.12 Step St5).

[0145] Next, an example of a bonding operation of bonding a chip C to a wafer W in the bonding apparatus 110 will be described (see also FIG. Fig.11 ).

[0146] First, the electrostatic carrier Cw for holding the plurality of chips C by suction is placed on the carrier holding portion 111 with the suction surface facing upward, that is, with the plurality of chips C facing upward.

[0147] Next, the wafer holding part 113 holding the wafer W is arranged above the electrostatic bearing member Cw. The wafer W is held in the wafer holding part 113 in a state where the surface Wa of the wafer W, which is the mounting surface for mounting the chip C, which has been pre-processed, faces downward. In addition, at this time, the wafer W held in the wafer holding part 113 is aligned by the alignment mechanism 114 so that the device layer Dw on the mounting surface of the wafer W after being cut into pieces corresponds to the positions of the multiple chips C on the electrostatic bearing member Cw. The high-precision alignment and reconfiguration of the chips C in the chip configuration device 60 relative to the electrostatic bearing member Cw are performed for the alignment of the device layer Dw on the wafer W and the chips C on the electrostatic bearing member Cw.

[0148] Next, the chip C held on the electrostatic carrier Cw of the carrier holding part 111 and the device layer Dw on the wafer W held on the wafer holding part 113 are pressed from the top and bottom to bond the chip C to the device layer Dw.

[0149] At this time, since the device layer Dw of the wafer W and the device surface of each chip C on the electrostatic carrier Cw are modified, first, a van der Waals force (intermolecular force) is generated between the device layer Dw and the device surface of the chip C, and the device layer Dw of the wafer W is bonded to the chip C on the electrostatic carrier Cw. Furthermore, since the device layer Dw and the device surface of each chip C are hydrophilized, the hydrophilic groups between the device layer Dw and the chip C are hydrogen bonded (intermolecular force), and the device layer Dw of the wafer W is firmly bonded to the chip C on the electrostatic carrier Cw.

[0150] When the device layer Dw of the wafer W is joined to the chip C on the electrostatic carrier Cw, pressure generated by air is applied to the back side Cb of the chip C on the electrostatic carrier Cw from the supply port 112a of the air supply unit 112 via the through holes 1a and 2a, thereby reducing the adhesion between the chip C on the adsorption surface of the electrostatic carrier Cw and the insulating layer 2.

[0151] More specifically, when air is supplied to the back side Cb of the chip C, the through hole 2a formed in the insulating layer 2 is blocked by the chip C. Fig.15 As shown, the insulating layer 2 expands with the central part of the through hole 1a formed in the main body 1 as the apex just below the chip C. In this way, the chip C and the insulating layer 2 are still closely attached at the center of the chip C corresponding to the central part of the through hole 1a, and the chip C floats from the insulating layer 2 at the peripheral part of the chip C corresponding to the peripheral part of the through hole 1a, thereby reducing the adhesion between the chip C and the insulating layer 2, more specifically, it becomes lower than the bonding force between the chip C and the device layer Dw of the wafer W.

[0152] In addition, even in the case where the through hole 2a is not formed in the insulating layer 2 as described above, Fig.16 As shown, by supplying air to the back surface Cb side of the chip C through the through hole 1 a , the insulating layer 2 can be expanded to reduce the adhesion between the chip C and the insulating layer 2 .

[0153] In addition, according to the technology involved in the present disclosure, as described above, both the electrostatic adsorption force and the vacuum adsorption force act between the chip C and the insulating layer 2. Therefore, even in the case where the through hole 2a of the insulating layer 2 and the through hole 1a of the main body 1 are formed with the same diameter as described above, the chip C is prevented from flying due to the destruction of the vacuum adsorption between the chip C and the insulating layer 2 (blowing air from the through hole 1a to the bottom of the chip C) when air is supplied to reduce the adhesion between the chip C and the insulating layer 2.

[0154] Next, the wafer holding unit 113 holding the wafer W is raised. As a result, the adhesion between the chip C and the insulating layer 2 is reduced, so that the chip C is completely separated from the insulating layer 2 .

[0155] Finally, the wafer holding part 113 is rotated about the horizontal axis to reverse the front and back sides of the wafer W. In other words, the mounting surface of the wafer W to which the plurality of chips C are bonded faces upward.

[0156] The bonding operation of bonding the chip C to the wafer W according to one embodiment is performed as described above.

[0157] In addition, as described above, the electrostatic carrier Cw that absorbs and holds the plurality of chips C may be arranged such that the absorption surface is on the lower side, that is, the plurality of chips C are held in a state facing downward, and the wafer W is arranged below the electrostatic carrier Cw. In other words, the arrangement of the electrostatic carrier Cw and the wafer W in the vertical direction is not limited to the example shown in the figure, and they may be held and transported in the reverse direction.

[0158] When a plurality of chips C are bonded to the device layer Dw of the wafer W, the wafer W with the chips C mounted thereon is then transferred by the transfer device 50 to the transfer device 40 , and then further transferred by the transfer device 30 to the front-opening wafer pod Fw on the front-opening wafer pod mounting table 20 .

[0159] Similarly, the electrostatic carrier Cw after the chip C is released is transported by the transport device 50 to the transport device 40, and then further transported by the transport device 30 to the front-opening FOUP Fc on the FOUP loading table 20. In this way, a series of chip-on-wafer manufacturing processes in the processing system 10 are completed.

[0160] Furthermore, the front-opening FOUP for collecting the dicing frame F, the electrostatic carrier Cw, and the wafer W does not necessarily need to be the same front-opening FOUP as the front-opening FOUP for storing the dicing frame F and the like when it is carried in. That is, for example, the front-opening FOUP for storing the dicing frame F and the like may be used to carry out other components, or a new front-opening FOUP for carrying out the dicing frame and the like may be carried in to the processing system 10.

[0161] According to the above embodiment, the electrostatic carrier Cw can be formed with a simple structure in which only the insulating layer 2 is formed on the surface of the conductive main body 1, and the electrostatic carrier Cw becomes a relay member for relaying the chip C from the dicing tape T to the wafer W during a series of chip-on-wafer manufacturing processes.

[0162] Moreover, there is no need to form an electrode wiring pattern inside the conductive main body as in conventional electrostatic carriers, so the freedom in forming through holes for detaching the chip C is greatly improved, and the work and cost associated with the structure of the electrostatic carrier Cw can be greatly reduced.

[0163] More specifically, in the structure of the conventional electrostatic carrier (electrostatic holding mechanism), the through hole required for releasing the held object needs to be formed directly below the held object and arranged away from the wiring pattern of the embedded electrode part for adsorbing and holding the held object. In addition, it is necessary to change the arrangement of the through hole or the wiring pattern according to the number and arrangement of the held objects, which requires a lot of effort and cost.

[0164] In this regard, in the electrostatic carrier Cw according to the technology disclosed herein, it is not necessary to form an electrode wiring pattern inside the conductive main body portion, and therefore the number and arrangement of the through holes can be arbitrarily determined.

[0165] In addition, according to the electrostatic carrier Cw involved in the technology disclosed in the present invention, the insulating layer 2 formed on the surface of the main body 1 is made of a flexible material with a low elastic modulus. As a result, air is exhausted from between the insulating layer 2 and the chip C, and in addition to the electrostatic adsorption force generated by applying a voltage to the main body 1, a vacuum adsorption force is also simulated, so that the chip C can be adsorbed and held more appropriately.

[0166] Furthermore, since vacuum adsorption force can be generated in addition to electrostatic adsorption force, the holding force of chip C can be properly maintained even if conductive liquid is supplied to electrostatic carrier Cw and the electrostatic adsorption force between electrostatic carrier Cw and chip C is lost when removing the protective film P, for example.

[0167] Furthermore, according to the electrostatic carrier Cw involved in this embodiment, by forming the insulating layer 2 formed on the surface of the main body 1 from a flexible material with a low elastic modulus as described above, the insulating layer 2 can be easily expanded by the supply of air when the chip C is detached, thereby appropriately reducing the adsorption force between the chip C and the insulating layer 2.

[0168] In addition, as described above, the electrostatic carrier Cw according to the present embodiment is configured to have a diameter substantially the same as that of the wafer W to be mounted on the chip C. Thus, the electrostatic carrier Cw can be transported and processed using the same transport device and processing device as the wafer W, and there is no need to newly provide a device for transporting and processing the electrostatic carrier Cw.

[0169] In addition, in the bonding device 110 involved in the above-mentioned embodiment, multiple chips C are simultaneously mounted on the wafer W by making the electrostatic carrier Cw on the carrier holding part 111 and the wafer W on the wafer holding part 113 face each other and contact each other, but the installation of the chip C on the wafer W can also be performed in a single-chip manner.

[0170] like Fig.17 As shown, in another embodiment of the bonding device 200 for mounting the chip C on the wafer W in a monolithic manner, a separation area 200a, a bonding area 200b, and a handover area 200c are formed. In the separation area 200a, the chip C is picked up from the electrostatic carrier Cw. In the bonding area 200b, the chip C is bonded to the wafer W. In the handover area 200c, the chip C is handed over between the separation area 200a and the bonding area 200b.

[0171] The detachment region 200 a is provided with a carrier holding portion 201 as a second carrier holding portion, an air supply portion 202 , and a first collet 203 .

[0172] The carrier holding part 201 and the air supply part 202 have substantially the same structure as the carrier holding part 111 and the air supply part 112 of the bonding apparatus 110 according to the above-mentioned embodiment. The air supply part 202 has a supply port 202a and an air supply source 202b, and supplies air toward the back surface Cb side of the chip C held by the electrostatic carrier Cw through the through hole 1a and the through hole 2a.

[0173] In the bonding apparatus 200 according to another embodiment, air from the air supply source 202b can be supplied to the chips C held by adsorption on the electrostatic carrier Cw, in other words, to the plurality of through holes 1a formed in the main body 1. In this case, it is desirable to provide control valves (not shown) in the air supply section 202 for supplying air to the chips C independently.

[0174] In addition, in the bonding apparatus 200 according to other embodiments, it is sufficient to be configured so that air can be supplied from the air supply source 202b to each of the chips C held by adsorption on the electrostatic carrier Cw. Fig.17 As shown, a common air supply source 202b is connected to a plurality of supply ports 202a, or it may be configured as follows Fig.18 In the figure, one air supply source 202b is connected to each of the plurality of supply ports 202a. In other words, any number of air supply sources 202b may be provided in the bonding apparatus 200.

[0175] The first collet 203 is disposed above the carrier holding portion 201, holds the chip C whose outer periphery floats due to the reduced adhesion between the chip C and the insulating layer 2 by the air supply from the air supply portion 202, and separates the chip C from the electrostatic carrier Cw, and transports the held chip C between the separation area 200a and the delivery area 200c. In one example, the first collet 203 is configured to be rotatable around a horizontal axis, and can reverse the upper and lower surfaces of the held chip C as shown in the figure.

[0176] As described above, the upper surface of the chip C held by the first collet 203 in the bonding apparatus 200 is the device surface where the device layer D is exposed by removing the protective film P. Therefore, the first collet 203 needs to hold the chip C so as not to damage the exposed device surface.

[0177] Specifically, as the first collet 203 , it is desirable to use a non-contact holding disk that can hold the chip C in a non-contact manner from above by utilizing the Bernoulli effect or the ultrasonic squeezing effect, for example.

[0178] Alternatively, the first collet 203 may be configured to hold the chip C by clamping the side surface thereof floated by the supply of air, for example, instead of holding the upper surface (device surface) of the chip C.

[0179] The bonding region 200 b is provided with a wafer holding portion 204 , a second collet 205 , and an alignment mechanism 206 .

[0180] The wafer holding part 204 as a substrate holding part has a holding surface for holding the wafer W on its upper surface, and holds the wafer W conveyed by the conveying device 50 with the surface on which the device layer Dw is formed, which is the mounting surface of the chip C, facing upward.

[0181] The second collet 205 is disposed above the wafer holding portion 204 , holds the chip C held by the first collet 203 from above, and transfers the held chip C between the bonding area 200 b and the delivery area 200 c .

[0182] In one example, the second collet 205 may be configured to be rotatable about a horizontal axis instead of the first collet 203. In this case, the second collet 205 holds the chip C held by the first collet 203 from below in the handover region 200c, and after turning the upper and lower surfaces of the chip C, the chip C is joined to the wafer W in the joining region 200b.

[0183] In the bonding apparatus 200, the device layer is not exposed on the back surface Cb side of the chip C held by the second collet 205, unlike the front surface Ca side held by the first collet 203. Therefore, the second collet 205 does not necessarily need to be composed of a non-contact holding plate or the like as the first collet 203.

[0184] In one example, the alignment mechanism 206 has the same structure as the alignment mechanism 67 of the chip arrangement device 60 . That is, the alignment mechanism 206 includes, for example, a camera and a sensor, and performs alignment between the wafer W held by the wafer holding unit 204 and the chip C held by the second collet 205 .

[0185] The bonding apparatus 200 according to the other embodiment is configured as described above. Next, an example of a bonding method of bonding the chip C to the wafer W using the bonding apparatus 200 will be described.

[0186] When bonding chips C to wafer W in bonding apparatus 200, first, electrostatic carrier Cw for adsorbing and holding multiple chips C is placed on carrier holding section 201 with multiple chips C facing upward. Next, wafer W to be mounted with chips C is placed on wafer holding section 204 with the surface on which device layer Dw is formed facing upward.

[0187] Next, air is selectively supplied to the through hole 1 a corresponding to the one chip C to be separated, and the insulating layer 2 is expanded, thereby pushing up the one chip C from below and making it float.

[0188] Next, the first collet 203 holds and lifts the floating chip C without damaging the device surface. The first collet 203 may hold the chip C before or while the chip C is floating by air.

[0189] Next, the first collet 203 is rotated about the horizontal axis to reverse the front and back sides of the chip C. In other words, the back side Cb (the side facing the device surface) of the chip C held by the first collet 203 is directed upward.

[0190] Next, the second collet 205 holds the back surface Cb of the chip C held by the first collet 203 from above, and the first collet 203 releases the holding of the front surface Ca of the chip C. In other words, the chip C is switched from the first collet 203 to the second collet 205 .

[0191] Next, the second collet 205 holding the chip C is moved to a position corresponding to one device layer Dw on the mounting surface of the wafer W. The second collet 205 and the device layer Dw are appropriately aligned using the alignment mechanism 206 .

[0192] Finally, the device surface of the chip C held by the second collet 205 and one device layer Dw of the wafer W are pressed from the top and bottom directions to bond the chip C to the device layer Dw.

[0193] The bonding operation of bonding the chips C to the wafer W according to other embodiments is performed as described above. The bonding operation of the chips C is performed independently and continuously on the plurality of chips C held by adsorption on the electrostatic support member Cw.

[0194] In addition, in the above-mentioned example, air is selectively supplied to the through hole 1a corresponding to a chip C to be separated, and only the chip C is lifted up from the bottom to make it float. However, in a case where air cannot be supplied to each through hole 1a independently (for example, a case where a control valve is not provided, etc.), air can be supplied to all the through holes 1a in advance, and all the chips C can be set to a floating state, and the chips C can be picked up sequentially by the first cartridge 203.

[0195] Or, for example, Fig.19 As shown in the carrier holding portion 301 , an air supply unit 310 having only one supply port 311 is provided in common to all the chips C of the plurality of chips C. The supply port 311 is connected to an air supply source 312 .

[0196] In this case, it is desirable that the carrier holding portion 301 and one supply port 311 are relatively movable in the horizontal direction. If the carrier holding portion 301 and the supply port 311 are relatively movable in the horizontal direction, at least one of the carrier holding portion 301 and the supply port 311 may be movable.

[0197] Furthermore, in the carrier holding part 301, air can be supplied from the supply port 311 to the entire lower surface of the electrostatic carrier Cw held on the carrier holding part 301, so that all the chips C held on the electrostatic carrier Cw are separated from the electrostatic carrier Cw at the same time. Alternatively, it is also possible to configure the supply port 311 below one chip C among the multiple chips C by relatively moving the carrier holding part 301 and the supply port 311 in the horizontal direction, so that air is selectively supplied to the one chip C, so that the one chip C is selectively separated from the electrostatic carrier Cw.

[0198] In addition, in the bonding device involved in the above embodiment, the case where the chip C held on the electrostatic carrier Cw is detached by supplying air from the air supply unit to the electrostatic carrier Cw on the carrier holding unit is described as an example. However, the method of detaching the chip C held on the electrostatic carrier Cw is not limited to this. For example, a lifting pin (not shown) can be inserted into the through hole 1a from the bottom of the electrostatic carrier Cw, and the front end of the lifting pin can be freely protruded and immersed relative to the upper surface of the main body 1 of the electrostatic carrier Cw (the upper end of the through hole 1a), to replace the supply of air. In this case, the lifting pin comes into contact with the lower surface of the chip C held on the electrostatic carrier Cw through the through hole 1a, whereby the chip C is lifted and detached from the electrostatic carrier Cw.

[0199] In addition, in the bonding device according to the above embodiment, the chip C is detached by supplying air to the lower surface of the chip C from below the electrostatic carrier Cw or by causing the lift pins to abut against the lower surface of the chip C from below the electrostatic carrier Cw. However, it is also possible to configure such that the chip C can be detached from the electrostatic carrier Cw using only the upper collet (corresponding to the first collet in the above embodiment) without applying force from the lower surface side of the chip C on the electrostatic carrier Cw.

[0200] Specifically, as stress acting on the chip C on the electrostatic carrier Cw, in addition to the pickup by the collet, the centrifugal force accompanying the rotation of the rotating holding disk in the surface modification device 80 and the surface hydrophilization device 90, the stress accompanying the flow of the conductive liquid, or the inertial force accompanying the transportation of the electrostatic carrier Cw are also considered. Among them, the stress accompanying the pickup by the collet acts on the chip C in the up and down direction (vertical direction), and on the other hand, other centrifugal forces, flow forces, and inertial forces are shear forces acting in the horizontal direction. From this point of view, for example, by making the holding force of the electrostatic carrier Cw on the chip C strong in the horizontal direction (relative to the shear stress) and weak in the vertical direction (relative to the tensile force), the chip C can be detached from the electrostatic carrier Cw only by holding it by the collet without the above-mentioned air supply and the lifting by the lifting pin.

[0201] All aspects of the embodiments disclosed herein are illustrative and non-restrictive. The embodiments described above may be omitted, replaced, or changed in various ways without departing from the attached claims and their gist. For example, the constituent elements of the embodiments described above may be combined arbitrarily. The functions and effects of the constituent elements involved in the combination may be obtained according to the arbitrary combination, and other functions and effects may be obtained as clearly defined by a person skilled in the art according to the description of this specification.

[0202] In addition, the effects described in this specification are only illustrative or exemplary, and not limiting. That is, the technology involved in the present disclosure can play other effects that can be clearly understood by those skilled in the art based on the description of this specification, as a supplement or replacement for the above-mentioned effects.

[0203] For example, in the above embodiment, the chip configuration device 60 and the bonding device 110 are configured in the same processing system 10, but these chip configuration devices 60 and bonding devices 110 may also be configured in different processing systems. In other words, a first processing system for configuring the chip C on the dicing frame F on the electrostatic carrier Cw and a second processing system for bonding the chip C on the electrostatic carrier Cw to the wafer W may also be independently constructed.

[0204] Description of Reference Numerals

[0205] 1: main body; 1a: through hole; 2: insulating layer; Cw: electrostatic carrier.

Claims

1. An electrostatic bearing member, comprising: a main body portion having conductivity and having a plurality of through holes in a thickness direction of the main body portion; and An insulating layer is formed on the surface of the main body.

2. The electrostatic carrier according to claim 1, wherein The main body is a conductive substrate made of silicon, aluminum, aluminum alloy, stainless steel or titanium.

3. The electrostatic carrier according to claim 1, wherein The insulating layer is made of a material having an elastic modulus of 2 GPa or less, preferably 0.5 GPa or less.

4. The electrostatic carrier according to claim 3, wherein: The insulating layer is a polyimide film formed on the surface of the main body by spin coating.

5. The electrostatic carrier according to claim 3, wherein: The insulating layer is an insulating film formed by attaching a polyimide film or a back grinding tape to the surface of the main body.

6. The electrostatic carrier according to claim 3, wherein: The insulating layer has a second through hole at a position corresponding to the through hole.

7. The electrostatic carrier according to claim 6, wherein: The second through hole is formed with a smaller diameter than the first through hole.

8. A processing system processes the chip. The processing system comprises a chip arrangement device, which picks up the chip and arranges the chip on the adsorption surface of the electrostatic carrier according to any one of claims 1 to 7. The chip configuration device comprises: A carrier holding portion having a holding surface on an upper surface thereof for holding the electrostatic carrier; an electric power supply portion that supplies electric power to the main body portion of the electrostatic carrier on the carrier holding portion; and The static eliminating unit contacts the chip on the static bearing member and is grounded.

9. The processing system according to claim 8, wherein: The static eliminating portion includes a grounding line in contact with the chip so that the grounding line faces a holding surface of the carrier holding portion that holds the static carrier.

10. The processing system according to claim 8, wherein: A collet is also provided, the collet picking up the chip and transferring the chip to the electrostatic carrier on the carrier holding portion, A ground line in the static eliminating portion that contacts the chip is formed integrally with the collet.

11. The processing system according to claim 8, wherein: The static eliminating unit is composed of a collet that picks up the chip and transfers the chip to the static carrier on the carrier holding unit, and the collet has a resistance value of 10e6Ω to 10e9Ω.

12. The processing system according to claim 8, wherein: A chip transfer mechanism is further provided for holding the plurality of chips at the same time and transferring the plurality of chips to the electrostatic carrier on the carrier holding portion.

13. The processing system of claim 8, wherein: The static eliminator is arranged above the carrier holding portion so as to cover the entire surface of the electrostatic carrier, and the static eliminator is in contact with the plurality of chips on the electrostatic carrier at the same time to ground the plurality of chips at the same time.

14. The processing system according to claim 8, further comprising: a protective film removing device for removing the protective film formed on the device surface of the chip held by adsorption on the electrostatic carrier; and a bonding device for bonding the chip held by adsorption on the electrostatic carrier to a substrate on which the chip is to be mounted, in, The bonding device comprises: a second carrier holding portion that holds the electrostatic carrier; a substrate holding portion that holds the substrate; and An air supply portion supplies air toward the through hole formed in the main body portion of the electrostatic carrier on the second carrier holding portion.

15. The processing system of claim 14, wherein: The bonding device comprises: a first collet that holds and transports the chip on the electrostatic carrier; and A second cartridge is used to transfer the chip to the first cartridge and to transport the chip to the substrate. The first collet is a non-contact holding disk that holds the device surface of the chip in a non-contact manner.

16. The processing system according to claim 8, further comprising: a protective film removing device for removing the protective film formed on the device surface of the chip held by adsorption on the electrostatic carrier; and a bonding device for bonding the chip held by adsorption on the electrostatic carrier to a substrate on which the chip is to be mounted, in, The bonding device comprises: a second carrier holding portion that holds the electrostatic carrier; a substrate holding portion that holds the substrate; and A lifting pin is inserted into the through hole formed in the main body of the electrostatic carrier on the second carrier holding portion.

17. A processing method is a processing method for processing a chip, the processing method comprising: Arranging a plurality of the chips on a holding surface of an electrostatic carrier, wherein the electrostatic carrier has a main body and an insulating layer, wherein the main body has conductivity and has a plurality of through holes in a thickness direction of the main body, and the insulating layer is formed on a surface of the main body; Supplying power to the main body to charge the main body; as well as A ground wire is brought into contact with the chip to generate an electrostatic force between the chip and the main body.

18. The processing method according to claim 17, wherein: Before placing the chip on the electrostatic bearing, power is supplied to the main body. After the chip is disposed on the electrostatic bearing, a ground line is connected to the chip for contact.

19. The processing method according to claim 17, wherein: After the chip is placed on the electrostatic carrier, the power supply and ground lines of the main body are brought into contact with the chip.

20. The processing method according to claim 17, wherein: The ground wires are simultaneously connected to the plurality of chips disposed on the electrostatic bearing member.

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