Hybrid bonding crack structure with air gap

Abstract

A hybrid bonded semiconductor structure includes a first substrate and a second substrate, each substrate having an interface joined in a hybrid bond. Each substrate has a die portion and a crack arrest structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or around a portion of the perimeter of each crack arrest structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unitary void having an air gap across the hybrid bond interface.

Description

Technical Field

[0001] The present invention generally relates to integrated circuit structures having crack stop structures, and more particularly, to hybrid bonded structures having crack stop structures. Background Art

[0002] During the manufacture of integrated circuits on wafers, operations such as cutting substrates and dielectric layers introduce external stresses that may cause microcracks during the manufacturing process. In addition, microcracks may exist or be formed by internally induced stresses. Microcracks can propagate in both the substrate and dielectric layers and cause circuit failures. Although crack stop structures are used to prevent the propagation of microcracks, hybrid bonding structures present additional challenges in preventing the propagation of microcracks, such as at areas where hybrid bonding occurs. Summary of the invention

[0003] According to one embodiment, a hybrid bonded semiconductor structure includes a first substrate and a second substrate, each of the first substrate and the second substrate having an interface joined in hybrid bonding. Each substrate has a die portion and a crack stop structure adjacent to the die portion. One or more voids in the first substrate and the second substrate are formed in or around a portion of the perimeter of each crack stop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form an integral void with an air gap across the hybrid bond interface. The voids prevent microcracks from extending, particularly across the bonding interface, which may lead to catastrophic failure of the semiconductor device.

[0004] In one embodiment, the crack stop structures of the first substrate and the second substrate are joined at the hybrid bonding interface. Extending the crack stop structure to the hybrid bonding interface reduces the likelihood that microcracks can propagate along the interface below the interface and damage the die.

[0005] In one embodiment, at least some of the voids formed in each of the first substrate and the second substrate have different shapes. The voids of different shapes may produce air gaps of different volumes, which may cause the propagation of microcracks.

[0006] In one embodiment, the one or more voids include a plurality of voids, at least some of the plurality of voids having different sizes. The voids of different sizes can aid in alignment, and some voids are effective for microcrack stopping caused by internal stresses, while other sizes are more effective for microcrack stopping caused by external stresses (such as dicing of a wafer).

[0007] In one embodiment, a plurality of voids are arranged continuously, extending across the hybrid bonding interface. The continuous voids reduce the possibility that a crack may bypass a single void.

[0008] In one embodiment, each hybrid bonding interface comprises a back-end-of-line (BEOL) interconnect level, and the integral void is at least partially filled with a dielectric or polysilicon material different from the material of the hybrid bonding interface. Filling the void with a dielectric has a different effect on stopping crack propagation.

[0009] In one embodiment, one or more voids in the first substrate and the second substrate are annular.Various shapes provide different amounts of microcrack stopping.

[0010] In one embodiment, one or more voids in the first substrate and the second substrate are arranged as non-continuous rings. The non-contiguous rings have a continuous plurality of voids to control microcrack propagation.

[0011] In one embodiment, one or more voids in the first substrate and the second substrate are circular. Circular voids can provide a larger surface area to prevent the propagation of microcracks.

[0012] In one embodiment, one or more voids are filled with a material different from the material forming the crack stop structure and / or the hybrid bonding interface. The voids provide air gaps to prevent micro cracks. However, filling the voids with dielectric materials can provide more stable operation because air gaps are susceptible to changes in temperature and humidity.

[0013] In one embodiment, a first plurality of devices on a first substrate are connected to a first pad, and a second plurality of devices on a second substrate are connected to a second pad, and the first pad and the second pad are connected at a bonding interface. The pads provide an ideal way to form hybrid bonds.

[0014] In one embodiment, the third substrate includes a die portion, a crack stop structure, and a hybrid bonding interface. The hybrid bonding interface of the third substrate is adjacent to the second substrate and faces the hybrid bonding interface of the first substrate to form a hybrid bond with the first substrate. A structure having a base substrate and two or more substrate structures bonded to the base substrate can provide greater flexibility in arranging gaps for microcrack stopping.

[0015] According to one embodiment, a joint semiconductor device includes a first wafer and a second wafer, each wafer having a bonding surface and a bonding pad. A plurality of void patterns adjacent to the bonding pad are formed in the first wafer and / or the second wafer. The first wafer and the second wafer are hybrid bonded to each other at the bonding pad. The use of the void patterns can enhance the microcrack stopping capability of the semiconductor structure.

[0016] In one embodiment, at least some of the plurality of void patterns are formed in the bonding surface of the first wafer and / or the second wafer. The arrangement of the void patterns in the bonding surface can prevent micro cracks from propagating along the interface.

[0017] In one embodiment, a plurality of void patterns alternate between the joining surface of the first wafer and the joining surface of the second wafer. Spreading of the void pattern provides stopping of micro cracks over a larger area.

[0018] In one embodiment, at least some of the void patterns are arranged adjacent to the bond pad and are smaller than the height of the bond pad. Smaller void patterns can be particularly effective in resisting internal stress.

[0019] In one embodiment, the bond pad is a metal bond pad and the void pattern has a varying depth in a corresponding back-end-of-line (BEOL) stack of the bond surface. The varying depth results in air gaps of different sizes and can prevent micro cracks from different stresses, such as internally generated stresses.

[0020] According to an embodiment, a method for manufacturing a hybrid bonded crack stop structure having voids includes providing a first substrate and a second substrate, each of the first substrate and the second substrate including a die portion and at least one crack stop structure adjacent to the die portion. A hybrid bonding interface is formed between an upper surface of the first substrate and the second substrate. The first substrate and the second substrate are hybrid bonded at the hybrid bonding interface. One or more voids are patterned adjacent to the hybrid bonding interface. Patterning the voids after the structure is hybrid bonded can facilitate easier construction than first manufacturing the voids in each of the first substrate and the second substrate.

[0021] In one embodiment, before hybrid bonding of the first substrate and the second substrate, a resist layer is disposed on each hybrid bonding interface, and patterning of the first void in the upper surface of the first substrate and the second void in the second substrate that are substantially aligned is performed. The resist layer is removed, and the first substrate and the second substrate are hybrid bonded. A single integral void with an air gap is formed by the substantially aligned first void and the second void. The single integral void with an air gap extends through the hybrid bonding interface. This structure provides a way to align two structures including voids to produce an integral void, and prevents microcracks from propagating along the interface and damaging the die.

[0022] In one embodiment, a pattern of voids is created around the individual metal bond pads by creating topography on the surface of each substrate prior to bonding by hybrid bonding. A macroscopic hybrid bond pattern is created that includes metal pad surfaces bonded to metal pad surfaces, dielectric surfaces bonded to dielectric surfaces, and voids bonded to voids. This patterning of voids provides a more effective stop to propagating microcracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used in addition or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for more effective description. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar components or steps.

[0024] Figure 1A A joined semiconductor structure having at least one microcrack is shown.

[0025] Figure 1B A hybrid bonded semiconductor structure is shown, with an enlarged portion of a hybrid bonded junction showing the path of a microcrack.

[0026] Figure 2 A structure of a hybrid bond crack stop structure having voids for air gaps is shown consistent with an illustrative embodiment.

[0027] Figure 3 A structure of a hybrid bond crack stop structure having multiple voids for air gaps is shown consistent with illustrative embodiments.

[0028] Figure 4 A structure of a hybrid bonded crack stop structure having multiple voids for an air gap, and an extended crack stop structure, consistent with illustrative embodiments, is shown.

[0029] Figure 5A , 5B 5C illustrate various types of voids within a crack stop framework of a hybrid bonded semiconductor structure consistent with illustrative embodiments.

[0030] Figure 5D , 5E 5F show patterns of voids in a continuous circle, a dashed circle, and a circle with a grid consistent with the illustrative embodiments.

[0031] Figure 5G , 5H and 5I respectively show the same as the illustrative embodiment Figure 5D , 5E and a rotated view of the arrangement of the pattern in 5F.

[0032] Figure 5J Another pattern with three-dimensional views and rotated views is shown consistent with the illustrative embodiments.

[0033] Fig. 6A and 6B A pattern of voids in each semiconductor is shown that bridges the link bonding interface consistent with the illustrated embodiment.

[0034] Figure 6C A gap etched across a join bond interface is shown consistent with an illustrative embodiment.

[0035] Fig.6D An alternative arrangement of new gaps in the hybrid bonding region is shown consistent with the illustrative embodiments.

[0036] Figure 7 Hybrid bond pads having various pattern arrangements and different types of voids integrated into the bond pattern are shown consistent with the illustrative embodiments.

[0037] Figure 8 A process flow for producing a semiconductor structure having hybrid bonding and voids to create air gaps is shown consistent with an illustrative embodiment.

[0038] Fig. 9 is a flow chart illustrating some operations of a method for fabricating a semiconductor structure having a mixture and voids for air gaps, consistent with an illustrative embodiment. DETAILED DESCRIPTION

[0039] In the following detailed description, many specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings can be practiced without these details. In other cases, known methods, processes, components and / or circuits have been described at a relatively high level without detailed description to avoid unnecessarily obscuring the various aspects of the present teachings. It should also be understood that the present disclosure is not limited to the depictions in the accompanying drawings, as there may be fewer elements or more elements than shown and described.

[0040] When discussing the present technology, it may be helpful to describe various highlight terms. In one aspect, spatially related terms such as "front", "rear", "top", "bottom", "below", "below", "lower", "above", "upper", "side", "left", "right", etc. are used with reference to the direction of the drawings being described. Since the components of the embodiments of the present disclosure can be positioned in a plurality of different directions, the directional terms are used for illustrative purposes and are by no means restrictive. Therefore, it will be understood that, in addition to the directions depicted in the figures, the spatially relative terms are intended to cover different directions of the device in use or operation. For example, if the device in the figure is flipped, the elements described as being "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, for example, the term "below" can cover the orientation of above as well as below. The device can be oriented in other ways (rotated 90 degrees or viewed or referenced in other directions), and the spatially relative descriptors used herein should be interpreted accordingly.

[0041] As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to a first surface of a chip.

[0042] As used herein, the term “vertical” describes an orientation that is arranged perpendicular to a first surface of a chip, a chip carrier or a semiconductor body.

[0043] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, if an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. The term "electrically connected" refers to a low-ohmic electrical connection between elements that are electrically connected together.

[0044] Although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0045] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic representations of idealized or simplified embodiments (and intermediate structures). Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the regions shown in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and are not intended to limit the scope.

[0046] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not restrictive. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

[0047] As used herein, certain terms are used to describe openings made to prevent the development of microcracks. A person of ordinary skill will understand that the terms void, cavity, and groove all refer to spaces in the surface of a bonding interface, substrate, or dielectric. For ease of description, the term "void" is used throughout this disclosure.

[0048] Although the terms first, second, third, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0049] Example embodiments are described herein with reference to schematic diagrams of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the regions shown in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and are not intended to limit the scope.

[0050] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not restrictive. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

[0051] Overview

[0052] The present disclosure proposes a structure and method for a hybrid bond crack stop structure with an air gap. The present disclosure also discloses a structure and method for a hybrid bond joining interface with an air gap incorporated into a pattern.

[0053] Figure 1A An example of a joined semiconductor structure 100A is shown, wherein a first substrate 101 and a second substrate 102 have respective dielectric layers 105, 110 thereon. The first substrate 101 and the second substrate 102 are joined by hybrid bonding. An interface 115 exists at the junction interface between two crack stop structures 125 and two columns of devices 120 (sometimes referred to as dies). In the present hybrid bonding, an interface 115 exists at the junction / interface between the crack stop structure 125 (shown in a dashed box) and the two devices 120. This interface 115 can be increased in size by microcracks 130 to separate the first bonded substrate from the second bonded substrate, or used as an access entry point, from which the microcracks 130 can bypass the crack stop structure 125 and potentially propagate downward into the die stack within the main active area, as shown. Figure 1A The microcrack 130 shown in FIG. 1 may propagate far enough to reach the device 120 and may result in catastrophic die failure.

[0054] Embodiments of the present disclosure relate to creating air gaps by placing grooves, cavities, or voids (hereinafter collectively referred to as "voids") across hybrid joints to prevent crack propagation along a hybrid bonded junction of two substrates. The voids can stop / reduce the incidence of cracks caused by both external stresses (e.g., from dicing wafers and from heat, moisture, and bonding pressure) and internal stresses (e.g., nascent cracks from the manufacturing process), and can be differently sized and arranged adjacent to crack arrest structures and devices to prevent the propagation of microcracks. The growth and propagation of microcracks are prevented by the air gaps created by the voids.

[0055] Figure 1BThe hybrid bonded semiconductor 100B structure is shown with an enlarged portion of the hybrid bonded junction 135 to illustrate the path of the microcrack 130. Despite the presence of several crack stop structures 125, the microcrack 130 can still propagate between the metal-to-metal and oxide-to-oxide junctions shown.

[0056] Example Architecture

[0057] Figure 2 A structure 200 for a hybrid bonded crack stop structure with an air gap is shown consistent with an illustrative embodiment. Figure 1A , Figure 2 The structure of FIG. 1 shows a first substrate 101 and a second substrate 102 having dielectric layers 105 and 110 thereon. The first substrate 101 and the second substrate 102 are bonded together by hybrid bonding. There is also an interface 115 (a portion of which is circled) at the junction interface between the two crack stop structures 125 and the two columns of devices 120.

[0058] Still reference Figure 2 , shows an example of a void 240 arranged across the junction of the first substrate and the second substrate. The void 240 creates an air gap that prevents the microcrack 130 from spreading on the structure. The circle with the slash shows that the microcrack 130 is prevented and does not further expand due to the void 240.

[0059] Example Embodiments

[0060] Figure 3 A structure 300 for a hybrid bonded crack stop structure having multiple voids for air gaps is shown consistent with an illustrative embodiment. Figure 3 In FIG. 1 , the basic concept of arranging the gap 240 across the hybrid bonding junction is to remove the material in which the crack propagates and prevent forward progress. It should be noted that the crack stop structure 125 stops before the hybrid junction, so the gap 240 can prevent the crack from propagating along the hybrid junction, such as Figure 1B and 1C.

[0061] Figure 4 A structure 400 for a hybrid bonded crack stop structure having multiple voids for air gaps and an extended crack stop structure is shown consistent with illustrative embodiments. Figure 4 and Figure 3 The difference is at least that the crack stop structures 125 of the first substrate 301 and the second substrate 301 are connected across the hybrid bond junction 135. However, the additional voids 240 add an extra measure to prevent micro cracks from possibly crossing the crack stop structure and damaging the device 120, because the air gap created by the voids 240 together with the crack stop structure 125 prevents more cracks than the crack stop structure 125 alone.

[0062] Figure 5A, Figure 5B and Figure 5C Various types of voids are shown incorporated into the crack stop structure design around the perimeter of a hybrid bonded semiconductor structure consistent with illustrative embodiments. The voids shown are annular 545, discontinuous 547, and circular 549. It should be understood that the present disclosure is not limited to the voids shown and described and are presented for illustrative purposes. Figure 5A , 5B And different shapes in 5C.

[0063] Figure 5D , 5E 5F show patterns of voids in a continuous circle, a dashed circle, and a circle with a grid consistent with the illustrative embodiments. Figure 5A A continuous circular pattern of voids is shown. Figure 5E A non-continuous circular pattern 553 is shown. Fig. 5F A circular pattern 555 within the grid is shown.

[0064] Figure 5G , 5H and 5I respectively show the same as the illustrative embodiment Figure 5D , 5E and a rotating view of the arrangement of the pattern in 5F. The continuous circle 5510 is Figure 5G Shown in. Figure 5H A non-continuous pattern 5530 is shown. Fig.5I A circular pattern 5550 within the grid is shown.

[0065] Figure 5J A modified circular void pattern 557 is shown having a three-dimensional view 5557 and a rotated view 559 consistent with an illustrative embodiment. The gaps in the circular pattern are shown in the rotated view 559.

[0066] Fig. 6A and Figure 6B A void pattern is shown in each semiconductor that spans the bond interface within a commonly bonded crack stop structure design and around the perimeter of the active device area of ​​the hybrid bonded adjoining semiconductor construction. Fig. 6A Shown are voids 240 patterned in each individual semiconductor construction that have been joined to create a single unitary void bridged across the joint bonding interface. Figure 6B Different sizes of gaps 240 are shown to aid in alignment. Figure 6B In FIG. 2 , two voids 240 appear to have a smaller void and a larger void connected to form an integral void.

[0067] Figure 6CA gap etched across the join bonding interface is shown consistent with the illustrated embodiment. After die-to-die bonding, the etched gap 640 spans the bonding interface. The gap may be filled with an underfill and / or overmold, etc.

[0068] Fig.6D An alternative arrangement of new gaps in a hybrid bonding region consistent with an illustrative embodiment is shown. New gaps 650 are arranged in the hybrid bonding region. These gaps 650 can, for example, be etched into the hybrid bonding region.

[0069] Figure 7 A structure with various patterns and different types of voids positioned around hybrid connection pads consistent with the illustrative embodiment is shown. It should be understood that in this embodiment, the voids are arranged around the hybrid connection pads of the electrical connections of the main area of ​​the active device. These voids are provided to solve the inherent intrinsic defects caused by the connection process and the structure itself. Although the previously described voids shown and described solve the external non-intrinsic cracks / defects caused by external forces (such as cutting, etc.). Compared with the voids that solve the externally caused and / or non-intrinsic cracks / defects, the voids around the periphery of the die of the active main area are more discrete and are located around and around the active electrical connection portion of the device. The voids 240 are in various shapes and patterns, each void having a different air gap to prevent micro cracks from both external stress and internal stress. For example, structure 702 shows a symmetrically shaped void 240. Structure 704 shows a void 240 in which the size of one portion is different from the size of another portion. Structure 706 shows that the voids are arranged in an alternating orientation (compared to structure 704). The different sizes of gaps 240 shown in structures 702, 704, and 704 are intended to facilitate alignment of the hybrid bonded structures.

[0070] Still reference Figure 7 , voids 240 of structure 706 are much thinner than, for example, voids 240 in structures 702, 704, and 706. Structure 710 shows voids 240 arranged on only one of the linked structures, and structure 712 shows an alternating arrangement.

[0071] Structures 714, 716, and 718 show voids 240 partially etched in the top dielectric layer. For example, structure 714 has relatively shorter voids 240 than used in structure 708. Structures 716 and 718 are similar to structures 710 and 712 in terms of the arrangement of the voids, but the voids 240 in structures 716 and 716 are shorter than in structures 710 and 712.

[0072] Example Process

[0073] With the foregoing overview of the example architecture, it may be helpful to now consider a high-level discussion of the example process. To this end, Figure 8A process flow for producing a semiconductor structure having hybrid bonding and voids to create an air gap is provided consistent with illustrative embodiments. Fig. 9 900 is a flowchart illustrating some operations of a method for fabricating a semiconductor structure having a hybrid junction and a void for an air gap consistent with an illustrative embodiment. It should be understood that the process shown and described is provided for illustrative purposes and the present disclosure is not limited to the process of fabricating a semiconductor structure having a hybrid junction and a void for an air gap consistent with an illustrative embodiment. Fig. 9 For example, the voids may be created in other ways (including but not limited to etching), and thus one specific non-limiting technique or process flow that may be used is shown.

[0074] refer to Figure 8 , structure 802 includes a substrate with a dielectric layer, a crack stop structure, and a device thereon. Structure 804 shows a resist layer 855 added on top of a bonding junction. Structure 806 shows a void 240 formed in the resist layer 855 and the semiconductor below. Structure 810 shows the removal of the resist layer 855 from the bonding junction. Structure 812 shows a first substrate and a second substrate aligned at the void 240. Structure 814 shows a hybrid bonded two substrate structure. Void 240 is shown bridged across the hybrid bond junction.

[0075] Fig. 9 Shown as a collection of blocks in a logical sequence, it represents a sequence of operations that can be implemented in combination.

[0076] At operation 902, a first substrate and a second substrate are provided, each of the first substrate and the second substrate including a die and at least one crack stop structure adjacent to a portion of the die. Figure 8 An example of a structure 802 having a die and a crack stop structure is shown.

[0077] At operation 904, a hybrid bonding interface is disposed on the upper surfaces of the first substrate and the second substrate. The hybrid bonding interface may be similar to Figure 1B An example is shown in . A hybrid bonding interface can have an oxide portion and a metal portion.

[0078] At operation 906, a resist layer is disposed on each hybrid bonding interface. Figure 8 Shown in structure 804 is a resist layer 855 disposed on the hybrid bonding interface.

[0079] At operation 908, a first void is patterned in the upper surface of the first substrate and a second void is patterned in the second substrate. The first void and the second void are substantially aligned. Structure 810 shows a non-limiting example of aligned substrates. It should be understood that operation 908 is optional. For example, a hybrid bonded structure can be formed at operation 910 (described below) and then the void can be etched into the substance. Arranging the void after hybrid bonding can facilitate hybrid bonded structures, requiring less alignment effort, compared to the case where the void is first patterned in the substrate surface before bonding.

[0080] At operation 910, the resist layer is removed, and the first substrate and the second substrate are hybrid bonded. Figure 8 Structure 814 is shown, which is a hybrid bonded structure having voids disposed between crack stop structures and bridging the hybrid bond interface.

[0081] The method ends after operation 910. It should be understood that there may be additional voids of various sizes and locations disposed on the first substrate and the second substrate prior to the hybrid bonding operation.

[0082] in conclusion

[0083] The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0084] Although the foregoing has described what is considered to be the best state and / or other examples, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and examples, and the teachings may be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0085] The components, operations, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. None of them and the discussion relating to them is intended to limit the scope of protection. Although various advantages have been discussed herein, it should be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, sizes, dimensions, and other specifications set forth in this specification (including in the appended claims) are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they are related and the practices in the field to which they belong.

[0086] Many other embodiments are also contemplated. These include embodiments with fewer, additional and / or different components, steps, features, objects, benefits and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0087] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is meant only as an example, rather than the best or optimal. Except as stated immediately above, nothing stated or shown is intended or should be construed as causing any component, step, feature, object, benefit, advantage, or equivalent to be dedicated to the public, whether or not it is recited in the claims.

[0088] It should be understood that the terms and expressions used herein have the common meaning consistent with these terms and expressions of the corresponding investigation and research fields corresponding thereto, unless a specific meaning is otherwise set forth herein. Relational terms such as first and second etc. can be used only to distinguish one entity or action from another entity or action, without necessarily requiring or implying any such actual relationship or order between these entities or actions. The terms "include", "comprise" or any other variation thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including the list of elements not only includes those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article or device. In the absence of further constraints, an element beginning with "one" or "an" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0089] An abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the present technical disclosure. It should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying the present disclosure. The method of the present disclosure should not be interpreted as reflecting the intention that the claimed embodiments have more features than the features explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the present invention lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are hereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

Claims

1. A hybrid bonded semiconductor structure, comprising: The first substrate and the second substrate each have an interface connected by hybrid bonding; Each substrate includes a die portion and a crack stop structure adjacent to the die portion; and one or more voids formed in the first substrate and the second substrate around a portion of a perimeter of each crack stop structure, Wherein at least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form an integrated void having an air gap across the hybrid bonding interface. 2 . The semiconductor structure of claim 1 , wherein the crack stop structures of the first substrate and the second substrate are joined at the hybrid bonding interface. 3 . The semiconductor structure of claim 1 , wherein at least some of the voids formed in each of the first substrate and the second substrate are shaped differently. 4 . The semiconductor structure of claim 1 , wherein the one or more voids comprise a plurality of voids, at least some of the plurality of voids having different sizes. 5 . The semiconductor structure of claim 1 , further comprising a plurality of voids arranged continuously and extending across the hybrid bonding interface.

6. The semiconductor structure of claim 1, wherein: Each hybrid bonding interface includes back-end-of-line (BEOL) interconnect levels, and The integral void is at least partially filled with a dielectric or polysilicon material that is different from the material of the hybrid bonding interface.

7. The semiconductor structure of claim 1, wherein one or more voids in the first substrate and the second substrate are annular. 8 . The semiconductor structure of claim 1 , wherein the one or more voids in the first substrate and the second substrate are arranged as non-continuous rings.

9. The semiconductor structure of claim 1, wherein one or more voids in the first substrate and the second substrate are circular.

10. The semiconductor structure of claim 1, wherein the one or more voids are filled with a material different from a material forming the crack stop structure and / or the hybrid bonding interface.

11. The semiconductor structure of claim 1, further comprising a first plurality of devices connected to a first pad on the first substrate and a second plurality of devices connected to a second pad on the second substrate, wherein the first pad and the second pad are connected at the hybrid bonding interface.

12. The semiconductor structure according to claim 1 further includes a third substrate, the third substrate including a core portion, a crack stop structure and a hybrid bonding interface, wherein the hybrid bonding interface of the third substrate is adjacent to the second substrate and faces the hybrid bonding interface of the first substrate to form a hybrid bond with the first substrate.

13. A combined semiconductor device comprising: a first wafer and a second wafer, each wafer having a bonding surface and a bonding pad, and a plurality of void patterns formed adjacent to bonding pads in the first wafer and / or the second wafer, The first wafer and the second wafer are hybrid-bonded to each other at the bonding pads. 14 . The joint semiconductor device of claim 13 , wherein at least some of the plurality of void patterns are formed in a joining surface of the first wafer and / or the second wafer. 15 . The joint semiconductor device of claim 13 , wherein the plurality of void patterns alternate between a joining surface of the first wafer and a joining surface of the second wafer. 16 . The joint semiconductor device of claim 13 , wherein at least some of the void patterns are disposed adjacent to the bonding pad and are smaller than a height of the bonding pad.

17. The joint semiconductor device according to claim 13, wherein: The bonding pad comprises a metal bonding pad; and The void pattern has a varying depth in a corresponding back end of line (BEOL) stack of the bonding surface.

18. A method of manufacturing a hybrid bonded crack arrest structure having a void, the method comprising: providing a first substrate and a second substrate, each of the first substrate and the second substrate comprising a die portion and at least one crack stop structure adjacent to the die portion; disposing a hybrid bonding interface on upper surfaces of the first substrate and the second substrate; hybrid bonding the first substrate and the second substrate; and One or more voids adjacent to the hybrid bonding interface are patterned.

19. The method of claim 18, wherein before performing hybrid bonding of the first substrate and the second substrate: disposing a resist layer on each hybrid bonding interface; patterning a first void in an upper surface of the first substrate and a second void in the second substrate, wherein the first void is substantially aligned with the second void; removing the resist layer; and A single integral void with an air gap is formed from the substantially aligned first and second voids, wherein the single integral void with an air gap extends across the hybrid bonding interface.

20. The method of claim 18, further comprising: patterning voids created around respective metal bond pads by creating topography on the surface of each substrate prior to bonding by hybrid bonding; and A macroscopic hybrid bonding pattern is generated, the macroscopic hybrid bonding pattern including metal pad surfaces bonded to metal pad surfaces, dielectric surfaces bonded to dielectric surfaces, and voids bonded to voids.

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