System and method for non-overlapping implementation of inverter for electric vehicle

Abstract

A system includes: an inverter including: a first electrical interface to separate a first high voltage region from a low voltage region; a first low voltage controller in the low voltage region, the first low voltage controller configured to send a first control signal to a first high voltage controller in the first high voltage region using the first electrical interface; a second electrical interface for separating a second high voltage region from the low voltage region; and a second low voltage controller in the low voltage region, the first low voltage controller configured to send a second control signal to a second high voltage controller in the second high voltage region using the second electrical interface, wherein the second low voltage controller is configured to provide an output latch signal to the first low voltage controller and to receive an input latch signal from the first low voltage controller.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 18 / 163,381 filed on February 2, 2023, which claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, and U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure generally relate to systems and methods for a gate driver for an inverter for an electric vehicle, and more particularly to systems and methods for a gate driver having a closed loop non-overlapping implementation architecture for phase switching elements for an inverter for an electric vehicle. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for converting high voltage direct current (HVDC) to alternating current (AC) to drive the motors. In inverters, overlapping turn-on events of relative phase switching elements can damage the inverter, and the dead time between switching events used to avoid overlapping turn-on events causes inverter inefficiency.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a first electrical interface configured to separate a first high voltage region from a low voltage region; a first low voltage controller, the first low voltage controller being in the low voltage region, the first low voltage controller being configured to receive a first PWM signal from a PWM controller and to send a first control signal to the first high voltage controller in the first high voltage region using the first electrical interface based on the first PWM signal; and a second electrical interface, The second electrical interface is configured to separate the second high voltage region from the low voltage region; and a second low voltage controller, which is in the low voltage region, the first low voltage controller is configured to receive a second PWM signal from the PWM controller, and based on the second PWM signal, uses the second electrical interface to send a second control signal to the second high voltage controller in the second high voltage region, wherein the second low voltage controller is configured to provide an output latch signal to the first low voltage controller and receive an input latch signal from the first low voltage controller, and wherein the output latch signal is based on the second PWM signal and the input latch signal.

[0007] In some aspects, the technology described herein relates to a system wherein a first low voltage controller is further configured to receive a feedback signal from a first high voltage controller via a first electrical interface, and wherein an input latch signal is based on a first PWM signal, an output latch signal, and the feedback signal.

[0008] In some aspects, the technology described herein relates to a system in which a first low voltage controller is configured to send a first control signal using a set of communication lines of a first electrical interface and to receive a feedback signal using the set of communication lines in the first electrical interface.

[0009] In some aspects, the technology described herein relates to a system in which a first control signal is configured to control a phase switching device of an inverter, and a feedback signal is configured to indicate an off state of the phase switching device.

[0010] In some aspects, the technology described herein relates to a system in which a first low voltage controller is configured to record time based on a first PWM signal and a feedback signal.

[0011] In some aspects, the techniques described herein relate to a system in which a first low voltage controller is configured to generate a fault based on a first PWM signal and an output latch signal.

[0012] In some aspects, the techniques described herein relate to a system in which an output latch signal and an input latch signal respectively enable a first PWM signal in a first low voltage controller and a second PWM signal in a second low voltage controller.

[0013] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to an inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0014] In some aspects, the technology described herein relates to a system comprising: a high voltage controller, the high voltage controller being configured in a high voltage region separated from a low voltage region by an electrical interface comprising a command channel and a message channel, the high voltage controller being configured to use the command channel of the electrical interface to receive a control signal from a low voltage controller in the low voltage region, to control a phase switching element based on the control signal, and to use the command channel of the electrical interface to send a switching element status signal to the low voltage controller, wherein the high voltage controller is configured to control the switching element status signal based on the status of the phase switching element.

[0015] In some aspects, the technology described herein relates to a system in which a high voltage controller is configured to send a switch status signal using a command channel of an electrical interface when the high voltage controller is not receiving a control signal from the command channel of the electrical interface.

[0016] In some aspects, the technology described herein relates to a system in which a high voltage controller is configured to send a switch state signal by sending a burst of electrical pulses on a command channel of an electrical interface.

[0017] In some aspects, the technology described herein relates to a system in which a high voltage controller includes one or more point-of-use controllers on a power module having a phase switch.

[0018] In some aspects, the technology described herein relates to a system in which a high voltage controller is configured to send control signals to one or more point-of-use controllers on a power module having phase switching elements and receive switching element status signals from the one or more point-of-use controllers.

[0019] In some aspects, the technology described herein relates to a system in which the high voltage controller is further configured to invert the switch element state signal and send the switch element state signal and the inverted switch element state signal to the low voltage controller using a command channel of the electrical interface.

[0020] In some aspects, the technology described herein relates to a system comprising: an electrical interface configured to separate a high voltage region from a low voltage region; a low voltage controller in the low voltage region, the low voltage controller comprising: a PWM comparator configured to receive a PWM signal and an input latch signal and generate a PWM comparator signal based on a comparison of the PWM signal and the input latch signal; a low voltage pulse generator configured to generate an upstream pulse based on the PWM comparator signal; a low voltage transmitter configured to send an upstream pulse to the electrical interface; a low voltage receiver configured to receive a downstream pulse from the electrical interface; a low voltage demodulator configured to generate a low voltage demodulation signal based on the downstream pulse; and an enable latch. , the enable latch is configured to be set with a low voltage demodulation signal and reset with a PWM comparator signal, the enable latch is further configured to provide an output latch signal; and a high voltage controller, the high voltage controller is in a high voltage region, the high voltage controller includes: a high voltage receiver, the high voltage receiver is configured to receive an upstream pulse from an electrical interface; a high voltage demodulator, the high voltage demodulator is configured to generate a high voltage demodulation signal based on the upstream pulse, the high voltage demodulation signal is configured to control a phase switching element; a high voltage off-state detector, the high voltage off-state detector is configured to detect the off-state of the phase switching element; a high voltage pulse generator, the high voltage pulse generator is configured to generate a downstream pulse based on the detected off-state of the phase switching element; and a high voltage transmitter, the high voltage transmitter is configured to send a downstream pulse to the electrical interface.

[0021] In some aspects, the technology described herein relates to a system in which a high voltage controller includes one or more point-of-use controllers on a power module having a phase switch.

[0022] In some aspects, the technology described herein relates to a system wherein the low voltage controller further comprises: a round trip timer configured to record a time from when the PWM signal becomes a logic low to when the output latch signal becomes a logic high.

[0023] In some aspects, the technology described herein relates to a system wherein the low voltage controller further comprises an overlap comparator configured to generate a fault when the PWM signal is logic high and the input latch signal is logic low.

[0024] In some aspects, the technology described herein relates to a system wherein the high voltage controller further comprises: a high voltage inverter configured to invert the downstream pulses to the high voltage transmitter.

[0025] In some aspects, the technology described herein relates to a system wherein the low voltage controller further comprises: a low voltage inverter configured to invert the upstream pulses to the low voltage transmitter.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 An exemplary system for implementing a gate driver for closed loop non-overlapping of a phase switching device according to one or more embodiments is depicted.

[0035] Figure 7 Depicted are exemplary waveform diagrams for a closed loop non-overlapping implementation of a gate driver for a phase switching device in accordance with one or more embodiments. DETAILED DESCRIPTION

[0036] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0037] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0038] Various embodiments of the present disclosure generally relate to systems and methods for a gate driver for an inverter for an electric vehicle, and more particularly to systems and methods for a gate driver having a closed loop non-overlapping implementation architecture for phase switching elements for an inverter for an electric vehicle.

[0039] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three half-H-bridge switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the half-H-bridge switches. The half-H-bridge switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the half-H-bridge switch by passing through the isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the half-H switching element via the gate driver output.

[0040] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0041] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0042] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0043] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0044] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0045] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point of use ICs have not yet been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0046] As described above, the half-H switching element can be, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect device (MOSFET), or another semiconductor device. For example, the turn-on and turn-off times of the half-H switching element may vary from device to device, with operating temperature, and with changes in gate driver power supply. A key design aspect of controlling the operation of the half-H switching element is to ensure that the opposite sides of the switching element (e.g., the upper phase and the lower phase) are not turned on at the same time. This is achieved by intentionally including a non-overlapping time or dead time from the commanded turn-off of the on-state switching element to the commanded turn-on of the opposite off-state switching element. Overlapping on states of relative switching elements can result in a shoot-through condition, resulting in an overcurrent event that can damage the system. Some design techniques use a fixed non-overlapping time that is implemented using logic before sending a PWM signal to the gate driver that controls the switching element.

[0047] Circuitry may be used on both sides of a half-H switch to detect and react to overcurrent events because overlapping events may occur despite the presence of fixed-time based non-overlap logic. For example, a shoot-through event may occur because the action of commanding the switch off does not guarantee that the switch will hit the off state command before the commanded on of the opposing switch, such as due to a failure of the gate driver, a failure of the switch, or a failure of the non-overlap logic. For these reasons, a fixed-time based non-overlap implementation is essentially open-loop because confirmation of the off state of one switch is not used to enable the commanded on of the opposing switch.

[0048] A closed loop non-overlap control system is a closed loop non-overlap control system in which a command-on signal to a switch is blocked unless the feedback signal verifies that the opposing switch is in the off state. Another way to describe this form of closed loop system would be to qualify it as "break before make", i.e. one switch must be broken (commanded off) before the opposing switch can be made (commanded on). A system that uses only fixed non-overlap times cannot be qualified as a break before make system.

[0049] When the dead time is reduced, the conversion efficiency in the inverter system can be improved. Dead time is an operating phase within the inverter control system in which both the upper switching element and the lower switching element are open and the phase voltage is not driven to a defined voltage by the switching element. The resulting dead phase voltage is a function of the direction and magnitude of the phase load current and the electrical characteristics of the open circuit switching element. The dead time phase of operation is the time when the phase voltage is not driven to the desired state of the system controller, and therefore represents a period of reduced switching efficiency. The minimum allowable dead time can be determined by considering all sources of variation that can increase the time required to open the on-state switching element and all sources of variation that can reduce the time required to open the relative off-state switching element. Statistical analysis may be required to calculate the probability that non-overlapping events may occur.

[0050] Due to the variation in characteristics of components in the signal path (including the switching element itself), the time between when the PWM command at the gate driver input is turned off to when the switching element is completely turned off may have a range of values. Due to the variation in characteristics of components in the signal path (including the switching element itself), the time between when the PWM command at the gate driver input is turned on to when the switching element begins to open may have a range of values. As part of the system architecture, these two time functions are separated by non-overlapping time. Overlap of these two time functions will result in a shoot-through condition. Some aspects of the variation within these two time functions may be statistical in nature, with a mean and standard deviation, so that there may never be a zero overlap probability. The best effect that can be achieved for the two time functions is to reduce the overlap probability by using sufficiently long non-overlapping times.

[0051] The above analysis applies to the case where the system is operating as expected and there are no failures that would cause the system to not follow the expected command on and command off time functions. For example, a PWM pin that is permanently or temporarily stuck in the asserted (high) state could be a failure mechanism that would cause the system to not follow the expected command off time function and that would cause a shoot-through event.

[0052] Some designs describe a dual channel closed loop non-overlap approach that can address the shortcomings of time-based open loop non-overlap implementations. Closed loop non-overlap implementations can use the following principle: before allowing the command to the opposite switch to open, a signal must be received from the switch to indicate that the switch is in the off state. Some designs describe a dual channel system in which a feedback channel is used to transmit the real-time on or off state of the switch, and a separate command channel is used to transmit the desired on or off command state of the switch.

[0053] Due to the nature of the communication channels, two channels are usually required to transmit both command and feedback data. In applications such as inverters, the communication between the low voltage controller domain and the high voltage switching domain is performed through a galvanic isolation barrier that cannot arbitrarily support simultaneous command data flowing in one direction and feedback data flowing in the opposite direction.

[0054] Due to the inherent lossy nature of the electrical isolation barrier, communication across the electrical isolation barrier requires the generation of a high amplitude signal from the transmit side and the use of a high sensitivity receiver on the receive side. The signal loss factor across the capacitive electrical barrier is a function of the series capacitance between the transmit and receive sides and the parasitic capacitance on the receive side of the electrical barrier. A loss factor between 10:1 and 100:1 would be an appropriate range to be expected from a practical hardware implementation. Such a high loss factor generally means that it is impractical to transmit signals simultaneously in both directions across the electrical barrier.

[0055] While the electrical channel can be designed to allow bidirectional communication by placing the transmitter and receiver on either side of the barrier, communication is typically limited to one direction at a time. Complicating this situation is the typical requirement that the command-on signal state is defined as the presence of continuous communication from the transmitter to the receiver, such that the loss of continuous communication from the transmitter is interpreted as the receiver issuing a command-off signal to the switching element. Such a requirement is very important for functional safety, as the loss of the transmitter due to any fault condition must not result in a continuous switch-element command-on state.

[0056] One observation that eases the requirement for a dual channel solution is that a command-on signal is typically defined as the presence of continuous signaling from the transmitter to the receiver, while a command-off signal is defined as the continuous absence of a signal. In general applications of command and feedback signaling, the presence or absence of continuous signaling along both the command and feedback channels must be allowed, thus necessitating the need for two independent channels to avoid data collisions that could occur if the command and feedback travel in opposite directions along a single electrical channel.

[0057] The dual-channel solution can be simplified to a specific single-channel solution in the following specific case: it is ensured that the single switch element first receives a commanded off signal along a single electrical channel in the form of a lack of continuous signaling from the controller domain to the switch element domain, and secondly, the switch element verifies that the switch element is in the commanded off state by sending a signal from the switch element domain to the controller domain along the same single (currently idle) electrical channel.

[0058] Electrical isolation requires a large area to implement, and each electrically isolated channel represents an opportunity for defect-related failures to occur. One or more embodiments may provide a closed loop feedback system that uses one electrically isolated channel to eliminate the increased cost and defect-related failure mechanisms associated with two electrically isolated channels.

[0059] Some designs using electrical isolation circuits and PWM non-overlapping control methods may describe PWM control of a half-H architecture using electrical isolation circuits, whereby centralized logic is used to control the non-overlap of PWM signals directed to high and low half-H switching elements, and the centralized logic uses the feedback state of the half-H switching element to prevent simultaneous command-on signals from being sent to both high and low half-H switching elements. Some designs show that two signals travel through two electrical interfaces, where the first signal is a PWM signal, and the independent second signal is a PWM enable that is asserted once the relative switching element is confirmed to be in the off state. This design requires a dedicated second electrical channel, which increases costs and may cause failures caused by defects. Some designs acknowledge that a dual-channel approach is necessary. Some designs do not consider reusing the command channel to transmit burst data as feedback. Here, reuse refers to transmitting and receiving signals on the same signal line or multiple signal lines of the command channel, which is relative to sending signals on a first signal line or path and receiving signals on an independent second path.

[0060] One or more embodiments may solve the problem of open loop non-overlapping implementation and the problem of two-channel closed loop non-overlapping implementation. When the switch is detected to be in the off state after the command off signal, the off state detector in the point-of-use controller can assert the output signal. When the off state detector asserts the output signal, the pulse burst transmitter in the point-of-use controller can send a short burst of electrical pulses in the downstream direction in the usual upstream electrical command channel. The electrical transmitter in the high voltage domain of the gate driver can retransmit the downstream electrical pulses from the point-of-use controller. The electrical receiver in the low voltage domain of the gate driver can detect the retransmitted downstream electrical pulses. The demodulator in the low voltage domain of the gate driver can convert the detected pulses into a logic 1 state. When the demodulator asserts the logic 1 state, the detection latch in the low voltage domain of the gate driver can be set. An AND gate in the low voltage domain of the gate driver can perform a logical AND operation with the PWM input signal and set the output of the enable latch for the opposite phase switch to enable (set the enable latch to a logic 1 state) and disable (set the enable latch to a logic 0 state) the PWM on state (logic 1) observed by the phase switch. An overlap detector can detect the situation when the PWM input to the AND gate is a logic 1 and the latch input to the AND gate is a 0, indicating that the system is trying to turn on the phase switch without receiving an off state confirmation from the opposite phase switch. A round trip timer can count the time between the time the enable latch from the output of the AND gate is set to a logic 0 and the time the enable latch is set to a logic 1, indicating the round trip command off time.

[0061] Some designs may describe a semi-H switcher environment with upper and lower switcher channels, each including an upstream command channel for transmitting on / off control signals from the low voltage domain to the high voltage domain, and a downstream message channel for transmitting the real-time on / off state of the switcher from the high voltage domain to the low voltage domain. Some designs may describe a PWM controller with the ability to send PWM high and low states upstream in the command channel and process data coming downstream in the message channel in order to adjust the PWM commands to prevent shoot-through events. Some designs may require a dedicated electrical channel to transmit continuous real-time status feedback of the switcher.

[0062] One or more embodiments may use an electrical command channel to transmit the off state of the switching element at a point in time when the channel no longer transmits an on-state command, and may use a burst of electrical pulses that lasts only long enough to transmit the successful off state to transmit the off state of the switching element. One or more embodiments may include a round-trip timer. One or more embodiments may include a non-overlap detector. One or more embodiments may include one less electrical channel per switching element than some designs. For example, for a three-phase inverter using six switching element channels, one or more embodiments may save a total of six electrical channels compared to some designs with twelve electrical channels. Each electrical channel may require area within an integrated circuit or may require external components to implement, and therefore one or more embodiments may be cheaper than some designs and have a lower probability of defect-related failures. One or more embodiments may include closed-loop non-overlap violation detection and round-trip timer diagnostics, which are advantages over some designs.

[0063] Some designs appear to be able to provide the real-time on or off state of the switching element to the low voltage plane, and this appears to provide an additional level of protection to prevent situations such as when the switching element is suddenly and instantaneously turned on when the relative switching element is currently turned on. This appears to allow the PWM controller or diagnostic circuit to prevent a shoot-through condition under this fault. However, it takes a finite time to transmit the change of the switching element state from the off state to the on state to the low voltage plane so that the relative switching element can be commanded to disconnect. The shoot-through event caused by this fault will occur during the entire time required to transmit the fault from the high voltage plane to the low voltage plane and then transmit the response from the low voltage plane to the high voltage plane. There is no advantage in using a dedicated auxiliary electrical channel to transmit the situation where an uncontrolled command has occurred, because the transmission of this information will not prevent the shoot-through event, because there is a delay in transmitting the unexpected command state, and there is a delay in mitigating the fault by commanding the relative channel to shut down. The response of the system will be that a shoot-through event occurs, which must be managed by the circuit located in the high voltage domain.

[0064] It will be understood by those skilled in the art that a shoot-through event can only be successfully responded to by an overcurrent detection and response circuit placed at the switch itself, and the communication feedback loop to another controller is too slow. If this were not the case, some designs would not display point-of-use overcurrent detection, such as desaturation detection or shunt current detection. However, by displaying point-of-use overcurrent detection, some designs provide a demonstration that some designs do not attempt to replace overcurrent detection with a closed loop feedback response. Additionally, failure of the electrical interface may prevent the closed loop feedback from responding to the overcurrent condition.

[0065] Thus, one or more embodiments may provide closed-loop feedback that is useful for preventing through-events by requiring confirmation of the off-state of the switching element to enable commands to the relative switching element. Once verification of the off-state of the switching element is received, the real-time state of the switching element in the on or off state is not required, because the real-time information is too slow and unreliable to be used to react to the through-event, and can only be used if the point-of-use overcurrent detection and response is fast enough and reliable enough. Therefore, real-time switching element on / off state feedback is not a required function to prevent through-events. Some designs may be over-designed to prevent through-events by dedicating an entire electrical channel to real-time feedback of the state of the switching element. One or more embodiments may be optimally designed to use a single burst of downstream electrical data through an available command channel to indicate that a successful off-state of the switching element has been reached to enable command-on of the relative switching element.

[0066] As described above, in an inverter, overlapping turn-on events of the switching elements of the opposite phases may damage the inverter, and the dead time between the switching events used to avoid overlapping turn-on events causes inverter inefficiency. Time-based non-overlap may fail if the gate-to-source voltage is too slow, the gate-to-source voltage remains high, the electrical bus communication fails, the PWM signal remains high, or the non-overlap logic is invalid.

[0067] One or more embodiments may provide a closed loop non-overlapping implementation architecture that ensures that an on-state phase switch is turned off before allowing a complementary off-state phase switch to turn on.

[0068] When both the upper phase switch and the lower phase switch are off and one of them is free to open, the lower PWM rising edge can send continuous electrical pulses to the command channel, thereby indicating the command to turn on to the lower phase switch. Then, the lower PWM rising edge can clear the lower latch, which asserts a logic 0 into the upper AND gate, thereby preventing the upper phase switch from turning on. Then, the lower PWM falling edge can stop the upstream electrical pulse, thereby indicating the command to turn off to the lower phase switch. Then, when the command off signal causes the lower phase switch to successfully turn off, the lower phase switch can send a "lower switching element off" downstream pulse burst (e.g., such as 300nS). Then, the "lower switching element off" signal can assert a logic 1 to the lower latch, which feeds the upper AND gate. The lower PWM rising edge may not be accepted before receiving the lower "lower switching element off" confirmation. For example, an overlap violation (i.e., PWM=1 and latch=0) may not propagate upstream and may be detected to set a fault or be reported via a serial peripheral interface. A round-trip timer within each gate driver may be used for fault analysis. One or more embodiments may provide a closed-loop non-overlap implementation architecture in the gate driver rather than in the PWM controller to reduce propagation delays in sending feedback to the PWM controller for signal processing. By ensuring that the on-state phase switch is disconnected before allowing the complementary off-state phase switch to turn on, one or more embodiments may provide a closed-loop feedback system that does not use a fixed non-overlap time or allows fixed non-overlap but prevents non-overlap events that may occur due to fault conditions or when a fixed non-overlap time is statistically infeasible. One or more embodiments may support a minimum non-overlap time of approximately 1 μS, which may be comparable to some open-loop designs. One or more embodiments may provide closed-loop feedback with an electrical channel.

[0069] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1 As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0070] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 3 14). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor in the pair carries an inverted data signal from the other capacitor in the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0071] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0072] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0073] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0074] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0075] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0076] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0077] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0078] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0079] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0080] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0081] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0082] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0083] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0084] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0085] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0086] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0087] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0088] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0089] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0090] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0091] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0092] Figure 6 An exemplary system for implementing a gate driver for closed loop non-overlapping of a phase switching device according to one or more embodiments is depicted. Figure 7 Depicted are exemplary waveform diagrams for a closed loop non-overlapping implementation of a gate driver for a phase switching device in accordance with one or more embodiments.

[0093] Figure 6Includes a command channel for transferring on / off control signals from the low voltage domain to the high voltage domain. Figure 6 A modified half-H switch environment is shown where the message channel is not shown and the command channel includes hardware that allows data to flow from the high voltage domain to the low voltage domain by reusing the command channel instead of using a dedicated real-time FET state feedback channel. Figure 6 and Figure 7 One or more embodiments are described by way of example using the following architecture and operations.

[0094] The system 600 may include a PWM controller 603, an upper phase gate driver 601 for an upper phase switch 644, and a lower phase gate driver 602 for a lower phase switch 648. The upper phase switch 644 and the lower phase switch 648 may be connected to a phase 690 of the motor 190 and a terminal 695 of the battery 195. For example, the PWM controller 603 may be a specific implementation of the inverter controller 300. For example, the upper phase switch 644 may be a specific implementation of the upper phase switch 144. For example, the lower phase switch 648 may be a specific implementation of the lower phase switch 148. The upper phase gate driver 601 may include a low voltage upper phase controller 620 and a high voltage upper phase controller 630 separated by an electrical isolator 650. For example, the low voltage upper phase controller 620 may be an implementation of the low voltage upper phase controller 120, the high voltage upper phase controller 630 may be an implementation of the high voltage upper phase controller 130 and the point of use upper phase controller 142, and the electrical isolator 650 may be an implementation of the electrical isolator 150. The lower phase gate driver 602 may include a low voltage lower phase controller 625 and a high voltage lower phase controller 635 separated by an electrical isolator 655. For example, the low voltage lower phase controller 625 may be an implementation of the low voltage lower phase controller 125, the high voltage lower phase controller 635 may be an implementation of the high voltage lower phase controller 135 and the point of use lower phase controller 146, and the electrical isolator 655 may be an implementation of the electrical isolator 150. The lower phase gate driver 602 may be similar to the upper phase gate driver 601, and thus the system 600 may be described with reference to the upper phase gate driver 601.

[0095] The PWM controller 603 may provide a PWM upper signal 605 to a low voltage upper phase controller 620, and a PWM lower signal 606 to a low voltage lower phase controller 625. The low voltage upper phase controller 620 may include an upper PWM comparator 611 and an upper enable latch 616. The low voltage lower phase controller 625 may include a lower PWM comparator 641 and a lower enable latch 646. An upper enable 681 output from the upper enable latch 616 may be connected to an input of the lower PWM comparator 641, and a lower enable 682 output from the lower enable latch 646 may be connected to an input of the upper PWM comparator 611.

[0096] For example, the upper PWM comparator 611 can be an AND gate and can assert an output high when both the PWM upper signal 605 and the lower enable 682 signal are high. The high output from the upper PWM comparator 611 can reset the upper enable latch 616 to assert the upper enable 681 to a low state, and thereby prevent the lower PWM comparator 641 from asserting a high output. For example, the lower PWM comparator 641 can be an AND gate and can assert an output high when both the PWM lower signal 606 and the upper enable 681 signal are high. The high output from the lower PWM comparator 641 can reset the lower enable latch 646 to assert the lower enable 682 to a low state, and thereby prevent the upper PWM comparator 611 from asserting a high output.

[0097] The low voltage upper phase controller 620 may include an upper PWM comparator 611, an LV pulse generator 612, an LV inverter 612A, a first LV transmitter 613A, a second LV transmitter 613B, an LV receiver 614, an LV demodulator 615, an upper enable latch 616, a round trip timer 617, and an overlap comparator 618. When the output of the upper PWM comparator 611 is high, the LV pulse generator 612 may generate a pulse stream. The first LV transmitter 613A may transmit the pulse stream from the LV pulse generator 612 through the electrical isolator 650. The LV inverter 612A may invert the pulse stream from the LV pulse generator 612, and the second LV transmitter 613B may transmit the inverted pulse stream through the electrical isolator 650. Here, the inverted pulse stream is a copy of the original pulse stream, but in an inverted form. The LV receiver 614 may receive the transmission from the electrical isolator 650. LV demodulator 615 may demodulate the received transmission into an input for setting upper enable latch 616 .

[0098] The high voltage upper phase controller 630 may include an HV receiver 671, an HV demodulator 672, an HV off state detector 673, an HV pulse generator 674, an HV inverter 674A, a first HV transmitter 675A, and a second HV transmitter 675B. The HV receiver 671 may receive a transmission from the electrical isolator 650. The HV demodulator 672 may demodulate the received transmission into an input of the upper phase switching element 644. The HV off state detector 673 may detect when the upper phase switching element 644 transitions from an on state to an off state. When the output of the HV off state detector 673 is high, the HV pulse generator 674 may generate a pulse burst. The first HV transmitter 675A may transmit a pulse burst from the HV pulse generator 674 through the electrical isolator 650. The HV inverter 674A may invert the pulse bursts from the HV pulse generator 674 , and the second HV transmitter 675B may transmit the inverted pulse bursts to the LV receiver 614 through the galvanic isolator 650 .

[0099] The system 600 may be referenced as follows Figure 6 and Figure 7 At initialization (i.e., the far left of waveform 700), both the PWM upper signal 605 and the PWM lower signal 606 can be logic low, and both the upper phase switching element 644 and the lower phase switching element 648 can be in the off state, as indicated by both the upper PWM signal 705 (from the PWM upper signal 605) and the lower PWM signal 725 (from the PWM lower signal 606) being low, and both the upper FET off signal 715 (from the HV off state detector 673) and the lower FET off signal 735 (from the lower related off state detector) being logic high. At initialization, both the upper FET output signal 720 (from the upper enable 681) and the lower FET output signal 740 (from the lower enable 682) are logic high.

[0100] Here, the upper PWM comparator 611 and the lower PWM comparator 641 each have a logic high input from the lower enable latch 646 and the upper enable latch 616, respectively, and have a logic low input from the PWM upper signal 605 and the PWM lower signal 606, respectively. This state allows the upper phase switch 644 or the lower phase switch 648 to be commanded to turn on via the PWM logic high state.

[0101] At the beginning of cycle 760, the lower PWM signal 725 changes from logic low to logic high, and the upper PWM signal 705 remains logic low. The lower PWM comparator 641 compares the logic high from the lower PWM signal 725 and the logic high from the upper FET output signal 720, and asserts the output signal high, which causes the lower LV pulse generator to generate a lower pulse 730, which travels upstream from the low voltage lower phase controller 625 through the electrical isolator 655 to the high voltage lower phase controller 635. At the same time, the output signal high at the output of the lower PWM comparator 641 resets the lower enable latch 646, causing the lower FET output signal 740 (lower enable 682) to be set to a logic low state (logic 0). The logic low state of the lower FET output signal 740 (lower enable 682) immediately places a logic zero at the input of the upper PWM comparator 611, which prevents the logic high state on the upper PWM signal 705 (PWM upper signal 605) from passing through the upper PWM comparator 611. This prevention ensures that the upper phase switch 644 is maintained in the off state.

[0102] At the same time, the high voltage lower phase controller 635 receives the lower pulse 730 and converts the pulse to a logic high signal with the HV demodulator, which drives the lower phase switch 648 to the on state, as indicated by the rising edge on the lower FET turn-off signal 735. At the beginning of cycle 765, the lower PWM signal 725 transitions to a low state. The output of the lower PWM comparator 641 is now a logic low and the low voltage lower phase controller 625 stops sending the lower pulse 730 to the high voltage lower phase controller 635. The lack of pulses across the galvanic isolator 655 is detected by the high voltage lower phase controller 635, the demodulated output transitions to a logic low, and the lower phase switch 648 is commanded to turn off.

[0103] The HV off state detector 673 detects the active state of the upper phase switch 644 (and the HV off state detector of the lower phase gate driver 602 similarly detects the active state of the lower phase switch 648). The HV off state detector 673 may use one or more different methods to determine the active state of the upper phase switch 644. One example would be to measure the gate to source voltage of the upper phase switch 644 if the upper phase switch 644 is a FET, such as Figure 6 As shown in the example shown. One example would be to measure the switch gate to emitter voltage if the upper phase switch 644 is an IGBT. For example, one example would be to measure the magnitude and / or direction of the current flowing through the upper phase switch 644 by measuring the voltage drop across a series resistor placed between the switch output and phase 690, or by measuring a representative percentage of the switch current using a parallel switch.

[0104] like Figure 7 As shown, after the logic low state of the lower PWM signal 725 and the lower pulse 730, the lower FET off signal 735 shows a transition from a logic low state to a logic high state, which occurs when the HV off state detector determines that the lower phase switching element 648 has successfully transitioned to the off state. The HV pulse generator responds to the rising edge of the off state detector signal 735 by asserting a short burst pulse (see "FET off signal" in the lower pulse 730) from the high voltage lower phase controller 635 downstream through the electrical isolator 655 to the low voltage lower phase controller 625. The duration of the pulse burst is intentionally limited and is not a continuous stream of pulses. The duration of the pulse burst is long enough so that the pulse burst can be detected by the low voltage lower phase controller 625. A typical pulse burst duration can be from about 100nS to about 300nS.

[0105] The downstream short pulse burst in the lower pulse 730 is demodulated by the LV demodulator, which asserts a logic high output to set the lower enable latch 646 to assert the lower FET output signal 740 to a logic high, as shown in cycle 765. The logic high on the lower enable 682 is input to the upper PWM comparator 611. Due to the successful closed loop response of the lower phase switch 648 to the commanded off cycle, the upper phase switch 644 is now enabled for use, as shown by the long arrow from the lower FET output signal 740 to the upper PWM signal 705 that starts cycle 770. The round trip timer records and stores the time between the output of the lower PWM comparator 641 transitions to a logic low (i.e., after the lower PWM signal 725 transitions to a logic low at the beginning of cycle 765) to the time when the lower enable 682 is asserted to a logic high (i.e., the lower FET output signal 740 transitions to a logic high near the end of cycle 765).

[0106] The operation of the upper phase gate driver 601 is the same as that of the lower phase gate driver 602 .

[0107] At the end of period 765, both the PWM upper signal 605 and the PWM lower signal 606 may be logic low, and both the upper phase switching element 644 and the lower phase switching element 648 may be in the off state, as indicated by both the upper PWM signal 705 (from the PWM upper signal 605) and the lower PWM signal 725 (from the PWM lower signal 606) being low, and both the upper FET off signal 715 (from the HV off state detector 673) and the lower FET off signal 735 (from the lower related off state detector) being logic high. At the end of period 765, both the upper FET output signal 720 (from the upper enable 681) and the lower FET output signal 740 (from the lower enable 682) are logic high.

[0108] Here, the upper PWM comparator 611 and the lower PWM comparator 641 each have a logic high input from the lower enable latch 646 and the upper enable latch 616, respectively, and have a logic low input from the PWM upper signal 605 and the PWM lower signal 606, respectively. This state allows the upper phase switch 644 or the lower phase switch 648 to be commanded to turn on via the PWM logic high state.

[0109] At the beginning of cycle 770, the upper PWM signal 705 changes from logic low to logic high, and the lower PWM signal 725 remains logic low. The upper PWM comparator 611 compares the logic high from the upper PWM signal 705 and the logic high from the lower FET output signal 740, and asserts the output signal high based on the comparison, which causes the LV pulse generator 612 to generate an upper pulse 710, which travels upstream from the low voltage upper phase controller 620 to the high voltage upper phase controller 630 through the electrical isolator 650. More specifically, the LV pulse generator 612 receives the output signal high from the upper PWM comparator 611 and generates the upper pulse 710. The first LV transmitter 613A and the second LV transmitter 613B send the upper pulse 710 and the inverted pulse (from the LV inverter 612A) to the HV receiver 671 through the electrical isolator 650.

[0110] At the same time, the output signal high at the output of the upper PWM comparator 611 resets the upper enable latch 616, causing the upper FET output signal 720 (upper enable 681) to be set to a logic low state (logic 0). The logic low state of the upper FET output signal 720 (upper enable 681) immediately places a logic 0 at the input of the lower PWM comparator 641, which prevents the logic high state on the lower PWM signal 725 (PWM lower signal 606) from passing through the lower PWM comparator 641. This prevention ensures that the lower phase switch 648 is maintained in the off state.

[0111] At the same time, the HV receiver 671 of the high voltage upper phase controller 630 receives the upper pulse 710 and converts the pulse to a logic high signal with the HV demodulator 672, which drives the upper phase switch 644 to the on state, as indicated by the falling edge on the upper FET turn-off signal 715. At the beginning of cycle 775, the upper PWM signal 705 transitions to a low state. The output of the upper PWM comparator 611 is now a logic low and the LV pulse generator 612 stops sending the upper pulse 710 to the high voltage upper phase controller 630. The lack of pulses across the galvanic isolator 650 is detected by the HV receiver 671 of the high voltage upper phase controller 630, the demodulated output of the HV demodulator 672 transitions to a logic low, and commands the upper phase switch 644 to turn off.

[0112] like Figure 7 As shown, after transitioning to the logic low state of the upper PWM signal 705 and the upper pulse 710, the upper FET off signal 715 shows a transition from a logic low state to a logic high state, which occurs when the HV off state detector 673 determines that the upper phase switching element 644 has successfully transitioned to the off state. The HV pulse generator 674 responds to the successful switching element transition to the off state from the HV off state detector 673 by asserting a short burst pulse (see "FET off signal" in the upper pulse 710) from the high voltage upper phase controller 630 downstream through the electrical isolator 650 to the low voltage upper phase controller 620. More specifically, the first HV transmitter 675A and the second HV transmitter 675B send the upper pulse 710 and the inverted pulse (from the HV inverter 674A) to the LV receiver 614 through the electrical isolator 650. The duration of the pulse burst is intentionally limited and is not a continuous stream of pulses. The duration of the pulse burst is long enough so that the pulse burst can be detected by the LV receiver 614. A typical pulse burst duration may be from about 100 nS to about 300 nS.

[0113] The downstream short pulse burst is demodulated by the LV demodulator 615, which asserts a logic high output to set the upper enable latch 616 to assert the upper FET output signal 720 to a logic high, as shown in cycle 775. The logic high on the upper enable 681 is input to the lower PWM comparator 641. Due to the successful closed loop response of the upper phase switch 644 to the commanded off cycle, the lower phase switch 648 is now enabled for use, as shown by the short arrow from the upper FET output signal 720 to the lower PWM signal 725 that ends cycle 775. The round trip timer 617 records and stores the time between the time when the output of the upper PWM comparator 611 transitions to a logic low (i.e., after the upper PWM signal 705 transitions to a logic low at the beginning of cycle 775) to the time when the upper enable 681 is asserted to a logic high (i.e., the time when the upper FET output signal 720 transitions to a logic high near the end of cycle 775).

[0114] Period 760 “ON” and period 765 “Non-overlap” may be associated with the on state and off state of the lower phase switch 648, respectively. Period 770 “ON” and period 775 “Non-overlap” may be associated with the on state and off state of the upper phase switch 644, respectively. For the lower phase switch 648, “Non-overlap” may refer to a time period after the lower PWM signal 725 transitions to a logic low, which is reserved so that the lower phase switch 648 is successfully turned off before the upper PWM signal 705 is asserted to a logic high. For the upper phase switch 644, “Non-overlap” may refer to a time period after the upper PWM signal 705 transitions to a logic low, which is reserved so that the upper phase switch 644 is successfully turned off before the lower PWM signal 725 is asserted to a logic high.

[0115] like Figure 6 As shown, the PWM controller 603 generating the upper PWM signal 705 and the lower PWM signal 725 cannot directly observe the upper enable 681 and the lower enable 682. However, the present disclosure is not limited thereto, and one or more signals from the low voltage upper phase controller 620 and the low voltage lower phase controller 625 may be sent to the PWM controller 603 so that decisions made by the PWM controller 603 regarding the PWM logic state may be processed based on one or more signals from the low voltage upper phase controller 620 and the low voltage lower phase controller 625, such as to notify the PWM controller 603 that a non-overlap violation has occurred and that the asserted command-on signal from the PWM controller 603 has been delayed or blocked. Such information may allow the PWM controller 603 to take corrective action.

[0116] Scenarios for non-overlap implementation and responses to non-overlap violations are discussed below to further explain one or more embodiments. The following cases 1 to 6 are similar when applied to the upper phase gate driver 601 or the lower phase gate driver 602 .

[0117] Case 1: The non-overlap time is a fixed time determined by the PWM controller 603 and is longer than the absolute worst case feedback loop time, and the non-overlap violation never occurs. Here, the lower FET output signal 740 is asserted as logic high before the PWM controller 603 asserts the upper PWM signal 705 as logic high. The upper FET output signal 720 is asserted as logic high before the PWM controller 603 asserts the lower PWM signal 725 as logic high.

[0118] Case 2: Same as Case 1, except that the lower round trip time for the commanded off event exceeds the fixed non-overlap time determined by the PWM controller 603 in Case 1. Here, when the upper PWM signal 705 reaches a logic high, the lower FET output signal 740 is a logic low. The overlap comparator 618 records the non-overlap violation and uses a timer to determine the duration of the non-overlap violation. The lower phase switch 648 reaches a commanded off and the lower FET output signal 740 is set to a logic high. The upper PWM signal 705 is a logic high and the lower FET output signal 740 is a logic high. After being delayed for the non-overlap violation time, the upper PWM signal 705 is sent to the upper phase switch 644. The non-overlap violation timer records the non-overlap violation time for diagnostic analysis.

[0119] Case 3: Same as Case 2, except that the output of the overlap comparator 618 is directed to the PWM controller 603, which is immediately notified that a non-overlap violation has occurred.

[0120] Case 4: Same as Case 2, except that the lower FET output signal 740 is directed to the PWM controller 603, which can then check immediately to see if a non-overlap violation will occur before asserting the upper PWM signal 705 to a high state.

[0121] Case 5: Both the upper FET output signal 720 and the lower FET output signal 740 are logic high, and both the upper PWM signal 705 and the lower PWM signal 725 are logic low, so that the upper phase switch 644 or the lower phase switch 648 can be turned on, and then the upper PWM signal 705 and the lower PWM signal 725 are set to logic high at the same time due to a fault in the system 600. Here, the upper FET output signal 720 and the lower FET output signal 740 are in a race condition, where one of the signals will be asserted to logic high before the other due to variations within the components of the system 600. The first of the upper FET output signal 720 and the lower FET output signal 740 to reach logic high will clear the associated latch. The first latch to be cleared to 0 will feed a logic 0 back to the relative PWM comparator (upper PWM comparator 611 or lower PWM comparator 641). The presence of a logic 0 at the input of the relative PWM comparator will implement the PWM comparator output as a logic low. There is a possibility that due to a race condition, the relative PWM comparator output may have briefly reached a logic high state, but the period of time will be very brief and will be followed by a logic low condition. The result of the above operation is that the race condition will resolve to one switch (upper phase switch 644 or lower phase switch 648) being enabled to be commanded on, and the relative switch being blocked from being commanded on. Non-overlap protection has been successfully demonstrated under the worst case condition of asserting the PWM upper signal 605 and the PWM lower signal 606 at the same time.

[0122] Case 6: Same as case 5, except that the upper PWM signal 705 high assertion occurs before or after the lower PWM signal 725 high assertion. This case will resolve itself so that the first side asserting a PWM logic high will prevent the opposite side from being commanded on.

[0123] As described above, one or more embodiments may provide a closed-loop feedback system that uses an electrically isolated channel to eliminate the increased cost and defect-related failure mechanisms associated with two electrically isolated channels. One or more embodiments may solve the problem of open-loop non-overlapping implementation and the problem of two-channel closed-loop non-overlapping implementation. One or more embodiments may use an electrical command channel to transmit the off state of the switching element at a time point when the channel no longer transmits the on-state command, and may use a burst of electrical pulses that lasts only long enough to transmit the successful off state to transmit the off state of the switching element. One or more embodiments may include a round-trip timer. One or more embodiments may include a non-overlap detector. One or more embodiments may include one less electrical channel per switching element than some designs. For example, for a three-phase inverter using six switching element channels, one or more embodiments may save a total of six electrical channels compared to some designs. Each electrical channel may require area within an integrated circuit or may require external components to implement, and therefore one or more embodiments may be cheaper than some designs and have a lower probability of failure associated with defects. One or more embodiments may include active non-overlapping violation detection and round-trip timer diagnosis, which is an advantage over some designs. One or more embodiments may provide closed-loop feedback useful for preventing shoot-through events by requiring confirmation of the off-state of the switching element to enable commands to the relative switching element. One or more embodiments may be optimally designed to use a single burst of downstream electrical data through an available command channel to indicate that a successful off-state of the switching element has been reached to enable commands to turn on the relative switching element. One or more embodiments may provide a closed-loop non-overlapping implementation architecture that ensures that the on-state phase switching element is disconnected before the complementary off-state phase switching element is allowed to turn on. One or more embodiments may support a minimum off-time or minimum non-overlapping time of approximately 1 μS. One or more embodiments may provide closed-loop feedback using an electrical channel.

[0124] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a first electrical interface configured to separate a first high voltage region from a low voltage region; a first low voltage controller, the first low voltage controller being in the low voltage region, the first low voltage controller being configured to receive a first PWM signal from a PWM controller, and to send a first control signal to a first high voltage controller in the first high voltage region using the first electrical interface based on the first PWM signal; a second electrical interface configured to separate a second high voltage region from the low voltage region; and a second low voltage controller, wherein the second low voltage controller is in the low voltage region, the first low voltage controller is configured to receive a second PWM signal from the PWM controller, and send a second control signal to a second high voltage controller in the second high voltage region using the second electrical interface based on the second PWM signal, wherein the second low voltage controller is configured to provide an output latch signal to the first low voltage controller and receive an input latch signal from the first low voltage controller, and The output latch signal is based on the second PWM signal and the input latch signal.

2. The system according to claim 1, The first low voltage controller is further configured to receive a feedback signal from the first high voltage controller through the first electrical interface, and The input latch signal is based on the first PWM signal, the output latch signal and the feedback signal.

3. The system according to claim 2, The first low voltage controller is configured to use a group of communication lines in the first electrical interface to send the first control signal, and use the group of communication lines in the first electrical interface to receive the feedback signal. 4 . The system of claim 2 , wherein the first control signal is configured to control a phase switching element of an inverter, and the feedback signal is configured to indicate an off state of the phase switching element. 5 . The system of claim 2 , wherein the first low voltage controller is configured to record time based on the first PWM signal and the feedback signal. 6 . The system of claim 1 , wherein the first low voltage controller is configured to generate a fault based on the first PWM signal and the output latch signal. 7 . The system of claim 1 , wherein the output latch signal and the input latch signal enable the first PWM signal in the first low voltage controller and the second PWM signal in the second low voltage controller, respectively.

8. The system of claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

9. A system comprising: a high voltage controller, the high voltage controller being arranged in a high voltage area separated from a low voltage area by an electrical interface including a command channel and a message channel, the high voltage controller being arranged to receive a control signal from a low voltage controller in the low voltage area using the command channel of the electrical interface, to control a phase switching element based on the control signal, and to send a switching element state signal to the low voltage controller using the command channel of the electrical interface, The high voltage controller is configured to control the switching element state signal based on the state of the phase switching element.

10. The system of claim 9, wherein the high voltage controller is configured to send the switch status signal using the command channel of the electrical interface when the high voltage controller is not receiving the control signal from the command channel of the electrical interface.

11. The system of claim 9, wherein the high voltage controller is configured to send the switch status signal by sending a burst of electrical pulses on the command channel of the electrical interface.

12. The system of claim 9, wherein the high voltage controller comprises one or more point-of-use controllers on a power module having the phase switching element.

13. The system of claim 9, wherein the high voltage controller is configured to send the control signal to one or more point-of-use controllers on a power module having the phase switching element, and receive the switching element status signal from the one or more point-of-use controllers.

14. The system of claim 9, wherein the high voltage controller is further configured to invert the switching element state signal and use the command channel of the electrical interface to send the switching element state signal and the inverted switching element state signal to the low voltage controller.

15. A system comprising: an electrical interface configured to separate a high voltage region from a low voltage region; A low voltage controller, wherein the low voltage controller is in the low voltage region, and the low voltage controller comprises: a PWM comparator configured to receive a PWM signal and an input latch signal, and generating a PWM comparator signal based on a comparison of the PWM signal and the input latch signal, a low voltage pulse generator configured to generate an upstream pulse based on the PWM comparator signal, a low voltage transmitter configured to send the upstream pulse to the electrical interface, a low voltage receiver configured to receive downstream pulses from the electrical interface, a low voltage demodulator configured to generate a low voltage demodulated signal based on the downstream pulse, and an enable latch configured to be set with the low voltage demodulation signal and reset with the PWM comparator signal, the enable latch further configured to provide an output latch signal; and A high voltage controller, wherein the high voltage controller is in the high voltage region, and the high voltage controller comprises: a high voltage receiver configured to receive the upstream pulse from the electrical interface, a high voltage demodulator configured to generate a high voltage demodulation signal based on the upstream pulse, the high voltage demodulation signal configured to control a phase switching element, a high voltage off-state detector configured to detect an off-state of the phase switching element, a high voltage pulse generator configured to generate the downstream pulse based on the detected off state of the phase switching element, and A high voltage transmitter is configured to send the downstream pulse to the electrical interface.

16. The system of claim 15, wherein the high voltage controller comprises one or more point-of-use controllers on a power module having the phase switching element.

17. The system of claim 15, wherein the low voltage controller further comprises: A round trip timer is configured to record a time from when the PWM signal becomes a logic low to when the output latch signal becomes a logic high.

18. The system of claim 15, wherein the low voltage controller further comprises: An overlap comparator is configured to generate a fault when the PWM signal is logic high and the input latch signal is logic low.

19. The system of claim 15, wherein the high voltage controller further comprises: A high voltage inverter is configured to invert the downstream pulses to the high voltage transmitter.

20. The system of claim 15, wherein the low voltage controller further comprises: A low voltage inverter is configured to invert the upstream pulse to the low voltage transmitter.

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