Storage device

Abstract

A storage device that can be highly integrated is provided. The memory device includes: a first transistor; and a second transistor on the first transistor, the first transistor including: a first oxide semiconductor on a substrate; a first conductor and a second conductor separated from each other on the first oxide semiconductor; a first insulator disposed on the first conductor and the second conductor and including an opening overlapping a region between the first conductor and the second conductor; a second insulator disposed in the opening of the first insulator and disposed on the first oxide semiconductor; and a third conductor disposed on the second insulator in the opening. The second transistor includes: a third insulator disposed on the first insulator and the third conductor and including an opening; a fourth conductor disposed on the third insulator and including an opening overlapping the opening of the third insulator; a second oxide semiconductor disposed in the openings of the third insulator and the fourth conductor; a fourth insulator disposed on the second oxide semiconductor in the opening; and a fifth conductor disposed on the fourth insulator in the opening. A part of the second oxide semiconductor passes through the third insulator and is electrically connected to the third conductor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors, etc.), input-output devices (e.g., touch panels, etc.), their driving methods, or their manufacturing methods.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or storage devices are one form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, and electronic devices sometimes include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices such as LSI (Large Scale Integration), CPU (Central Processing Unit), and memory (storage device) have been developed. These semiconductor devices are used in various electronic devices such as computers and portable information terminals. In addition, various storage methods have been developed for purposes such as temporary storage during the execution of calculations and long-term storage of data. Typical storage methods include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and flash memory.

[0005] In addition, as the amount of data to be processed increases, semiconductor devices with larger storage capacity are required. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors.

[0006] In addition, in order to increase the storage capacity of semiconductor devices, miniaturization of transistors in semiconductor devices is being carried out. In order to achieve miniaturization of transistors, research on vertical transistors is becoming increasingly hot. For example, non-patent documents 2 and 3 disclose a vertical transistor containing a metal oxide in a region where a channel is formed (also referred to as a channel formation region). [Prior technical literature] [Patent Document]

[0007] [Patent Document 1] International Patent Application Publication No. 2021 / 053473 [Non-patent literature]

[0008] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 [Non-patent document 2] X.Duan et al., “Novel Vertical Channel-All-Around (CAA) IGZOFETs for 2T0C DRAM with High Density beyond 4F 2 by Monolithic Stacking", IEDMTech.Dig., 2021, pp.222-225 [Non-patent document 3] H.Fujiwara et.al, "Surrounding Gate Vertical-Channel FET with Gate Length of 40nm Using BEOL Compatible High-Thermal-Tolerance In-Al-Zn Oxide Channel", 2020Symposium on VLSI Technology: Digest of Technical Papers, pp.1-2, TH2.2 Summary of the invention Technical problem to be solved by the invention

[0009] One of the purposes of one embodiment of the present invention is to provide a storage device that can be miniaturized or highly integrated. One of the purposes of one embodiment of the present invention is to provide a storage device with a large storage capacity. One of the purposes of one embodiment of the present invention is to provide a storage device that occupies a small area. One of the purposes of one embodiment of the present invention is to provide a storage device with high reliability. One of the purposes of one embodiment of the present invention is to provide a storage device with low power consumption. One of the purposes of one embodiment of the present invention is to provide a novel storage device.

[0010] Note that the description of these objectives does not prevent the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Objectives other than the above objectives can be extracted from the description of the specification, drawings, and claims. Solutions to technical problems

[0011] One embodiment of the present invention is a storage device, which includes: a first transistor; and a second transistor on the first transistor, the first transistor including: a first oxide semiconductor; a first conductor and a second conductor separated from each other on the first oxide semiconductor; a first insulator arranged on the first conductor and the second conductor and including an opening located between the first conductor and the second conductor; a second insulator arranged in the opening of the first insulator and arranged on the first oxide semiconductor; and a third conductor arranged in the opening of the first insulator and arranged on the second insulator, the second transistor including: a third insulator arranged on the first insulator and the third conductor and including an opening overlapping with the first oxide semiconductor; a fourth conductor arranged on the third insulator and including an opening overlapping with the opening of the third insulator; a second oxide semiconductor arranged in the openings of the third insulator and the fourth conductor; a fourth insulator arranged on the second oxide semiconductor in the openings of the third insulator and the fourth conductor; and a fifth conductor arranged on the fourth insulator in the openings of the third insulator and the fourth conductor, the second oxide semiconductor passes through the third insulator and is electrically connected to the third conductor.

[0012] In the above memory device, preferably, a sixth conductor is arranged under the second oxide semiconductor, the opening of the third insulator reaches the sixth conductor, and the sixth conductor is in contact with a portion of the second oxide semiconductor and electrically connected to the third conductor.

[0013] Furthermore, in the above-mentioned storage device, preferably, the fourth conductor is used as one of the source electrode and the drain electrode of the second transistor, the fifth conductor is used as the gate electrode of the second transistor, and the sixth conductor is used as the other of the source electrode and the drain electrode of the second transistor.

[0014] Furthermore, in the above-described memory device, preferably, a channel length of the second transistor is smaller than at least a channel width of the second transistor.

[0015] Furthermore, in the above storage device, preferably, a seventh conductor is included in contact with a top surface of the fifth conductor, the fourth conductor extends in a first direction, the seventh conductor extends in a second direction, and the first direction and the second direction intersect each other.

[0016] Furthermore, in the above-described memory device, preferably, another portion of the second oxide semiconductor, a portion of the fourth insulator, and a portion of the fifth conductor are located on the fourth conductor.

[0017] Furthermore, in the above-described memory device, preferably, another portion of the second oxide semiconductor is in contact with a top surface of the fourth conductor.

[0018] Furthermore, in the above-described memory device, preferably, a portion of the fourth insulator covers another portion of the second oxide semiconductor.

[0019] In the above semiconductor device, preferably, the openings of the third insulator and the fourth conductor have a circular shape or a substantially circular shape when viewed from a plan view.

[0020] In the above semiconductor device, it is preferred that the second oxide semiconductor contains any one or more selected from In, Ga, and Zn.

[0021] In the above-mentioned semiconductor device, preferably, the third insulator has a stacked structure, the stacked structure includes a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer contains silicon and nitrogen, the second layer contains silicon and oxygen, and the third layer contains silicon and nitrogen.

[0022] In the above semiconductor device, it is preferred that the first oxide semiconductor contains any one or more selected from In, Ga, and Zn. Effects of the Invention

[0023] According to one embodiment of the present invention, a storage device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device that occupies a small area can be provided. According to one embodiment of the present invention, a storage device with high reliability can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel storage device can be provided.

[0024] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A It is a perspective view showing a structural example of a storage device. Figure 1B This is a circuit diagram for explaining the structure of a storage device. Figure 2A and Figure 2B It is a perspective view showing a structural example of a storage device. Figure 3A and Figure 3B is a cross-sectional view showing a structural example of a storage device. Figure 4A and Figure 4B is a cross-sectional view showing a structural example of a storage device. Figure 5A and Figure 5Bis a cross-sectional view showing a structural example of a storage device. 6A to 6F is a cross-sectional view showing a structural example of a storage device. 7A to 7F is a cross-sectional view showing a structural example of a storage device. Figure 8 is a cross-sectional view showing a structural example of a storage device. Fig.9A is a plan view showing an example of a semiconductor device. FIG. 9B to FIG. 9D is a cross-sectional view showing an example of a semiconductor device. Fig. 10A and Fig. 10B is a cross-sectional view showing an example of a semiconductor device. Fig.11A and Fig. 11B is a cross-sectional view showing an example of a semiconductor device. Fig. 12A and Fig. 12B is a cross-sectional view showing an example of a semiconductor device. FIG. 13A to FIG. 13E is a cross-sectional view showing an example of a semiconductor device. FIG. 14A to FIG. 14D is a cross-sectional view showing an example of a semiconductor device. FIG. 15A to FIG. 15D is a cross-sectional view showing an example of a semiconductor device. Fig.16A and Fig. 16B is a cross-sectional view showing an example of a semiconductor device. Fig.17A is a block diagram showing a structural example of a storage device. Fig. 17B It is a perspective view showing a structural example of a storage device. Fig.18A and Fig.18B is a circuit diagram showing a structural example of a memory cell. Fig.18C and Fig.18D It is a perspective view showing a structural example of a storage device. Fig.19A and Fig.19B is a diagram showing an example of a semiconductor device. Fig. 20A and Fig. 20B It is a diagram showing an example of an electronic component. FIG. 21A to FIG. 21E This is a schematic diagram of a storage device according to one embodiment of the present invention. Fig.22A and Fig. 22B is a diagram showing an example of an electronic device, FIG. 22C to FIG. 22E This is a diagram showing an example of a large computer. Fig.23 is a diagram showing an example of space equipment. Fig.24 is a diagram showing an example of a storage system that can be used in a data center. Modes for Carrying Out the Invention

[0026] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0027] Note that in the structure of the invention described below, the same reference numeral is used in common between different drawings to represent the same part or part having the same function, and its repeated description is omitted. In addition, when representing a part having the same function, the same hatching is sometimes used without adding a reference numeral in particular.

[0028] In addition, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings.

[0029] In this specification, etc., for convenience, ordinal numbers such as "first" and "second" are used, but such ordinal numbers do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, sometimes the ordinal numbers attached to components in one part of this specification are inconsistent with the ordinal numbers attached to the components in another part of this specification or in the claims.

[0030] Note that in this specification, etc., “insulator” may be referred to as “insulating film” or “insulating layer”. Also, “conductor” may be referred to as “conductive film” or “conductive layer”. Also, “semiconductor” may be referred to as “semiconductor film” or “semiconductor layer”.

[0031] In this specification, etc., "oxynitride" refers to a material whose oxygen content is higher than the nitrogen content in its composition, and "nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content in its composition. For example, when "silicon oxynitride" is described, it refers to a material whose oxygen content is higher than the nitrogen content in its composition, and when "silicon nitride oxide" is described, it refers to a material whose nitrogen content is higher than the oxygen content in its composition.

[0032] In this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper", "lower", "above" or "below" are sometimes used to explain the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each structure is described. Therefore, the words and phrases described in this specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be called "an insulator located below the conductor".

[0033] In this specification, etc., "high consistency" refers to a structure in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal when viewed from a cross section. For example, in the manufacturing process of a semiconductor device, a flattening process (typically a CMP process) is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the height of the processed surface by the CMP process is equal to the height of the reference surface. Note that depending on the processing device, processing method or material of the processed surface during the CMP process, the heights of multiple layers are sometimes different. In this specification, etc., "high consistency" also includes the above situation. For example, in the case where there are two layers with heights relative to the reference surface (here, the first layer and the second layer), when the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is less than 20nm, it is also referred to as "high consistency".

[0034] In this specification, etc., "ends coincide" means that at least a portion of the outlines of each layer in the stack overlap when viewed from above. For example, it refers to a case where the upper layer and the lower layer are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is located inside the outline of the lower layer or the outline of the upper layer is located outside the outline of the lower layer, and these cases are also included in the case of "ends coincide".

[0035] Note that, in general, it is difficult to clearly distinguish between “completely consistent” and “substantially consistent.” Therefore, in this specification, “consistent” includes both completely consistent and substantially consistent.

[0036] (Implementation Method 1) In this embodiment, referring to FIGS. 1 to Figure 8 A storage device according to one embodiment of the present invention will be described.

[0037] One embodiment of the present invention relates to a memory device provided on a substrate. The memory device includes a first transistor and a second transistor, and a memory cell can be formed using these transistors. The memory device of one embodiment of the present invention has a function of storing data.

[0038] A storage device of one embodiment of the present invention preferably includes two transistors (OS transistors) containing metal oxide in a channel formation region. The off-state current of the OS transistor is very small. Therefore, by using the OS transistor in the storage device, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be substantially reduced. Therefore, a storage device with low power consumption can be provided. In addition, since the frequency characteristics of the OS transistor are high, the storage device can read and write data at a high speed. Therefore, a storage device with a fast operating speed can be provided.

[0039] <Configuration Example of Storage Device> A configuration example of a storage device according to one embodiment of the present invention will be described below.

[0040] Figure 1A : is a perspective view showing a structural example of a storage device according to one embodiment of the present invention. Figure 1B is corresponding to Figure 1A The circuit diagram of the storage device is shown. In addition, Figure 2A The stereogram shown is a cut along a plane including the dot-dash line A1-A2. Figure 1A In addition, Figure 2B The stereogram shown is a cut along a plane including the dot-dash line A3-A4. Figure 1A In addition, Figure 3A : is a cross-sectional view of the storage device corresponding to the portion indicated by the dot-dash line A1-A2. Figure 3B 2 is a cross-sectional view of the memory device corresponding to the portion indicated by the dot-dash line A3-A4. Note that the dot-dash line A1-A2 is a straight line parallel to the Y axis in the figure, and is also parallel to or substantially parallel to the channel length direction of the transistor 20. In addition, the dot-dash line A3-A4 is a straight line parallel to the X axis in the figure, and is also parallel to or substantially parallel to the channel width direction of the transistor 20. In addition, in the above-mentioned three-dimensional diagram, some components are omitted for easy understanding.

[0041] Note that arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings of this specification. Note that in this specification, "X direction" refers to the direction along the X axis, and sometimes does not distinguish between the forward and reverse directions except for the cases clearly stated. The same is true for "Y direction" and "Z direction". For example, the Z direction sometimes refers to the direction perpendicular to or approximately perpendicular to the substrate surface. In addition, the X direction, Y direction, and Z direction are directions that intersect each other. For example, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, one of the X direction, Y direction, and Z direction is sometimes referred to as the "first direction". In addition, the other one is sometimes referred to as the "second direction". In addition, the remaining one is sometimes referred to as the "third direction".

[0042] A memory device according to one embodiment of the present invention includes a transistor 20 and a transistor 40 on the transistor 20. The transistor 20 includes: an oxide semiconductor 22 on a substrate (not shown); a conductor 24a and a conductor 24b separated from each other on the oxide semiconductor 22; an insulator 34 disposed on the conductor 24a and the conductor 24b and including an opening between the conductor 24a and the conductor 24b; an insulator 28 disposed in the opening of the insulator 34 and disposed on the oxide semiconductor 22; and a conductor 26 disposed in the opening of the insulator 34 and disposed on the insulator 28.

[0043] In addition, the transistor 40 includes: a conductor 32c on the conductor 26; an insulator 52 disposed on the conductor 32c and including an opening overlapping with the oxide semiconductor 22; a conductor 44 disposed on the insulator 52 and including an opening overlapping with the opening of the insulator 52; the oxide semiconductor 42 disposed in the openings of the insulator 52 and the conductor 44; an insulator 48 disposed on the oxide semiconductor 42 in the openings of the insulator 52 and the conductor 44; and a conductor 46 disposed on the insulator 48 in the openings of the insulator 52 and the conductor 44. Here, a portion of the oxide semiconductor 42 passes through the insulator 52 and contacts the conductor 32c.

[0044] Note that Figure 3A and Figure 3B As shown in the figures, an insulator 36 is provided on the insulator 34. The conductors 30a and 30b are arranged in the openings formed in the insulator 34 and the insulator 36. In addition, the conductor 30c is arranged in the opening formed in the insulator 36. The conductor 30a is in contact with the top surface of the conductor 24a, the conductor 30b is in contact with the top surface of the conductor 24b, and the conductor 30c is in contact with the top surface of the conductor 26.

[0045] An insulator 38 is provided on the insulator 36. The conductor 32a, the conductor 32b, and the conductor 32c are arranged in the opening formed in the insulator 38. Here, the conductor 32a is in contact with the top surface of the conductor 30a, the conductor 32b is in contact with the top surface of the conductor 30b, and the conductor 32c is in contact with the top surface of the conductor 30c. In addition, an insulator 52 is provided on the insulator 38. In addition, an insulator 54 is provided on the insulator 52. The conductor 44 is arranged in the opening formed in the insulator 54.

[0046] In addition, an insulator 56 is provided on the insulator 54. In addition, a portion of the oxide semiconductor 42, a portion of the insulator 48, and a portion of the conductor 46 are arranged in the opening formed in the insulator 56. That is, a portion of the oxide semiconductor 42, a portion of the insulator 48, and a portion of the conductor 46 are located on the conductor 44. In addition, an insulator 58 is provided on the insulator 56. The conductor 50 is arranged in the opening formed in the insulator 58. Here, the conductor 50 is in contact with the top surface of the conductor 46.

[0047] Hereinafter, when describing the common contents between components distinguished by letters, the letters may be omitted for description. For example, when describing the common contents between conductor 24a and conductor 24b, conductor 24 may be described as conductor 24.

[0048] In the transistor 20, the conductor 26 is used as a gate electrode, the insulator 28 is used as a gate insulator, the conductor 24a is used as one of the source electrode and the drain electrode, and the conductor 24b is used as the other of the source electrode and the drain electrode. In addition, the conductor 32a is used as a wiring electrically connected to one of the source electrode and the drain electrode of the transistor 20, and the conductor 32b is used as a wiring electrically connected to the other of the source electrode and the drain electrode of the transistor 20.

[0049] In the transistor 20, the conductor 26 and the insulator 28 are formed in a self-aligned manner so as to fit into the opening formed by the insulator 34, the conductor 24a, and the conductor 24b. Thus, the conductor 26 can be arranged reliably without alignment in the region between the conductor 24a and the conductor 24b. Note that a detailed structural example of the transistor 20 will be described in Embodiment 2.

[0050] In transistor 40, conductor 46 is used as a gate electrode, insulator 48 is used as a gate insulator, conductor 44 is used as one of the source electrode and the drain electrode, and conductor 32c is used as the other of the source electrode and the drain electrode. In addition, conductor 44 is provided to extend in the Y direction and is used as a wiring electrically connected to one of the source electrode and the drain electrode. In addition, conductor 50 is provided to extend in the X direction and is used as a wiring electrically connected to the gate electrode. Therefore, the extension direction of conductor 44 intersects with the extension direction of conductor 50.

[0051] By adopting the above structure, the other of the source electrode and the drain electrode of the transistor 40 is electrically connected to the gate electrode of the transistor 20 through the conductor 30c. That is, the conductor 32c is electrically connected to the conductor 26. In addition, the oxide semiconductor 42 is electrically connected to the conductor 26. Here, the transistor 40 is a vertical transistor in which the channel formation region is formed in a manner parallel to the Z direction. Therefore, the conductor 32c used as the other of the source electrode and the drain electrode is formed at the lower part of the transistor 40. On the other hand, the conductor 26 used as the gate electrode of the transistor 20 is formed at the upper part of the transistor 20. Therefore, in the memory cell in which the other of the source electrode and the drain electrode of the transistor 40 is electrically connected to the gate electrode of the transistor 20, the transistor 40 can be electrically connected to the transistor 20 without providing redundant wiring or through-holes. As a result, the occupied area of ​​the memory cell can be reduced, so the memory cell can be configured with high density to increase the storage capacity of the memory device. In other words, high integration of the memory device can be achieved.

[0052] In addition, the oxide semiconductor 42 has a region in contact with the side surface of the conductor 44 and a region in contact with a portion of the top surface of the conductor 44 near the opening of the conductor 44. In this way, since the oxide semiconductor 42 is in contact with not only the side surface but also the top surface of the conductor 44, the area in contact between the oxide semiconductor 42 and the conductor 44 can be increased.

[0053] In addition, the transistor 40 preferably overlaps at least a portion of the transistor 20. For example, the oxide semiconductor 42 preferably overlaps at least a portion of the oxide semiconductor 22 via the conductor 26. By adopting such a structure, the transistor 20 and the transistor 40 can be arranged in a manner that does not significantly increase the occupied area when viewed from a plane. As a result, the occupied area of ​​the memory cell can be reduced, so the memory cell can be arranged at a high density to increase the storage capacity of the memory device.

[0054] Note that the above shows a structure in which the transistor 20 and the transistor 40 are connected via the conductor 32c and the conductor 30c, but the present invention is not limited thereto. Figure 4A and Figure 4B As shown, the oxide semiconductor 42 of the transistor 40 may also be in contact with the conductor 26 of the transistor 20. Figure 4A is corresponding to Figure 3A The picture, Figure 4B is corresponding to Figure 3B .

[0055] In this case, oxide semiconductor 42, insulator 48, and conductor 46 are arranged in openings formed in conductor 44, insulator 52, insulator 38, and insulator 36. Since the opening reaches conductor 26, insulator 28, and insulator 34, the bottom surface of oxide semiconductor 42 is in contact with the top surfaces of conductor 26, insulator 28, and insulator 34. By adopting such a structure, it is unnecessary to form conductor 30c and conductor 32c, so that the memory device can be miniaturized.

[0056] In addition, the memory device described in this embodiment includes the transistor 20 and the transistor 40 and is used as a memory cell. Figure 1B As shown, the gate electrode of transistor 40 is electrically connected to wiring WOL, one of the source electrode and the drain electrode is electrically connected to wiring WBL, and the other of the source electrode and the drain electrode is electrically connected to the gate electrode of transistor 20. One of the source electrode and the drain electrode of transistor 20 is electrically connected to wiring RBL, and the other of the source electrode and the drain electrode is electrically connected to wiring SL. In addition, the gate capacitance of transistor 20 is used as a storage capacitor. In other words, the storage device shown in this embodiment can also be called a capacitor-free storage cell. Therefore, it can be called a gain unit type storage cell with 2 transistors and 0 capacitor elements.

[0057] The wiring WOL is used as a write word line, the wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring SL is used as a select line.

[0058] The wiring WOL corresponds to the conductor 50 , the wiring WBL corresponds to the conductor 44 , the wiring RBL corresponds to the conductor 32 a , and the wiring SL corresponds to the conductor 32 b .

[0059] [Transistor 40] Below, refer to Figures 1A to 8 The structure of transistor 40 is described. Note that 6A to 6F , Fig. 7A , FIG. 7C to FIG. 7F and Figure 8 The transistor 40 shown is Figure 3A FIG. 4 is a diagram showing a partial variation of the structure of transistor 40. Figure 7B The transistor 40 shown is Figure 3B A variation of a portion of the structure of transistor 40 is shown.

[0060] like Figure 1AAs shown in FIG. 5 , the transistor 40 may include a conductor 32 c, a conductor 44 on an insulator 52, an oxide semiconductor 42 on the conductor 32 c, an insulator 48 provided in contact with the top surface of the oxide semiconductor 42, and a conductor 46 provided in contact with the top surface of the insulator 48. Here, the oxide semiconductor 42 is provided in contact with the top surface of the conductor 32 c exposed in the openings of the insulator 52 and the conductor 44, the side surfaces of the insulator 52 in the openings, the side surfaces of the conductor 44, and at least a portion of the top surface of the conductor 44. In addition, the conductor 50 on the conductor 46 does not necessarily need to be provided. For example, as Fig. 7A and Figure 7B As shown, the upper portion of the opening of the insulator 52 in the conductor 46 and the conductor 44 may be extended to be used as wiring.

[0061] At least a portion of the components of transistor 40 is disposed in the openings of insulator 52 and conductor 44. Here, the bottom of the openings of insulator 52 and conductor 44 is the top surface of conductor 32c, and the side walls of the openings are the side surfaces of insulator 52 and conductor 44.

[0062] like Figure 3A and 6A to 6F As shown in FIG. 1 , the sidewalls of the openings of the insulator 52 and the conductor 44 may have a shape that is perpendicular or substantially perpendicular to the top surface of the conductor 32c. In this case, the openings of the insulator 52 and the conductor 44 are cylindrical. By adopting this structure, the occupied area of ​​the openings of the insulator 52 and the conductor 44 can be reduced, thereby achieving high integration of the storage device.

[0063] In addition, if 7A to 7F and Figure 8 As shown in FIG. 1 , the sidewalls of the openings of the insulator 52 and the conductor 44 may also be tapered. By making the sidewalls of the openings of the insulator 52 and the conductor 44 tapered, the coverage of the oxide semiconductor 42 or the insulator 48 can be improved, thereby reducing defects such as voids. For example, the angle ( Fig. 7A The angle θ) shown is preferably 45 degrees or more and 90 degrees or less. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.

[0064] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to the substrate surface or the formed surface. For example, a region having an angle (hereinafter sometimes referred to as a taper angle) formed by the inclined side surface and the substrate surface is less than 90°. Note that the side surface and the substrate surface of a component do not necessarily have to be completely flat, and may be a nearly planar shape with a slight curvature or a nearly planar shape with fine concave and convex shapes.

[0065] In addition, the openings of the insulator 52 and the conductor 44 may be circular when viewed from a plane. However, this is not limiting, and the openings of the insulator 52 and the conductor 44 may be shapes other than circular when viewed from a plane. For example, the openings of the insulator 52 and the conductor 44 may be roughly circular shapes such as ellipses, polygonal shapes such as quadrangles, or shapes with arcs at the corners of polygons such as quadrangles when viewed from a plane. In this case, the maximum width of the openings of the insulator 52 and the conductor 44 may be appropriately calculated based on the shape of the uppermost portion of the openings of the insulator 52 and the conductor 44. For example, in the case where the opening is a quadrangle when viewed from a plane, the maximum width of the openings of the insulator 52 and the conductor 44 is preferably the length of the diagonal line of the uppermost portion of the openings of the insulator 52 and the conductor 44.

[0066] In addition, if 7A to 7F and Figure 8 As shown in FIG. 1 , when the openings of the insulator 52 and the conductor 44 are circular and the side walls of the openings are tapered when viewed from a plane, the openings of the insulator 52 and the conductor 44 are truncated cone-shaped. Here, the area of ​​the upper bottom surface of the truncated cone (for example, the opening portion provided in the conductor 44) is larger than the area of ​​the lower bottom surface of the truncated cone (the top surface of the conductor 32c exposed in the opening of the insulator 52). At this time, the maximum diameter of the openings of the insulator 52 and the conductor 44 is preferably calculated based on the upper bottom surface of the truncated cone.

[0067] The oxide semiconductor 42, the insulator 48, and the conductor 46 are disposed in the openings of the insulator 52 and the conductor 44 so as to reflect the shapes of the openings. Therefore, the oxide semiconductor 42 is disposed so as to cover the bottom and sidewalls of the openings of the insulator 52 and the conductor 44, the insulator 48 is disposed so as to cover the oxide semiconductor 42, and the conductor 46 is disposed so as to fit into the recess of the insulator 48 reflecting the shapes of the openings of the insulator 52 and the conductor 44.

[0068] like Fig. 7AAs shown in FIG. 1 , the bottom of the conductor 46 located at the opening of the insulator 52 and the conductor 44 has a flat region. Note that depending on the maximum width of the opening of the insulator 52 and the conductor 44 (the maximum diameter when the opening is circular when viewed from a plane), the thickness of the insulator 52, the thickness of the oxide semiconductor 42, and the thickness of the insulator 48, etc., the bottom of the conductor 46 located at the opening may not have a flat region. For example, Figure 7C As shown, the bottom of the conductor 46 located in the opening of the insulator 52 and the conductor 44 may be shaped like a needle.

[0069] Here, the needle-like shape refers to a shape that becomes thinner as it approaches the top end (closer to the bottom of the conductor 46 located at the opening of the insulator 52 and the conductor 44). In addition, the top end of the needle-like shape may be an acute angle or a curved shape that is convex downward. In addition, the shape in which the top end of the needle-like shape is an acute angle may also be called a V-shape.

[0070] The region of the conductor 46 located in the opening of the insulator 52 and the conductor 44 and facing the oxide semiconductor 42 via the insulator 48 is used as a gate electrode. Therefore, the conductor 46 embedded in the opening of the insulator 52 and the conductor 44 and having a needle-like bottom shape can also be called a needle-shaped gate. Fig. 7A and Figure 7B As shown, even if the bottom of the conductor 46 is in a shape having a flat region, the conductor 46 may be referred to as a needle-shaped gate.

[0071] Fig. 7A The structure in which the side surface of the conductor 44 in the opening of the insulator 52 and the conductor 44 is consistent with the side surface of the insulator 52 in the opening is shown in FIG. Fig.7D As shown, the side surfaces of the conductor 44 in the opening of the insulator 52 and the conductor 44 may be discontinuous with the side surfaces of the insulator 52 in the opening. In addition, the inclination of the side surfaces of the conductor 44 in the opening of the insulator 52 and the conductor 44 may be different from the inclination of the side surfaces of the insulator 52 in the opening.

[0072] Here, if Fig.7D As shown, the angle formed by the side surface of the conductor 44 in the opening of the insulator 52 and the conductor 44 and the top surface of the conductor 32c is angle θ2. At this time, angle θ2 is preferably smaller than angle θ. By adopting this structure, the coverage of the side surface of the conductor 44 in the opening of the insulator 52 and the conductor 44 by the oxide semiconductor 42 is improved, and defects such as voids can be reduced.

[0073] Here, in the transistor 40, at least a portion of a region of the oxide semiconductor 42 in contact with the conductor 44 (hereinafter referred to as the first low resistance region) is used as one of the source region and the drain region. In addition, in the transistor 40, at least a portion of a region of the oxide semiconductor 42 in contact with the conductor 32c (hereinafter referred to as the second low resistance region) is used as the other of the source region and the drain region. Figure 2A and Figure 2B As shown, the conductor 44 is in contact with the entire periphery of the oxide semiconductor 42. Therefore, one of the source region and the drain region of the transistor 40 may be formed on the entire periphery of the portion of the oxide semiconductor 42 formed in the same layer as the conductor 44.

[0074] In addition, in the oxide semiconductor 42, at least a portion of the region sandwiched between the first low resistance region and the second low resistance region (hereinafter referred to as the high resistance region) is used as a channel formation region. That is, the channel formation region of the transistor 40 is located in the region between the conductor 32c and the conductor 44 of the oxide semiconductor 42. In addition, it can also be said that the channel formation region of the transistor 40 is located in the region of the oxide semiconductor 42 that contacts the insulator 52 or in the vicinity thereof.

[0075] The channel length of the transistor 40 is the distance between the source region and the drain region. In other words, the channel length of the transistor 40 is determined by the thickness of the insulator 52 on the conductor 32c. When viewed from a cross section, the channel length is the distance between the end of the region where the oxide semiconductor 42 and the conductor 32c are in contact and the end of the region where the oxide semiconductor 42 and the conductor 44 are in contact. In other words, the channel length is equivalent to the length of the side surface of the insulator 52 on the opening side when viewed from a cross section.

[0076] In the existing transistor, the channel length is set according to the exposure limit of the photolithography method, but in the present invention, the channel length can be set according to the thickness of the insulator 52 and the angle θ formed by the side surface of the insulator 52 in the opening of the insulator 52 and the top surface of the conductor 32c. Therefore, the channel length of the transistor 40 can be set to a very fine structure below the exposure limit of the photolithography method (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm or below 10nm and above 1nm or above 5nm). Therefore, the on-state current of the transistor 40 becomes larger, so that the frequency characteristics can be improved. As a result, the read speed and write speed of the memory cell can be improved, so a memory device with a high operating speed can be provided.

[0077] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the openings of the insulator 52 and the conductor 44. Therefore, compared with the conventional transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane, the occupied area of ​​the transistor 40 can be reduced. Thus, the memory device can be highly integrated, so that the memory capacity per unit area can be increased.

[0078] In addition, when viewed from a plane, the oxide semiconductor 42, the insulator 48 and the conductor 46 are arranged in a concentric circle shape near the channel formation region. Therefore, the side of the conductor 46 arranged in the center is opposite to the side of the oxide semiconductor 42 across the insulator 48. That is, when viewed from a plane, the circle of the oxide semiconductor 42 as a whole becomes the channel formation region. At this time, for example, the channel width of the transistor 40 is determined according to the length of the periphery of the oxide semiconductor 42. In other words, it can be said that the channel width of the transistor 40 is determined by the maximum width of the opening of the insulator 52 and the conductor 44 (the maximum diameter when the opening is circular when viewed from a plane). Therefore, by increasing the size of the maximum width of the opening of the insulator 52 and the conductor 44, the channel width per unit area can be increased and the on-state current can be increased.

[0079] In addition, the length of the outer periphery of the oxide semiconductor 42 can be calculated, for example, based on the region facing the conductor 44 or the position of half the thickness of the insulator 52. Note that, as required, the perimeter of any position of the opening of the insulator 52 and the conductor 44 can be set as the channel width of the transistor 40. For example, the perimeter of the lowest portion of the opening of the insulator 52 and the conductor 44 can be set as the channel width, or the perimeter of the highest portion of the opening of the insulator 52 and the conductor 44 can be set as the channel width.

[0080] When the openings of the insulator 52 and the conductor 44 are formed by photolithography, the maximum width of the opening is set according to the exposure limit of the photolithography. In addition, the maximum width of the openings of the insulator 52 and the conductor 44 is set according to the thickness of the oxide semiconductor 42, the insulator 48, and the conductor 46 provided in the opening. The maximum width of the openings of the insulator 52 and the conductor 44 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that in the case where the shape of the openings of the insulator 52 and the conductor 44 is circular when viewed from a plane, the maximum width of the opening is equivalent to the diameter of the openings of the insulator 52 and the conductor 44.

[0081] In addition, in the memory device of the present invention, the channel length of the transistor 40 is preferably at least smaller than the channel width of the transistor 40. The channel length of the transistor 40 in one embodiment of the present invention is greater than or equal to 0.1 times and less than or equal to 0.99 times, preferably greater than or equal to 0.5 times and less than or equal to 0.8 times, of the channel width of the transistor 40. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0082] In addition, by forming the openings of the insulator 52 and the conductor 44 in a circular shape when viewed from a plane, the oxide semiconductor 42, the insulator 48, and the conductor 46 are arranged in concentric circles. As a result, the distance between the conductor 46 and the oxide semiconductor 42 is substantially uniform, so that the gate electric field can be uniformly applied to the oxide semiconductor 42.

[0083] In the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer, it is preferred that the number of oxygen vacancies is small or the concentration of impurities such as hydrogen, nitrogen, and metal elements is low compared to the source region and the drain region. In addition, hydrogen near an oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0084] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where there are more oxygen vacancies than in a channel formation region, and V O The resistance is reduced by increasing the carrier concentration when there is more H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0085] like Figure 3A and Figure 3B As shown in FIG. 4 , a portion of the oxide semiconductor 42 is located outside the opening of the insulator 52 and the conductor 44, that is, located on the conductor 44. Figure 3A and Figure 3B , etc. show a structure in which the oxide semiconductor 42 is divided in the Y direction, but the present invention is not limited thereto. For example, the oxide semiconductor 42 may be extended in the Y direction.

[0086] in addition, Figure 3B The structure in which the side end of the oxide semiconductor 42 is aligned with the side end of the conductor 44 is shown, but the present invention is not limited to this. Figure 7BAs shown, the side edge of the oxide semiconductor 42 may be located inside the side edge of the conductor 44. Alternatively, the side edge of the oxide semiconductor 42 may be located outside the side edge of the conductor 44.

[0087] The band gap of the metal oxide used as the oxide semiconductor 42 is preferably larger than the band gap of silicon (typically 1.1 eV), preferably greater than 2 eV, more preferably greater than 2.5 eV, and further preferably greater than 3.0 eV. By using a metal oxide having a larger band gap than silicon as the oxide semiconductor 42, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced. In addition, the frequency of the refresh operation required for a general DRAM is about 1 time / 60 msec, and the frequency of the refresh operation of a memory device of one embodiment of the present invention can be about 1 time / 10 sec, that is, more than 10 times or more than 100 times the frequency of the refresh line operation can be achieved. In addition, by using a memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to more than 1 time / 1 sec and less than 1 time / 100 sec, preferably more than 1 time / 5 sec and less than 1 time / 50 sec.

[0088] In addition, as the oxide semiconductor 42 , a single layer or a stacked layer of a metal oxide described in [Metal Oxide] to be described later can be used.

[0089] As the oxide semiconductor 42, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0090] In addition, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0091] As an analysis of the composition of the metal oxide used for the oxide semiconductor 42, for example, energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Alternatively, a combination of multiple of the above methods can be used for analysis. Note that elements with low contents are sometimes affected by the accuracy of analysis, and the actual contents are different from the contents obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0092] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. Note that when the metal oxide is formed by sputtering, the composition of the metal oxide after formation is sometimes different from the composition of the sputtering target. In particular, the zinc content in the metal oxide after formation is sometimes reduced to about 50% of the zinc content in the sputtering target.

[0093] The oxide semiconductor 42 preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide semiconductor 42. For example, the crystallinity of the oxide semiconductor 42 can be improved by depositing the oxide semiconductor 42 by a sputtering method in which the substrate is heated or by subjecting the oxide semiconductor 42 to microwave treatment in an atmosphere including oxygen.

[0094] CAAC-OS preferably has a plurality of layered crystal regions and its c-axis is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 42 preferably has layered crystals that are roughly parallel to the side walls of the openings of the insulator 52 and the conductor 44, and in particular, layered crystals that are roughly parallel to the side surfaces of the insulator 52. By adopting this structure, the layered crystals of the oxide semiconductor 42 are roughly parallel to the channel length direction of the transistor 40, so the on-state current of the transistor can be increased.

[0095] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0096] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0097] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 42, oxygen can be suppressed from being extracted from the oxide semiconductor 42 by the source electrode or the drain electrode. Therefore, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 42, so that the transistor 40 is stable to high temperatures (so-called thermal budget) in the manufacturing process.

[0098] The crystallinity of the oxide semiconductor 42 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED), or a combination of a plurality of the above methods.

[0099] Note that Figure 3A The oxide semiconductor 42 is shown as a single-layer structure in the above-mentioned examples, but the present invention is not limited thereto. The oxide semiconductor 42 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may also be adopted.

[0100] For example, Figure 8 As shown, the oxide semiconductor 42 may have a stacked-layer structure of an oxide semiconductor 42 a and an oxide semiconductor 42 b on the oxide semiconductor 42 a .

[0101] The conductivity of the material used for the oxide semiconductor 42 a is preferably different from the conductivity of the material used for the oxide semiconductor 42 b .

[0102] For example, the oxide semiconductor 42a may use a material having a higher conductivity than the oxide semiconductor 42b. By using a material having a higher conductivity for the conductor 32c used as a source electrode or a drain electrode and the oxide semiconductor 42a in contact with the conductor 44, the contact resistance between the oxide semiconductor 42 and the conductor 32c and the contact resistance between the oxide semiconductor 42 and the conductor 44 can be reduced, thereby realizing a transistor with a large on-state current.

[0103] Here, when a material with high conductivity is used for an oxide semiconductor 42b disposed on one side of a conductor 46 used as a gate electrode, the threshold voltage of the transistor is sometimes caused to drift, so that the drain current (hereinafter also recorded as the cut-off current) flowing when the gate voltage is 0V becomes larger. Specifically, when the transistor 40 is an n-channel transistor, the threshold voltage is sometimes reduced. Therefore, the oxide semiconductor 42b preferably uses a material with a lower conductivity than the oxide semiconductor 42a. Thus, when the transistor 40 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cut-off current can be realized. Note that sometimes the cut-off current is recorded as normally closed.

[0104] As described above, by making the oxide semiconductor 42 have a stacked structure and using a material having a higher conductivity than the oxide semiconductor 42b for the oxide semiconductor 42a, a normally-off transistor with a large on-state current can be realized. Thus, a semiconductor device having both low power consumption and high performance can be realized.

[0105] In addition, the carrier concentration of the oxide semiconductor 42a is preferably higher than the carrier concentration of the oxide semiconductor 42b. By increasing the carrier concentration of the oxide semiconductor 42a, the conductivity becomes higher, and the contact resistance between the oxide semiconductor 42 and the conductor 32c and the contact resistance between the oxide semiconductor 42 and the conductor 44 can be reduced, thereby realizing a transistor with a large on-state current. By reducing the carrier concentration of the oxide semiconductor 42b, the conductivity becomes lower, thereby realizing a normally-off transistor.

[0106] Here, although an example is shown in which a material having a higher conductivity than the oxide semiconductor 42b is used for the oxide semiconductor 42a, one embodiment of the present invention is not limited to this. The oxide semiconductor 42a may also use a material having a lower conductivity than the oxide semiconductor 42b. The carrier concentration of the oxide semiconductor 42a may be lower than the carrier concentration of the oxide semiconductor 42b.

[0107] The band gap of the first metal oxide used for oxide semiconductor 42a is preferably different from the band gap of the second metal oxide used for oxide semiconductor 42b. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and further preferably 0.3 eV or more.

[0108] The band gap of the first metal oxide used for oxide semiconductor 42a can be smaller than the band gap of the second metal oxide used for oxide semiconductor 42b. Thus, the contact resistance between oxide semiconductor 42 and conductor 32c and the contact resistance between oxide semiconductor 42 and conductor 44 can be reduced, thereby realizing a transistor with a large on-state current. In addition, in the case where transistor 40 is an n-channel transistor, the threshold voltage can be increased, thereby realizing a normally closed transistor.

[0109] Here, although an example in which the band gap of the first metal oxide is smaller than the band gap of the second metal oxide is shown, one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0110] As described above, the band gap of the first metal oxide used for the oxide semiconductor 42a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 42b. The composition of the first metal oxide is preferably different from the composition of the second metal oxide. By making the composition of the first metal oxide different from the composition of the second metal oxide, the band gap can be controlled. For example, the content of element M of the first metal oxide is preferably lower than the content of element M of the second metal oxide. Specifically, in the case where In-M-Zn oxide is used as the first metal oxide and the second metal oxide, the composition of the first metal oxide can be set to In:M:Zn=1:1:1 [atomic number ratio] or thereabouts, and the composition of the second metal oxide can be set to In:M:Zn=1:3:2 [atomic number ratio] or thereabouts. As element M, it is particularly preferred to use one or more of gallium, aluminum and tin.

[0111] The first metal oxide may not contain the element M. For example, the first metal oxide used for the oxide semiconductor 42a may be an In-Zn oxide, and the second metal oxide used for the oxide semiconductor 42b may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide. More specifically, the composition of the first metal oxide may be set to In:Zn=1:1 [atomic ratio] or thereabouts or In:Zn=4:1 [atomic ratio] or thereabouts, and the composition of the second metal oxide may be set to In:Ga:Zn=1:1:1 [atomic ratio] or thereabouts.

[0112] Here, although an example is shown in which the content of the element M of the first metal oxide is lower than the content of the element M of the second metal oxide, one embodiment of the present invention is not limited thereto. The content of the element M of the first metal oxide may also be higher than the content of the element M of the second metal oxide. In addition, as long as the composition of the first metal oxide and the second metal oxide is different, the content of elements other than the element M of the first metal oxide and the second metal oxide may also be different.

[0113] The thickness of the oxide semiconductor 42 is preferably not less than 1 nm, not less than 3 nm, or not less than 5 nm and not more than 20 nm, not more than 15 nm, not more than 12 nm, or not more than 10 nm.

[0114] The thickness of each layer constituting the oxide semiconductor 42 (here, the oxide semiconductor 42a and the oxide semiconductor 42b) may be determined so that the thickness of the oxide semiconductor 42 is within the above range. The thickness of the oxide semiconductor 42a may be determined so that the contact resistance between the oxide semiconductor 42a and the conductor 32c and the contact resistance between the oxide semiconductor 42a and the conductor 44 are within the required range. In addition, the thickness of the oxide semiconductor 42b may be determined so that the threshold voltage of the transistor is within the required range. Note that the thickness of the oxide semiconductor 42a may be the same as or different from the thickness of the oxide semiconductor 42b.

[0115] Figure 8 Although the example in which the oxide semiconductor 42 has a stacked-layer structure of two layers of the oxide semiconductor 42 a and the oxide semiconductor 42 b is shown, the present invention is not limited thereto and the oxide semiconductor 42 may have a stacked-layer structure of three or more layers.

[0116] When the oxide semiconductor 42 has a structure in which the first layer to the third layer are stacked in order from the conductor 32c side, for example, the following structure may be adopted: as the first layer, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto is used, as the second layer, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto or In:Zn=4:1 [atomic ratio] or a composition close thereto is used, and as the third layer, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto is used. For example, the thickness of the first layer and the third layer may be set to about 1 nm, and the thickness of the second layer may be set to about 3 nm to 5 nm.

[0117] Here, the energy of the conduction band bottom of the first layer and the third layer is preferably higher than the energy of the conduction band bottom of the second layer. In other words, the electron affinity of the first layer and the third layer is preferably smaller than the electron affinity of the second layer. For example, the difference between the conduction band bottom energy (electron affinity) of the first layer and the third layer and the conduction band bottom energy (electron affinity) of the second layer is preferably 0.05 eV or more and less than 0.3 eV.

[0118] Here, the electron affinity or the conduction band bottom energy level Ec can be calculated from the ionization potential Ip, which is the difference between the vacuum energy level and the energy level Ev at the top of the valence band, and the energy gap Eg. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.

[0119] By adopting the above structure, the on-state current of the transistor 200 can be increased, so that a transistor structure with less variation and high reliability can be realized.

[0120] As the insulator 48, a single layer or a stack of insulators described in [Insulator] described later can be used. As the insulator 48, for example, silicon oxide or silicon oxynitride can be used. Silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0121] In addition, a material having a high relative dielectric constant, that is, a so-called high-k material described in [Insulator] described later, may be used as the insulator 48. For example, hafnium oxide or aluminum oxide may be used.

[0122] The thickness of the insulator 48 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulator 48 may be a region having the above thickness.

[0123] The concentration of impurities such as water and hydrogen in the insulator 48 is preferably reduced. This can prevent impurities such as water and hydrogen from being mixed into the channel formation region of the oxide semiconductor 42 .

[0124] A portion of the insulator 48 is located outside the openings of the insulator 52 and the conductor 44, that is, located on the conductor 44 and the insulator 52. Fig. 6E , Fig. 6F , 7A to 7F and Figure 8 As shown in FIG. 1 , the insulator 48 preferably covers the side end of the oxide semiconductor 42. This can prevent the conductor 46 and the oxide semiconductor 42 from being short-circuited. Figure 7BAs shown, the insulator 48 preferably covers the side end of the conductor 44. This can prevent the conductor 46 and the conductor 44 from being short-circuited.

[0125] Note that Figure 3A The insulator 48 is shown as a single-layer structure in FIG. 1 , but the present invention is not limited thereto. The insulator 48 may also have a stacked-layer structure.

[0126] For example, Figure 8 As shown, the insulator 48 may also have a stacked structure of an insulator 48a, an insulator 48b on the insulator 48a, an insulator 48c on the insulator 48b, and an insulator 48d on the insulator 48c.

[0127] The insulator 48b preferably uses a material with a low relative dielectric constant as described in [Insulator] to be described later. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 48b contains at least oxygen and silicon. By adopting this structure, the parasitic capacitance generated between the conductor 46 and the conductor 44 can be reduced. In addition, it is preferred that the impurity concentration of water, hydrogen, etc. in the insulator 48b is reduced.

[0128] The insulator 48a preferably uses an insulator having oxygen barrier properties as described in [Insulator] to be described later. The insulator 48a has a region in contact with the oxide semiconductor 42. When the insulator 48a has oxygen barrier properties, it is possible to suppress the detachment of oxygen from the oxide semiconductor 42 during heat treatment or the like. Therefore, the formation of oxygen vacancies in the oxide semiconductor 42 can be suppressed. As a result, the electrical characteristics of the transistor 40 can be improved, and the reliability can be improved. As the insulator 48a, for example, aluminum oxide is preferably used. In this case, the insulator 48a contains at least oxygen and aluminum.

[0129] The insulator 48d preferably uses an insulator having hydrogen barrier properties as described in [Insulator] described later. This can suppress the diffusion of impurities contained in the conductor 46 into the oxide semiconductor 42. Silicon nitride has high hydrogen barrier properties and is therefore suitable for the insulator 48d. In this case, the insulator 48d contains at least nitrogen and silicon.

[0130] The insulator 48d may also have oxygen barrier properties. The insulator 48d is provided between the insulator 48b and the conductor 46. Thus, oxygen contained in the insulator 48b can be prevented from diffusing into the conductor 46 and oxidation of the conductor 46 can be suppressed. In addition, a reduction in the amount of oxygen supplied to the channel formation region can be suppressed.

[0131] In addition, it is preferred to provide an insulator 48c between the insulator 48b and the insulator 48d. As the insulator 48c, it is preferred to use an insulator having a function of capturing or fixing hydrogen as described in [Insulator] to be described later. By providing the insulator 48c, hydrogen contained in the oxide semiconductor 42 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 42 can be reduced. As the insulator 48c, for example, hafnium oxide is preferably used. In this case, the insulator 48c contains at least oxygen and hafnium. In addition, the insulator 48c may also have an amorphous structure.

[0132] In order to achieve miniaturization of transistor 40, the thickness of insulators 48a to 48d is preferably thin, and it is preferred to set their thicknesses within the above range. Typically, the thicknesses of insulators 48a, 48b, 48c, and 48d are set to 1nm, 2nm, 2nm, and 1nm, respectively. By adopting such a structure, even if transistor 40 is miniaturized or highly integrated, it can have good electrical characteristics.

[0133] exist Figure 8 The insulator 48 has a laminated structure of four layers of insulators 48a to 48d, but the present invention is not limited thereto. The insulator 48 may also have a laminated structure of two, three, or five or more layers. In this case, each layer included in the insulator 48 is preferably an insulator appropriately selected from the insulators 48a to 48d.

[0134] A single layer or a stack of the conductors described in [Conductor] described later can be used as the conductor 46. For example, a highly conductive material such as tungsten can be used as the conductor 46.

[0135] In addition, as the conductor 46, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. As the conductive material, there can be cited a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.). Thus, the decrease in the conductivity of the conductor 46 can be suppressed.

[0136] The conductor 46 may also have a laminated structure. Figure 8 As shown in FIG. 1 , the conductor 46 may have a laminated structure of a conductor 46a and a conductor 46b on the conductor 46a. In this case, for example, titanium nitride may be used as the conductor 46a and tungsten may be used as the conductor 46b. By laminating tungsten in this way, the conductivity of the conductor 46 can be improved and the function as the wiring WOL can be fully exerted.

[0137] exist Figure 8The conductor 46 has a two-layer laminate structure of the conductor 46a and the conductor 46b, but the present invention is not limited thereto. The conductor 46 may also have a three-layer laminate structure or more.

[0138] exist Fig. 7A The conductor 46 is provided so as to be embedded in the openings of the insulator 52 and the conductor 44, but the present invention is not limited thereto. For example, a concave portion reflecting the shape of the openings of the insulator 52 and the conductor 44 may be formed in the center of the conductor 46, and a part of the concave portion is located in the openings of the insulator 52 and the conductor 44. In this case, the concave portion may be filled with an inorganic insulating material or the like.

[0139] like 6A to 7F As shown in FIG. 1 and FIG. 2 , a portion of the conductor 46 may be located outside the openings of the insulator 52 and the conductor 44, that is, located on the conductor 44 and the insulator 52. Fig. 6E and Fig. 7A As shown in the figures, the side end of the conductor 46 is preferably located inside the side end of the oxide semiconductor 42. Thus, it is possible to prevent the conductor 46 from being short-circuited with the oxide semiconductor 42. In addition, the side end of the conductor 46 may be consistent with the side end of the oxide semiconductor 42, or may be located outside the side end of the oxide semiconductor 42.

[0140] In addition, if Figure 3A As shown in FIG. 5 , a portion of the conductor 46, a portion of the insulator 48, and a portion of the oxide semiconductor 42 may be located outside the openings of the insulator 52 and the conductor 44, that is, located on the conductor 44 and the insulator 52. Here, a portion of the conductor 46, a portion of the insulator 48, and a portion of the oxide semiconductor 42 are preferably provided in a manner embedded in the insulator 56. At this time, the height of the top surface of the conductor 46 and the height of the top surface of the insulator 56 are preferably consistent. Note that this is not limited to this, as Fig. 7A As shown in FIG. 1 and FIG. 2 , an insulator 56 may be provided so as to cover the conductor 46 .

[0141] like Figure 3A As shown in FIG. 1 , a conductor 50 may be provided in contact with the top surface of the conductor 46. As the conductor 50, a single layer or a stack of conductors described in [Conductor] described above may be used. For example, as the conductor 50, a highly conductive conductive material such as tungsten may be used.

[0142] When the conductor 50 is provided, the conductor 50 is used as the wiring WOL, so the conductor 50 may be extended in the X direction, for example. Here, the conductor 46 may be formed in an island shape when viewed from a plane. Note that in this specification, etc., an island shape refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

[0143] The conductor 50 is preferably provided so as to be embedded in the insulator 58. At this time, the height of the top surface of the conductor 50 and the height of the top surface of the insulator 58 are preferably the same.

[0144] exist Figure 3A In the embodiment, the side end of the conductor 50 is consistent with the side end of the conductor 46, but the present invention is not limited to this. Fig. 6E As shown, the side end of the conductor 50 may be located outside the side end of the conductor 46. In addition, the side end of the conductor 50 may be located inside the side end of the conductor 46.

[0145] like Figure 3A As shown in the figure, the conductor 32c is arranged in contact with the top surface of the conductor 30c. When viewed from a plane, the conductor 32c is formed into an island shape. The conductor 32c is preferably arranged in a manner embedded in the insulator 38. In addition, the conductor 32a and the conductor 32b formed in the same layer as the conductor 32c are also preferably arranged in a manner embedded in the insulator 38. At this time, the height of the top surface of the conductor 32a to the conductor 32c is preferably consistent with the height of the top surface of the insulator 38. Note that this is not limited to this, and a structure without the insulator 38 can also be adopted. At this time, the conductors 32a to 32c are covered by the insulator 52.

[0146] As the conductors 32a to 32c, a single layer or a stack of conductors described in [Conductor] described later can be used. As the conductors 32a to 32c, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. By adopting this structure, it is possible to suppress excessive oxidation of the conductor 32c due to the oxide semiconductor 42. Alternatively, a metal oxide can be used as the conductor 32c. For example, indium tin oxide with added silicon can also be used. In addition, for example, a structure in which indium tin oxide with added silicon is stacked on tungsten can also be used. By stacking tungsten in this way, the conductivity of the conductor 32c can be improved.

[0147] also, Figure 3A The top surface of the conductor 32c is flattened, but the present invention is not limited thereto. Fig. 6A As shown, a recessed portion overlapping the openings of the insulator 52 and the conductor 44 may be formed on the top surface of the conductor 32c. By adopting a structure in which the oxide semiconductor 42, the insulator 48, and at least a portion of the conductor 46 are formed in such a manner as to be embedded in the recessed portion, the gate electric field of the conductor 46 can be easily applied to the vicinity of the conductor 32c of the oxide semiconductor 42.

[0148] In addition, for example, Figure 6BAs shown, an opening that overlaps with the openings of the insulator 52 and the conductor 44 may be formed in the conductor 32c. The opening is formed so as to pass through the conductor 32c, and the top surface of the conductor 30c is exposed in the opening, that is, the bottom surface of the oxide semiconductor 42 is in contact with the top surface of the conductor 30c. By adopting this structure, the gate electric field of the conductor 46 can be easily applied to the vicinity of the conductor 32c of the oxide semiconductor 42.

[0149] A single layer or a stack of the conductors described in [Conductor] described later can be used as the conductor 44. For example, a highly conductive material such as tungsten can be used as the conductor 44.

[0150] As with the conductor 46, the conductor 44 is preferably made of a conductive material that is not easily oxidized or has a function of inhibiting oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. By adopting such a structure, the conductor 44 can be prevented from being excessively oxidized by the oxide semiconductor 42.

[0151] Alternatively, a metal oxide may be used as the conductor 44. For example, indium tin oxide with silicon added may be used. In addition, for example, a structure in which indium tin oxide with silicon added is stacked on tungsten may be used. By stacking tungsten in this way, the conductivity of the conductor 44 can be improved and the function as the wiring WBL can be fully exerted.

[0152] When the oxide semiconductor 42 is in contact with the conductor 32c, a metal compound or oxygen vacancy is formed, and the second low resistance region of the oxide semiconductor 42 is low-resistance. By making the oxide semiconductor 42 in contact with the conductor 32c low-resistance, the contact resistance between the oxide semiconductor 42 and the conductor 32c can be reduced. Similarly, when the oxide semiconductor 42 is in contact with the conductor 44, the first low resistance region of the oxide semiconductor 42 is low-resistance. Thus, the contact resistance between the oxide semiconductor 42 and the conductor 44 can be reduced.

[0153] In addition, if Figure 3B As shown in FIG. 1 and FIG. 2 , the conductor 44 may be embedded in the insulator 54. In this case, the height of the top surface of the conductor 44 is preferably consistent with the height of the top surface of the insulator 54. By adopting this structure, the physical distance from the conductor 46 to the conductor 44 (especially the side end of the conductor 44) can be increased, and the conductor 46 and the conductor 44 can be prevented from short-circuiting. Note that this is not limited to this. Figure 7B As shown in FIG. 1 , the insulator 54 may not be provided.

[0154] In addition, if Figure 6C As shown, an insulator 59 may be provided between the conductor 44 and the insulator 56. Figure 3AUnlike the structure shown in the figure, the top surface of the conductor 44 is not in contact with the oxide semiconductor 42 .

[0155] Furthermore, if Fig.6D As shown, a structure in which the height of the top surface of the oxide semiconductor 42 is consistent with the height of the top surface of the insulator 52 in the openings of the insulator 59, the conductor 44, and the insulator 52 may also be adopted. In this structure, the top surface of the oxide semiconductor 42 is in contact with the bottom surface of the conductor 44. Here, the height of the top surface of the insulator 48 and the conductor 46 is preferably consistent with the height of the top surface of the insulator 59. In this structure, the top surface of the conductor 46 is in contact with the bottom surface of the conductor 50. By adopting this structure, the oxide semiconductor 42, the insulator 48, and the conductor 46 are only formed in the openings of the insulator 59, the conductor 44, and the insulator 52, so there is no need to perform a process of processing the oxide semiconductor 42, the insulator 48, and the conductor 46 by photolithography.

[0156] Since insulator 38, insulator 52, insulator 54, insulator 59, insulator 56, and insulator 58 are used as interlayer films, their relative dielectric constants are preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. As insulator 38, insulator 52, insulator 54, insulator 59, insulator 56, and insulator 58, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] described later can be used. Silicon oxide and silicon oxynitride are preferably used because they have thermal stability.

[0157] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in insulators 38, 52, 54, 59, 56, and 58. This can prevent impurities such as water and hydrogen from entering the channel formation region of oxide semiconductor 42.

[0158] In addition, as the insulator 52 disposed near the channel formation region, it is preferable to use an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). By heat-treating the insulator 52 containing excess oxygen, oxygen can be supplied from the insulator 52 to the channel formation region of the oxide semiconductor 42, thereby reducing oxygen vacancies and V O H. Thus, the electrical characteristics of the transistor 40 can be stabilized and the reliability can be improved.

[0159] Note that Figure 3A The insulator 52 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 52 may also have a stacked-layer structure.

[0160] For example, Fig. 6F , Fig. 7E , Figure 7F and Figure 8As shown, the insulator 52 may also have a stacked structure of an insulator 52a, an insulator 52b on the insulator 52a, and an insulator 52c on the insulator 52b.

[0161] The insulator 52b preferably uses an insulator containing oxygen. The insulator 52b preferably has a region having a higher oxygen content than at least one of the insulator 52a and the insulator 52c. In particular, the insulator 52b preferably has a region having a higher oxygen content than the insulator 52a and the insulator 52c, respectively. When the oxygen content of the insulator 52b is high, an i-type region is easily formed in the region in contact with the insulator 52b in the oxide semiconductor 42 and in the vicinity thereof.

[0162] The insulator 52b is preferably a film that releases oxygen by heating. Since the insulator 52b releases oxygen due to heat applied in the manufacturing process of the transistor 40, oxygen can be supplied to the oxide semiconductor 42. By supplying oxygen from the insulator 52b to the oxide semiconductor 42, especially to the channel formation region of the oxide semiconductor 42, oxygen vacancies in the oxide semiconductor 42 and V O H, a transistor with good electrical characteristics and high reliability can be realized.

[0163] For example, oxygen can be supplied to the insulator 52 b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by depositing an oxide film on the top surface of the insulator 52 b by sputtering in an oxygen atmosphere. The oxide film can then be removed.

[0164] The insulator 52b is preferably formed by a deposition method such as sputtering or plasma enhanced chemical vapor deposition (PECVD). In particular, when sputtering is used, a film containing very little hydrogen can be deposited by a deposition method that does not use hydrogen gas as a deposition gas. Therefore, the semiconductor 42 can be prevented from being supplied with hydrogen, thereby stabilizing the electrical characteristics of the transistor 40.

[0165] When the channel length of transistor 40 is small, oxygen vacancies in the channel formation region and V O The influence of H on the power supply characteristics and reliability is particularly great. By supplying oxygen from the insulator 52b to the oxide semiconductor 42, oxygen vacancies and V can be suppressed at least in the region of the oxide semiconductor 42 that is in contact with the insulator 52b. O H increases. Therefore, a transistor with a small channel length having good electrical characteristics and high reliability can be realized.

[0166] Insulator 52a and insulator 52c preferably use an insulator having oxygen barrier properties as described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of oxygen in insulator 52b to the substrate side through insulator 52a and to the insulator 56 side through insulator 52c due to heating. In other words, by sandwiching insulator 52b with insulator 52a and insulator 52c, which are not easy to diffuse oxygen, the oxygen in insulator 52b can be confined. Thus, oxygen can be effectively supplied to oxide semiconductor 42.

[0167] In addition, due to the oxygen in the insulator 52b, the conductor 32c and the conductor 44 are oxidized, and sometimes the resistance becomes higher. By providing the insulator 52a between the insulator 52b and the conductor 32c, it is possible to suppress the conductor 32c from being oxidized and the resistance from becoming higher. In addition, by providing the insulator 52c between the insulator 52b and the conductor 44, it is possible to suppress the conductor 44 from being oxidized and the resistance from becoming higher. At the same time, the amount of oxygen supplied from the insulator 52b to the oxide semiconductor 42 increases, and the oxygen vacancies in the oxide semiconductor 42 can be reduced.

[0168] In addition, in the oxide semiconductor 42, the amount of oxygen supplied to the region in contact with the insulator 52a and the region in contact with the insulator 52c is small compared to the region in contact with the insulator 52b. As a result, sometimes the region in contact with the insulator 52a and the region in contact with the insulator 52c of the oxide semiconductor 42 are low-resistance. That is, by adjusting the thickness of the insulator 52a, the range of the second low-resistance region used as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 52c, the range of the first low-resistance region used as the other of the source region and the drain region can be controlled. As described above, since the source region and the drain region can be controlled by the thickness of the insulator 52a and the insulator 52c, the thickness of the insulator 52a and the insulator 52c can be appropriately set according to the characteristics required by the transistor 40.

[0169] The insulator 52a and the insulator 52c preferably use an insulator having hydrogen barrier properties described in [Insulator] to be described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through the insulator 52a or the insulator 52c to the oxide semiconductor 42. Since both the silicon nitride film and the silicon oxynitride film have the characteristics of releasing very few impurities (for example, water and hydrogen) and not easily permeating oxygen and hydrogen, they can be used for the insulator 52a and the insulator 52c. Note that the insulator 52a and the insulator 52c can use the same material or different materials.

[0170] The thickness of the insulator 52a is preferably smaller than the thickness of the insulator 52b. In addition, the thickness of the insulator 52c is preferably smaller than the thickness of the insulator 52b. The thickness of the insulator 52a and the insulator 52c is preferably greater than 1nm and less than 15nm, more preferably greater than 2nm and less than 10nm, further preferably greater than 3nm and less than 7nm, and further preferably greater than 3nm and less than 5nm. The thickness of the insulator 52b is preferably greater than 3nm and less than 30nm, more preferably greater than 5nm and less than 20nm, and further preferably greater than 7nm and less than 15nm. By setting the thickness of the insulators 52a to 52c within the above range, oxygen vacancies in the oxide semiconductor 42, especially oxygen vacancies in the channel formation region, can be reduced.

[0171] For example, it is preferable that the insulator 52a and the insulator 52c use silicon nitride, and the insulator 52b use silicon oxide. In this case, the insulator 52a and the insulator 52c contain at least silicon and nitrogen. In addition, the insulator 52b contains at least silicon and oxygen.

[0172] Notice, Fig. 6F , Fig. 7E , Figure 7F and Figure 8 The insulator 52 is shown to have a three-layer stacked structure, but one embodiment of the present invention is not limited thereto. The insulator 52 may have a two-layer or four-layer stacked structure.

[0173] In addition, if Figure 7F and Figure 8 As shown, an insulator 57 may be provided in a manner covering the conductor 46 and the insulator 48. When providing the insulator 57, the insulator 56 may be provided on the insulator 57. As the insulator 57, it is preferable to use an insulator having hydrogen barrier properties as described in [Insulator] described later. Thus, it is possible to suppress the diffusion of hydrogen from the outside of the transistor through the insulator 48 to the oxide semiconductor 42. Both the silicon nitride film and the silicon oxynitride film have the characteristics of releasing very little impurities (for example, water and hydrogen) and not easily permeating oxygen and hydrogen, so they can be applied to the insulator 57.

[0174] [Transistor 60] In addition, the storage device shown in this embodiment may also adopt Figure 5A and Figure 5B The structure shown in FIG. 1 is a structure in which a transistor 60 is provided under the transistor 20. The transistor 60 is provided on a substrate 62 and includes a conductor 66, an insulator 68, a semiconductor region 63 formed by a portion of the substrate 62, and a low resistance region 64a and a low resistance region 64b used as a source region or a drain region. Figure 5A is corresponding to Figure 3A The picture, Figure 5B is corresponding to Figure 3B.

[0175] like Figure 5B As shown, in the transistor 60, the conductor 66 covers the top surface and the side surface in the channel width direction of the semiconductor region 63 via the insulator 68. In this way, by making the transistor 60 have a Fin-type structure, the effective channel width increases, thereby improving the on-state characteristics of the transistor 60. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 60 can be improved.

[0176] The transistor 60 may be a p-channel transistor or an n-channel transistor. Alternatively, a structure in which a p-channel transistor 60 and an n-channel transistor 60 are mixed may be adopted.

[0177] The channel forming region of the semiconductor region 63, the region near the channel, the low resistance region 64a and the low resistance region 64b used as the source region or the drain region, etc. preferably contain semiconductors such as silicon-based semiconductors, and more preferably contain single crystal silicon. Therefore, as the substrate 62, for example, a single crystal silicon substrate can be used. Alternatively, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that applies stress to the lattice to change the interplanar spacing to control the effective mass can be used. Alternatively, the transistor 60 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0178] The low resistance regions 64 a and 64 b contain, in addition to the semiconductor material used for the semiconductor region 63 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0179] As the conductor 66 used as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron can be used.

[0180] In addition, since the material of the conductor determines the work function, the threshold voltage (Vth) of the transistor can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferred in terms of heat resistance.

[0181] Figure 5A and Figure 5B The transistor 60 shown is only an example, and the structure is not limited to this, and an appropriate transistor can be used according to the circuit structure and driving method.

[0182] Insulators 74, 76, and 78 are sequentially stacked to cover transistor 60. Semiconductor region 63 is isolated by insulator 73. Insulator 73 can be formed by LOCOS (Local Oxidation of Silicon) method or STI (Shallow Trench Isolation) method.

[0183] As the insulator 73 , the insulator 74 , the insulator 76 , and the insulator 78 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0184] The insulator 76 may also be used as a planarization film for planarizing steps caused by the transistor 60 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 76, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0185] Insulator 78 may also have a stacked structure. For example, it is preferable to provide silicon oxide or silicon oxynitride on the upper layer of insulator 78, and to use a barrier film for preventing hydrogen and impurities from diffusing from substrate 62 or transistor 60 to the region where transistor 200 is provided on the lower layer of insulator 78.

[0186] As an example of a film having hydrogen barrier properties, for example, silicon nitride can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 20, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to use a film that inhibits hydrogen diffusion between transistor 20 and transistor 60. Specifically, a film that inhibits hydrogen diffusion refers to a film with a small amount of hydrogen released.

[0187] In addition, insulator 74, insulator 76, and insulator 78, conductors 70 (conductor 70a, conductor 70b, conductor 70c) and conductors 72 (conductor 72a, conductor 72b, conductor 72c) and the like electrically connected to transistor 20 or transistor 40 are embedded. Here, conductor 70 and conductor 72 are used as plugs or wiring. Note that in conductors used as plugs or wiring, the same figure mark is sometimes used to represent multiple structures. In addition, in this specification, etc., wiring and a plug electrically connected to the wiring can also be a component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0188] As the material of each plug and wiring (conductor 70 and conductor 72, etc.), a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, preferably tungsten. Alternatively, it is preferred to use a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0189] Alternatively, a wiring layer may be provided on the insulator 78 and the conductor 72. The transistor 60 can be electrically connected to the transistor 20 or the transistor 40 via the wiring layer.

[0190] <Constituent Materials of Storage Device> Next, constituent materials that can be used for the storage device are described.

[0191] [Substrate] As a substrate for forming the above-mentioned storage device, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductive substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate provided with an element on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0192] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0193] For example, when miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin filmization of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferred to select the material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a large dielectric strength.

[0194] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0195] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate and acrylic resin can be cited. In addition, as inorganic insulating materials with low relative dielectric constants other than the above, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, silicon oxide with holes can be cited. In addition, these silicon oxides can also contain nitrogen.

[0196] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the transmission of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the transmission of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used. Specifically, as an insulator having a function of suppressing the transmission of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0197] In addition, an insulator such as a gate insulator that contacts a semiconductor or an insulator that is disposed near a semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen contacts a semiconductor layer or when an insulator having a region containing excess oxygen is disposed near a semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having holes.

[0198] In addition, as an insulator having oxygen barrier properties, there can be mentioned an oxide containing one or both of aluminum and hafnium, an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In addition, as an oxide containing one or both of aluminum and hafnium, there can be mentioned aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0199] In addition, examples of insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.

[0200] An insulator having oxygen barrier properties and an insulator having hydrogen barrier properties can be said to be an insulator having barrier properties against one or both of oxygen and hydrogen.

[0201] In addition, as an insulator having the function of capturing or fixing hydrogen, an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be cited. In addition, these oxides more preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following properties: oxygen atoms have dangling bonds and hydrogen is captured or fixed by the dangling bonds. In addition, these metal oxides preferably have an amorphous structure, but a portion thereof may also be formed with a crystalline region.

[0202] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance is not easily diffused (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as impurity absorption) the corresponding substance can be replaced by the term barrier property. In addition, hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - In addition, unless otherwise stated, the impurities recorded as corresponding substances refer to impurities in the channel formation region or in the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is not easily diffused.

[0203] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, the nitride of the alloy or the oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0204] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, oxides of strontium and ruthenium, or oxides of lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even after absorbing oxygen, and are therefore preferred.

[0205] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0206] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0207] In addition, when a metal oxide is used in the channel formation region of the transistor, the conductor used as the gate electrode preferably adopts a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0208] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide in which a channel is formed can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0209] [Metal oxides] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities.

[0210] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to generation or capture of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferred that the metal oxide used for the semiconductor layer of the transistor has fewer lattice defects.

[0211] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical properties are easily changed, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms V O H and may generate electrons that become carriers. Thus, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even if no voltage is applied to the gate electrode). Thus, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0212] The type of lattice defects that are likely to exist in the metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0213] The structure of metal oxides is divided into single crystal structure and other structures (non-single crystal structure). As non-single crystal structures, there are CAAC structure, polycrystalline structure, nc structure, amorphous-like (a-like) structure and amorphous structure. The a-like structure has a structure between the nc structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0214] In addition, there are voids or low-density areas in metal oxides having an a-like structure and metal oxides having an amorphous structure. In other words, the crystallinity of metal oxides having an a-like structure and metal oxides having an amorphous structure is lower than that of metal oxides having a nc structure and metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxide of the metal oxide having an a-like structure is higher than that of the metal oxide having a nc structure and the metal oxide having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0215] Therefore, it is preferred to use a metal oxide with high crystallinity for the semiconductor layer of the transistor. For example, it is preferred to use a metal oxide with a CAAC structure or a metal oxide with a single crystal structure. By using the metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0216] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is sufficient to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0217] Here, the metal oxide having a channel formation region preferably adopts a metal oxide with high crystallinity. Furthermore, the crystal preferably has a crystal structure stacked with multiple layers (for example, a first layer, a second layer, and a third layer). In other words, the crystal has a layered crystal structure (also called a layered crystal, a layered structure). At this time, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having the crystal include, for example, single crystal oxide semiconductors, CAAC-OS (c-axis alignedcrystalline oxide semiconductor), and the like.

[0218] In addition, the c-axis of the crystal is preferably oriented in the normal direction of the formed surface or film surface of the metal oxide. Thus, the multiple layers are arranged in parallel or approximately parallel to the formed surface or film surface of the metal oxide. That is, the multiple layers extend in the channel length direction.

[0219] For example, the three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron in which the metal contained in the first layer exists at the center. In addition, the second layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the second layer exists at the center. In addition, the third layer has an atomic coordination structure of an oxygen triangular bipyramid or tetrahedron in which the metal contained in the third layer exists at the center.

[0220] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and deformation structures thereof.

[0221] Furthermore, it is preferred that the first to third layers are all composed of one metal element or a plurality of metal elements having the same valence and oxygen. Note that it is preferred that the valence of the one or more metal elements constituting the first layer is the same as the valence of the one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferred that the valence of the one or more metal elements constituting the first layer is different from the valence of the one or more metal elements constituting the third layer.

[0222] By adopting the above structure, the crystallinity of the metal oxide can be improved and the mobility of the metal oxide can be improved. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased and the electrical characteristics of the transistor can be improved.

[0223] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Note that element M is a metal element or a semi-metal element with a high bonding energy with oxygen, for example, a metal element or a semi-metal element with a higher bonding energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and the "metal elements" recorded in this specification, etc. sometimes include semi-metal elements.

[0224] As an oxide semiconductor of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide) and the like containing silicon may be mentioned.

[0225] By increasing the atomic number ratio of indium relative to the total atomic number of all metal elements in the metal oxide, the field effect mobility of the transistor can be increased.

[0226] Note that the metal oxide may also contain one or more metal elements with a large periodic number instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large periodic number in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0227] In addition, the metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0228] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor can be suppressed and the reliability can be improved.

[0229] In addition, by increasing the atomic number ratio of the element M relative to the total atomic number of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0230] In addition, by increasing the atomic number ratio of In relative to the total atomic number of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high frequency characteristics.

[0231] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0232] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. In the method for depositing a metal oxide according to one embodiment of the present invention, since the ALD method is used, the metal oxide having the layered crystal structure can be easily formed.

[0233] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0234] The ALD method can deposit atoms layer by layer, which has the following effects: it can deposit very thin films; it can deposit structures with high aspect ratios; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. In addition, in the PEALD method, deposition can be performed at lower temperatures by using plasma, so it is sometimes preferred. In addition, the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods. In addition, the quantification of these elements can be performed using XPS or SIMS. Note that the deposition method of the metal oxide as one embodiment of the present invention uses the ALD method, but due to the use of one or both of the conditions of high substrate temperature during deposition and impurity removal treatment, the amount of carbon and chlorine contained in the film is sometimes less than when the ALD method is used without the above conditions.

[0235] The ALD method is different from a deposition method in which particles released from a target material are deposited. It is a film-forming method in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, this method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0236] The ALD method can control the composition of the obtained film according to the amount of source gas introduced. For example, when the ALD method is used, a film of any composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time). In addition, for example, when the ALD method is used, a film whose composition changes continuously can be deposited by changing the source gas while performing deposition. When deposition is performed while changing the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0237] Note that after the metal oxide film is deposited by the ALD method or the like, microwave treatment is preferably performed, and microwave treatment is more preferably performed in an atmosphere containing oxygen.

[0238] By carrying out microwave treatment under an oxygen-containing atmosphere, high frequencies such as microwaves and RF can be used to plasmatize the oxygen gas and cause the oxygen plasma to act on the metal oxide. At this time, high frequencies such as microwaves and RF can also be irradiated to the metal oxide. In other words, high frequencies such as microwaves and RF, oxygen plasma, etc. can be acted on the metal oxide.

[0239] Due to the effects of high frequency, oxygen plasma, etc., the impurity concentration of the metal oxide can be reduced. For example, hydrogen in the metal oxide can be separated into water molecules. In addition, for example, carbon in the metal oxide can be separated into carbon oxides (CO and / or CO2). In addition, by supplying oxygen free radicals generated in oxygen plasma to the metal oxide, oxygen vacancies, V in the metal oxide can be reduced. O H et al.

[0240] In addition, due to the effects of high frequency, oxygen plasma, etc., energy above the processing temperature of microwave treatment is provided to the atoms in the metal oxide. Therefore, the rearrangement of metal atoms and oxygen atoms in the metal oxide is promoted, and the crystallinity of the metal oxide can be improved. Note that there is a tendency that the impurity concentration and defects (oxygen vacancies and V) in the metal oxide OThe less the amount of H, the easier it is to improve the crystallinity of the metal oxide. That is, microwave treatment in an oxygen-containing atmosphere reduces the impurity concentration and defect amount in the metal oxide and improves the crystallinity of the metal oxide.

[0241] [[Transistor including an oxide semiconductor]] Next, a case where a metal oxide (oxide semiconductor) is used for a transistor is described. Hereinafter, a transistor using an oxide semiconductor in a semiconductor layer may be referred to as an OS transistor, and a transistor using silicon in a semiconductor layer may be referred to as a Si transistor.

[0242] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of more than 2nm and less than 30nm can be manufactured.

[0243] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 Above. Note that, when the purpose is to reduce the carrier concentration of the oxide semiconductor film, it is sufficient to reduce the impurity concentration in the oxide semiconductor film to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0244] Since the defect state density of a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is low, the trap state density may also be low.

[0245] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0246] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity.

[0247] In addition, in Si transistors, the short channel effect (also called Short Channel Effect: SCE) appears as the miniaturization of transistors develops. Therefore, the miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, OS transistors use oxide semiconductors as semiconductor materials with large band gaps, which can suppress the short channel effect. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0248] In addition, the short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0249] In addition, as an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0250] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region of OS transistors and the characteristic length between the drain region and the channel formation region are smaller. Therefore, compared with Si transistors, OS transistors have a higher ability to resist short channel effects. That is to say, in the case of manufacturing transistors with short channel lengths, OS transistors are more preferred than Si transistors.

[0251] When the carrier concentration of the oxide semiconductor is reduced until the channel formation region becomes i-type or substantially i-type, in a short channel transistor, the lower end of the conduction band of the channel formation region decreases due to the conduction-band-lowering (CBL) effect, and thus the energy difference between the lower end of the conduction band of the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Therefore, the OS transistor can also be regarded as a channel formation region becoming n-type. - type region and the source region and drain region become n + n + / n - / n + Accumulation type junction-less transistor structure or n + / n - / n + Accumulation-type non-junction transistor structure.

[0252] By having the above structure, the OS transistor can have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, a short channel effect occurs in Si transistors, so it is sometimes difficult to set the gate length to less than 20nm or less than 15nm. Therefore, compared with Si transistors, OS transistors can be suitable for transistors with short channel lengths. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is operating.

[0253] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz at room temperature.

[0254] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a short channel length.

[0255] [[Impurities in metal oxides]] Here, the influence of each impurity in the metal oxide (oxide semiconductor) is described.

[0256] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0257] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×1018 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0258] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, thereby sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0259] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0260] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0261] [Other semiconductor materials] The oxide semiconductor 42 may be referred to as a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero band gap semiconductor) may also be used. For example, it is preferred to use a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) for the semiconductor material.

[0262] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. A layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0263] As single element semiconductors that can be used as semiconductor materials, silicon and germanium can be cited. As silicon that can be used for the semiconductor layer, single crystal silicon, polycrystalline silicon, microcrystalline silicon and amorphous silicon can be cited. As polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited.

[0264] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals having a cubic crystal structure.

[0265] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0266] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as a semiconductor layer, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0267] As described above, at least a part of the structure, method, etc. described in this embodiment mode can be implemented in combination with other embodiments described in this specification as appropriate.

[0268] (Implementation Method 2) In this embodiment, a structural example of the transistor 20 described in the above embodiment will be described with reference to FIGS. 9 to 16 .

[0269] <Structural Example of Semiconductor Device> 9A to 9D 1 and 2 are a top view and a cross-sectional view of a semiconductor device (transistor 200 ). Fig.9A is a top view of the semiconductor device. FIG. 9B to FIG. 9D is a cross-sectional view of the semiconductor device. Fig. 9B It is along Fig.9A The cross-sectional view of the portion of the dot-dash line A1-A2 in FIG. 1 is also a cross-sectional view of the transistor 200 in the channel length direction. Fig. 9C It is along Fig.9A The cross-sectional view of the portion of the dot-dash line A3-A4 in FIG. 1 is also a cross-sectional view of the transistor 200 in the channel width direction. Fig.9D It is along Fig.9A The cross-sectional view of the portion of the dotted line A5-A6 in FIG. 1 is also a cross-sectional view in the channel width direction of the transistor 200. Note that Fig.9A In the top view of FIG. , some components are omitted for clarity. FIG. 10A to FIG. 15D FIG. 2 is an enlarged cross-sectional view of the channel length direction of the transistor 200. Fig.16A and Fig. 16B A cross-sectional view of the transistor 200 along the channel length direction is shown.

[0270] Transistor 200 includes a conductor 205 (conductor 205a and conductor 205b) arranged in a manner embedded in an insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

[0271] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulator 255, the insulator 250, and the conductor 260 are arranged inside the openings provided in the insulators 280 and 275. In addition, an insulator 282 is provided on the insulator 280 and the conductor 260. In addition, an insulator 283 is provided on the insulator 282. In addition, an insulator 215 is provided on the substrate (not shown), and an insulator 216 and the conductor 205 are provided on the insulator 215. An insulator 255 is provided between the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, the insulator 280, and the insulator 250.

[0272] Here, the transistor 200 corresponds to the transistor 20 described in Embodiment 1. That is, the oxide 230 corresponds to the oxide semiconductor 22 , the conductor 242 a corresponds to the conductor 24 a , the conductor 242 b corresponds to the conductor 24 b , the insulator 250 corresponds to the insulator 28 , the conductor 260 corresponds to the conductor 26 , and the insulator 280 corresponds to the insulator 34 .

[0273] The oxide 230 has a region used as a channel formation region of the transistor 200. In addition, the conductor 260 has a region used as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region used as a first gate insulator of the transistor 200. In addition, the conductor 205 has a region used as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 224, the insulator 222, and the insulator 221 all have a region used as a second gate insulator of the transistor 200.

[0274] The conductor 242a has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b has a region that functions as the other of a source electrode and a drain electrode of the transistor 200.

[0275] The oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By providing the oxide 230a below the oxide 230b, it is possible to suppress diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b.

[0276] This embodiment shows an example in which the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b , but the present invention is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b or a stacked-layer structure of three or more layers.

[0277] The oxide 230b has a channel formation region of the transistor 200 and a source region and a drain region disposed so as to sandwich the channel formation region. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region may be swapped.

[0278] Since the channel formation region has fewer oxygen vacancies or lower impurity concentration than the source region and the drain region, the channel formation region is a high resistance region with low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0279] In addition, the source region and the drain region have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, and are therefore low-resistance regions with high carrier concentrations. That is, the source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentrations than the channel formation region.

[0280] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 Below, less than 1×10 17 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm -3 , less than 1×10 13 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the channel formation region, and it can be, for example, 1×10-9 cm -3 .

[0281] In the case where the purpose is to reduce the carrier concentration of the oxide 230b, the impurity concentration in the oxide 230b can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0282] Therefore, in order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. In order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0283] In addition, the channel formation region, the source region, and the drain region may be formed not only in the oxide 230 b but also in the oxide 230 a .

[0284] In the oxide 230, it is sometimes difficult to clearly observe the boundaries between the regions. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to change in stages for each region, but may change continuously in each region. That is, the closer to the channel formation region, the lower the concentrations of the metal elements and impurity elements such as hydrogen and nitrogen may be.

[0285] Note that a metal oxide serving as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a and the oxide 230 b ).

[0286] As described above, the band gap of the metal oxide used as a semiconductor is preferably larger than the band gap of silicon. The off-state current of the OS transistor using the metal oxide with a wider band gap is small, so the power consumption of the semiconductor device can be sufficiently reduced. In addition, the frequency characteristics of the OS transistor are high, so the semiconductor device can be operated at high speed.

[0287] The oxide 230 preferably includes a metal oxide (oxide semiconductor). As metal oxides that can be used for the oxide 230, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three selected from indium, element M and zinc. In addition, the element M is a metal element or a metalloid element with a high bond energy with oxygen, for example, a metal element or a metalloid element with a bond energy with oxygen higher than that of indium. Specifically, as the element M, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In addition, in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include metalloid elements.

[0288] The oxide 230 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0289] At this time, by increasing the atomic number ratio of indium contained in the metal oxide relative to the total atomic number of all metal elements, the field effect mobility of the transistor can be increased.

[0290] In addition, the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. The greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As a metal element with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. In addition, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0291] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0292] In addition, by increasing the ratio of the number of zinc atoms contained in the metal oxide to the total number of atoms of all metal elements, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0293] In addition, by increasing the atomic number ratio of the element M contained in the metal oxide relative to the sum of the atomic numbers of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the change of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0294] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0295] The oxide 230 preferably has a stacked structure of a plurality of oxide layers having different chemical compositions. For example, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to the metal element of the main component is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to the metal element of the main component. In addition, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to In is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to In. By adopting this structure, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b.

[0296] In addition, the atomic number ratio of In in the metal oxide used for oxide 230b to element M is preferably greater than the atomic number ratio of In in the metal oxide used for oxide 230a to element M. With this structure, transistor 200 can obtain large on-state current and high frequency characteristics.

[0297] In addition, since oxide 230a and oxide 230b contain a common element as a main component in addition to oxygen, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. The defect state density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, so that transistor 200 can obtain a large on-state current and high frequency characteristics.

[0298] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto can be used. In addition, as the oxide 230b, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto can be used. Alternatively, as the oxide 230b, a metal oxide that does not contain the element M and has a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto or a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto can be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M. In addition, in the case where a single layer of oxide 230b is provided as the oxide 230, a metal oxide that can be used for oxide 230a can also be used as the oxide 230b. In addition, the composition of the metal oxide that can be used for oxide 230a and oxide 230b is not limited thereto. For example, the composition of the metal oxide that can be used for oxide 230a can also be applied to oxide 230b. Similarly, the composition of the metal oxide that can be used for oxide 230b can also be applied to oxide 230a.

[0299] As either or both of the oxide 230a and the oxide 230b, metal oxides of the above composition may be stacked. For example, the oxide 230b may be a stacked film in which a metal oxide layer of In:Zn=4:1 [atomic ratio] and a metal oxide layer of In:Ga:Zn=1:1:1 [atomic ratio] are stacked in sequence. In addition, in the above-mentioned oxide 230b, a metal oxide layer of In:Ga:Zn=1:3:2 [atomic ratio] or a metal oxide layer of In:Ga:Zn=1:3:4 [atomic ratio] may be used instead of the metal oxide layer of In:Ga:Zn=1:1:1 [atomic ratio].

[0300] The metal oxide may be deposited by sputtering, CVD, MBE, PLD or ALD. In addition, the above deposition methods may be combined. For example, a structure in which the oxide 230a is deposited by sputtering and the oxide 230b is deposited by ALD may be adopted. In addition, when the metal oxide is deposited by sputtering, the atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0301] In addition, if Fig.11A and Fig. 11B As shown, the oxide 230 may also have a three-layer stacked structure of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. Here, as the oxide 230c, a metal oxide that can be used as the oxide 230a can be used. The oxide 230c is processed into an island shape after being continuously deposited with the oxide 230a and the oxide 230b. Therefore, when viewed from a plane, the end of the oxide 230c is consistent or approximately consistent with the end of the oxide 230a and the end of the oxide 230b. In addition, the oxide 230c is in contact with the insulator 250 in the region sandwiched between the conductor 242a and the conductor 242b. Fig.11A is corresponding to Fig. 9B The enlarged picture of Fig. 11B is corresponding to Fig. 9C Magnified image of .

[0302] In the above structure, for example, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto can be used as the oxide 230a, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto or a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto can be used as the oxide 230b, and a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto can be used as the oxide 230c. For example, the thickness of the oxide 230a and the oxide 230c can be set to about 1 nm, and the thickness of the oxide 230b can be set to about 3 nm to 5 nm.

[0303] Here, it is preferred that the conduction band bottom energy of oxide 230a and oxide 230c is higher than the conduction band bottom energy of oxide 230b. In other words, the electron affinity of oxide 230a and oxide 230c is preferably smaller than the electron affinity of oxide 230b. For example, the difference between the conduction band bottom energy (electron affinity) of oxide 230a and oxide 230c and the conduction band bottom energy (electron affinity) of oxide 230b is preferably 0.05 eV or more and less than 0.3 eV.

[0304] By adopting the above structure, the on-state current of the transistor 200 can be increased, and a transistor structure with less variation and high reliability can be realized.

[0305] The three-layer structure of oxide 230 is not limited to Fig.11A and Fig. 11B For example, it is also possible to use Fig. 12A and Fig. 12B The structure shown. Fig. 12A and Fig. 12B In the illustrated structure, oxide 230c is provided in contact with the bottom surface and the side surface of insulator 250. Therefore, oxide 230c is covered by insulator 250 in the openings formed in insulator 280 and insulator 275. In addition, oxide 230c is in contact with oxide 230b in a region sandwiched between conductor 242a and conductor 242b. Fig. 12A is corresponding to Fig. 9B The enlarged picture of Fig. 12B is corresponding to Fig. 9C Magnified image of .

[0306] In the transistor 200 , the oxide 230 b preferably has crystallinity. In particular, CAAC-OS is preferably used as the oxide 230 b.

[0307] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0308] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide with CAAC-OS has heat resistance and high reliability.

[0309] In addition, by using a crystalline oxide such as CAAC-OS as the oxide 230 b, the source electrode or the drain electrode can suppress the extraction of oxygen from the oxide 230 b. Therefore, even if heat treatment is performed, the extraction of oxygen from the oxide 230 b can be reduced, so that the transistor 200 is also stable to the high temperature (so-called thermal budget) in the manufacturing process.

[0310] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, and reliability may be reduced. In addition, hydrogen near the oxygen vacancies forms V O H may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor will have a normally-on characteristic. Therefore, in the channel formation region of the oxide semiconductor, it is preferred to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0311] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V OH. Note that when too much oxygen is supplied to the source region or the drain region, the on-state current of the transistor 200 may decrease or the field effect mobility may decrease. Furthermore, when the amount of oxygen supplied to the source region or the drain region is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor become uneven. In addition, when the oxygen supplied from the insulator to the oxide semiconductor diffuses to the conductor such as the gate electrode, the source electrode and the drain electrode, the conductor is sometimes oxidized, which leads to a loss of conductivity, thereby having a negative impact on the electrical characteristics and reliability of the transistor.

[0312] Therefore, in the oxide semiconductor, it is preferred that the carrier concentration of the channel formation region is reduced and the region is i-type or substantially i-type, while it is preferred that the carrier concentration of the source region and the drain region is high and the region is n-type. In other words, it is preferred to reduce oxygen vacancies and V O H. In addition, it is preferable that the source region and the drain region are not supplied with excessive oxygen and the V of the source region and the drain region are not excessively reduced. O H content. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce V O H amount, it is necessary to reduce the hydrogen concentration.

[0313] Therefore, the semiconductor device in this embodiment has a structure in which the hydrogen concentration in the channel formation region is reduced, oxidation of the conductors 242a, 242b, and 260 is suppressed, and reduction in the hydrogen concentration in the source region and the drain region is suppressed.

[0314] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of trapping or fixing hydrogen. Thus, the hydrogen concentration in the channel formation region of the oxide 230b can be reduced. Therefore, the V O H makes the channel formation region i-type or substantially i-type.

[0315] Here, if Fig. 10A As shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. At this time, the insulator 250a and the insulator 250c preferably have the function of capturing or fixing hydrogen.

[0316] As an insulator having the function of capturing or fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulator 250a and the insulator 250c, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used. The above-mentioned metal oxide having an amorphous structure sometimes has the following property: the oxygen atom has a dangling bond and hydrogen is captured or fixed by the dangling bond. That is, it can be said that the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0317] In addition, the insulator 250a and the insulator 250c preferably use a high dielectric constant (high-k) material. As an example of a high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a and the insulator 250c, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0318] As the insulator 250 a and the insulator 250 c , it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0319] In this embodiment, an aluminum oxide film is used as the insulator 250a. In addition, the aluminum oxide preferably has an amorphous structure. Here, by providing the insulator 250a in contact with the oxide 230b, hydrogen contained in the oxide 230b and the like can be more effectively captured and fixed.

[0320] In this embodiment, hafnium oxide is used as the insulator 250c. Here, by providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0321] Next, as the insulator 250b, an insulator having thermal stability, such as silicon oxide or silicon oxynitride, is preferably used. Note that in this specification, etc., "oxynitride" refers to a material whose oxygen content is higher than the nitrogen content, and "nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content. For example, "silicon oxynitride" refers to a material whose oxygen content is higher than the nitrogen content, and "silicon nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content.

[0322] Furthermore, in order to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulators 250a, 250c, 250d, 255, and 275.

[0323] Note that in this specification, etc., a blocking insulator refers to an insulator having a barrier property. In this specification, etc., having a barrier property means having a property of hindering the penetration of a corresponding substance (also referred to as low permeability). For example, an insulator having a barrier property has a property that a corresponding substance does not easily diffuse into the inside of the insulator. For example, an insulator having a barrier property has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0324] As oxygen blocking insulators, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride can be cited. In addition, as oxides containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate) can be cited. For example, insulators 250a, 250c, 250d, 255, and 275 preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen blocking insulators. For example, when a stacked-layer structure is adopted as insulator 255, a two-layer structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film can be adopted.

[0325] The insulator 250a and the insulator 255 preferably have oxygen barrier properties. The insulator 250a and the insulator 255 are preferably less likely to allow oxygen to penetrate than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a1 and the side surface of the conductor 242b1. The insulator 255 has a region in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the top surface of the conductor 242a2, and the top surface of the conductor 242b2. The insulator 250a is in contact with the side surface of the insulator 255. When the insulator 250a and the insulator 255 have oxygen barrier properties, the side surfaces of the conductor 242a and the conductor 242b can be prevented from being oxidized and an oxide film can be formed on the side surfaces. Therefore, a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility can be prevented.

[0326] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. When the insulator 250a has oxygen barrier properties, it is possible to suppress the detachment of oxygen from the channel formation region of the oxide 230b during heat treatment, etc. Therefore, the formation of oxygen vacancies in the oxides 230a and 230b can be reduced.

[0327] In addition, by providing the insulator 250a and the insulator 255, even if the insulator 280 contains too much oxygen, it is possible to suppress the excessive supply of oxygen to the oxide 230a and the oxide 230b, and to supply an appropriate amount of oxygen to the oxide 230a and the oxide 230b. Therefore, it is possible to suppress a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility due to excessive oxidation of the source region and the drain region.

[0328] Since an oxide containing one or both of aluminum and hafnium has an oxygen barrier property, it can be suitably used as the insulator 250 a .

[0329] In addition, silicon nitride also has oxygen barrier properties, so it can be appropriately used as the insulator 255. In this case, the insulator 255 is an insulator containing at least nitrogen and silicon. In addition, the insulator 255 preferably has hydrogen barrier properties. Thus, impurities such as hydrogen in the conductors 242a2 and 242b2 can be prevented from diffusing into the oxide 230b.

[0330] The insulator 250d also preferably has oxygen barrier properties. The insulator 250d is provided between the channel formation region of the oxide 230 and the conductor 260 and between the insulator 280 and the conductor 260. By adopting this structure, it is possible to suppress the diffusion of oxygen in the channel formation region of the oxide 230 into the conductor 260 and the formation of oxygen vacancies in the channel formation region of the oxide 230. In addition, it is possible to suppress the diffusion of oxygen in the oxide 230 and oxygen in the insulator 280 into the conductor 260 and the oxidation of the conductor 260. The insulator 250d is preferably at least less likely to allow oxygen to permeate than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0331] In addition, the insulator 250d preferably has a hydrogen barrier property, so that impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide 230b.

[0332] Insulator 275 also preferably has oxygen barrier properties. Insulator 275 is provided between insulator 280 and conductor 242a and between insulator 280 and conductor 242b. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in insulator 280 into conductor 242a and conductor 242b. Therefore, it is possible to suppress the oxidation of conductor 242a and conductor 242b caused by oxygen contained in insulator 280, thereby increasing resistivity and reducing on-state current. Insulator 275 is preferably at least less likely to allow oxygen to penetrate than insulator 280. For example, silicon nitride is preferably used as insulator 275. At this time, insulator 275 is an insulator containing at least nitrogen and silicon.

[0333] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region in the oxide 230 , a hydrogen blocking insulator is preferably provided near the source region and near the drain region. In the semiconductor device described in this embodiment, the hydrogen blocking insulator is, for example, the insulator 275 .

[0334] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked-layer structure of the above hydrogen barrier insulators.

[0335] By providing the insulator 275, the diffusion of hydrogen from the source region and the drain region to the outside can be reduced, thereby suppressing the reduction of the hydrogen concentration in the source region and the drain region. Therefore, the source region and the drain region can be made n-type.

[0336] By adopting the above structure, the channel forming region can be i-type or substantially i-type and the source region and the drain region can be n-type, and a semiconductor device with good electrical characteristics can be provided. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the high-frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0337] Insulators 250a to 250d are used as part of the gate insulator. Insulators 250a to 250d are arranged in an opening formed in insulator 280 together with insulator 255 and conductor 260. In order to achieve miniaturization of transistor 200, the thickness of insulators 250a to 250d is preferably thin. The thickness of insulators 250a to 250d is preferably 0.1nm or more and 10nm or less, more preferably 0.1nm or more and 5.0nm or less, further preferably 0.5nm or more and 5.0nm or less, further preferably 1.0nm or more and less than 5.0nm, and further preferably 1.0nm or more and 3.0nm or less. In addition, at least a portion of insulators 250a to 250d includes an area of ​​the above-mentioned thickness.

[0338] In order to reduce the thickness of the insulators 250a to 250d as described above, it is preferred to use atomic layer deposition (ALD) for deposition. In addition, in order to set the insulators 250a to 250d and the insulator 255 in the opening of the insulator 280, etc., it is preferred to use the ALD method for deposition. The ALD method includes a thermal ALD method that uses only thermal energy to react precursors and reactants, and a PEALD (Plasma Enhanced ALD) method that uses reactants excited by plasma. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred.

[0339] The ALD method can deposit atoms in layers, and thus has the advantages of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. Therefore, the insulators 250 and 255 can be deposited with the aforementioned small thickness and high coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b.

[0340] The precursor used in the ALD method sometimes contains carbon, etc. Therefore, the film formed by the ALD method sometimes contains more impurities such as carbon than the film formed by other deposition methods. In addition, the quantitative analysis of impurities can be performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or Auger electron spectroscopy (AES: Auger Electron Spectroscopy).

[0341] Note that in the above description, the insulator 250 has a four-layer structure of the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of the insulators 250a to 250d. By forming the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving productivity.

[0342] For example, Fig.13A As shown, the insulator 250 may also have a two-layer structure. In this case, the insulator 250 preferably has a stacked structure of an insulator 250a and an insulator 250d on the insulator 250a. A high-k material may be used for at least one of the insulator 250a and the insulator 250d. Thus, the equivalent oxide thickness (EOT) can be reduced while the thickness of the insulator 250a and the insulator 250d is maintained to a degree that suppresses leakage current.

[0343] For example, Fig. 13B As shown, the insulator 250 may also have a three-layer structure. In this case, the insulator 250 preferably has a stacked structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250d on the insulator 250b. Fig.13A The structure shown is further provided with an insulator 250b.

[0344] In this embodiment, it is preferred that the semiconductor device has a structure for suppressing the mixing of hydrogen into the transistor 200, etc. in addition to the above-mentioned structure. For example, it is preferred that an insulator having a function of suppressing the diffusion of hydrogen is provided in a manner covering one or both of the upper and lower parts of the transistor 200, etc. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 283, an insulator 282, an insulator 222, and an insulator 221, etc. In addition, the insulator 215 under the transistor 200 may also have the same structure as either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a stacked structure of the insulator 282 and the insulator 283, and may adopt a structure in which the insulator 282 is located at the bottom and the insulator 283 is located at the top, or may adopt a structure in which the insulator 282 is located at the top and the insulator 283 is located at the bottom.

[0345] One or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 are preferably used as a blocking insulator to inhibit impurities such as water and hydrogen from diffusing from the substrate side or above the transistor 200 to the transistor 200. Therefore, one or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably contain an insulating material that does not easily diffuse (does not easily allow the above impurities to pass through) impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferred to contain an insulating material that does not easily diffuse (does not easily allow the above oxygen to pass through) oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0346] Insulator 283, insulator 282, insulator 222, and insulator 221 preferably all include an insulator having a function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen, and for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride, etc., can be used. For example, silicon nitride with higher hydrogen barrier properties is preferably used for insulator 283 and insulator 221. In addition, for example, aluminum oxide with high ability to capture or fix hydrogen is preferably used for insulator 282. In addition, for example, hafnium oxide with high ability to capture or fix hydrogen and a high dielectric constant (high-k) material is preferably used for insulator 222.

[0347] By adopting such a structure, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed above the insulator 283 to the transistor 200 or the like. In addition, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed below the insulator 221 to the transistor 200 or the like. In addition, hydrogen in the insulators 280, 224, and 250 or the like can be captured or fixed to the insulator 282 or the insulator 222. In addition, by providing the insulators 282 and 283, it is possible to suppress oxygen in the insulators 280 or the like from diffusing to the top of the transistor 200 or the like. In addition, by providing the insulators 222 and 221, it is possible to suppress oxygen in the insulators 224 or the like from diffusing to the bottom of the transistor 200 or the like. In this way, by adopting a structure in which the upper and lower parts of the transistor 200 are surrounded by an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen to the oxide semiconductor. Thus, it is possible to achieve improvement in the electrical characteristics and reliability of the semiconductor device.

[0348] In addition, the insulator 255, the insulator 275, and the insulator 250d are preferably made of silicon nitride or the like having a higher hydrogen barrier property. In addition, the insulator 250a is preferably made of aluminum oxide or the like having a high ability to capture or fix hydrogen. In addition, the insulator 250c is preferably made of hafnium oxide or the like having a high ability to capture or fix hydrogen.

[0349] Here, it is preferable that the region of the insulator 275 that does not overlap with the oxide 230 is in contact with the insulator 222, the side end of the insulator 275 is in contact with the insulator 255, and the upper end of the insulator 255 and the upper ends of the insulators 250a to 250d are in contact with the insulator 282. With the above structure, in the region sandwiched between the insulator 283 and the insulator 221, the insulator 280 is separated from the oxide 230 by the insulator 275, the insulator 255 and the insulator 250a are separated from the insulator 280b, the conductor 260 is separated from the insulator 250b by the insulator 250d, and the conductors 242a2 and 242b2 are separated from the insulator 250b by the insulator 255 and the insulator 250a.

[0350] Thus, it is possible to suppress the diffusion of impurities such as water and hydrogen in the insulator 280 to the oxide 230 and the insulator 250b. In addition, it is possible to suppress the diffusion of impurities such as water and hydrogen in the conductor 260 to the oxide 230 through the insulator 250b. In addition, it is possible to suppress the diffusion of impurities such as water and hydrogen in the conductor 242a2 and the conductor 242b2 to the oxide 230 through the insulator 250b. For example, even if a contact plug is formed in contact with the top surface of the conductor 242a2 and the conductor 242b2 and impurities such as water and hydrogen diffuse to the conductor 242a2 and the conductor 242b2 through the contact plug, the diffusion of impurities such as water and hydrogen to the oxide 230 can be reduced. In addition, hydrogen in the insulator 250a and the insulator 250b can be captured and fixed to the insulator 282. By adopting such a structure, the diffusion of hydrogen to the oxide semiconductor can be further reduced. Thus, the electrical characteristics and reliability of the semiconductor device can be improved.

[0351] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Fig.9A and Fig. 9C As shown in FIG. 1 , the conductor 205 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 205 can be used as wiring when a plurality of transistors are arranged.

[0352] like Fig. 9B and Fig. 9C As shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in a manner of contacting the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is provided in a manner of being embedded in the concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is consistent or substantially consistent with the height of the top surface of the insulator 216.

[0353] Here, as the conductor 205a, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Alternatively, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0354] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide 230 through the insulator 216 and the like. In addition, by using a conductive material having a function of inhibiting oxygen diffusion as the conductor 205a, it is possible to inhibit the conductor 205b from being oxidized and the conductivity from being reduced. As the conductive material having a function of inhibiting oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a can have a single-layer structure or a laminated structure of the above-mentioned conductive material. For example, the conductor 205a preferably contains titanium nitride.

[0355] In addition, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0356] The conductor 205 can be used as a second gate electrode. In this case, the Vth of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced compared to the case where a negative potential is not applied to the conductor 205.

[0357] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to the resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferred to reduce the thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so the diffusion of the impurities into the oxide 230 can be reduced.

[0358] Note that in the above structure, a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 205 has a three-layer stacked structure, the stacked structure of the conductor 205a and the conductor 205b described above may be adopted, and a conductor made of the same material as the conductor 205a may be provided on the conductor 205b. In this case, the conductor may be formed in a manner embedded in a recess formed by the conductor 205a and the conductor 205b, and the recess is formed in a manner such that the top surface of the conductor 205b is lower than the uppermost portion of the conductor 205a.

[0359] The insulator 224 , the insulator 221 , and the insulator 222 are used as gate insulators.

[0360] The insulator 224 in contact with the oxide 230 preferably includes, for example, silicon oxide or silicon oxynitride. Thus, oxygen can be supplied from the insulator 224 to the oxide 230 to reduce oxygen vacancies.

[0361] In addition, the insulator 224 is preferably processed into an island shape in the same manner as the oxide 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 includes an insulator 224 of substantially the same size. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 is substantially equal. Thus, the non-uniformity of the electrical characteristics of the transistor 200 within the substrate surface can be suppressed. Note that the present invention is not limited to this, and a structure in which the pattern of the insulator 224 is not formed in the same manner as the insulator 222 may be adopted.

[0362] In addition, the insulator 224 may have a stacked structure of two or more layers. In this case, the insulator 224 is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0363] As the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thus, the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed from decreasing. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least metal and nitrogen.

[0364] exist Fig. 9BIn the embodiment, the conductors 242a and 242b have a two-layer structure. The conductor 242a is a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. At this time, as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), it is preferred to use the above-mentioned conductive material that is not easily oxidized or a conductive material having the function of inhibiting oxygen diffusion. This can inhibit the conductivity of the conductors 242a and 242b from being reduced. In addition, it can inhibit oxygen from being extracted from the oxide 230b to form excessive oxygen vacancies. In addition, by using a material that easily absorbs (extracts) hydrogen as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), the hydrogen concentration of the oxide 230 can be reduced, so it is preferred.

[0365] As the conductors 242a1 and 242b1, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferred.

[0366] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, when a nitride containing tantalum is used as the conductor 242a1 or the conductor 242b1, hydrogen contained in the oxide 230b or the like may easily diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0367] The electrical conductivity of the conductor 242a2 and the conductor 242b2 is preferably higher than that of the conductor 242a1 and the conductor 242b1. For example, the thickness of the conductor 242a2 and the conductor 242b2 is preferably greater than that of the conductor 242a1 and the conductor 242b1. As the conductor 242a2 and the conductor 242b2, a conductor that can be used for the conductor 205b described above can be used. By adopting the above structure, the resistance of the conductor 242a2 and the conductor 242b2 can be reduced. As a result, the operating speed of the semiconductor device according to this embodiment can be improved.

[0368] For example, tantalum nitride or titanium nitride can be used as the conductor 242 a 1 and the conductor 242 b 1 , and tungsten can be used as the conductor 242 a 2 and the conductor 242 b 2 .

[0369] In addition, in order to suppress the decrease in the conductivity of the conductors 242a and 242b, a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b. In particular, it is preferred to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. When CAAC-OS is used, it is possible to suppress the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. In addition, it is possible to suppress the decrease in the conductivity of the conductors 242a and 242b.

[0370] like Fig. 9B and Fig. 9C As shown, insulator 255 is arranged in an opening formed in insulator 280 or the like, and is in contact with the side surface of insulator 280, the side surface of insulator 275, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of conductor 242a2, the side surface of conductor 242b2, the top surface of conductor 242a1, the top surface of conductor 242b1, and the top surface of insulator 222. In other words, insulator 255 is formed in contact with the side wall of the opening formed in insulator 280 or the like. That is, insulator 255 can be called a sidewall insulating film. In addition, as Fig. 9C As shown, a portion of the insulator 255 may be formed so as to be in contact with the side surface of the oxide 230 and the side surface of the insulator 224 .

[0371] The insulator 255 is formed in a manner in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, it is preferably an inorganic insulator that is not easily oxidized. In addition, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferably an inorganic insulator that is not easily oxidized by the conductor 242a2 and the conductor 242b2. Therefore, the insulator 255 preferably uses an insulating material that can be used for the insulator 250d having oxygen barrier properties. For example, silicon nitride can be used as the insulator 255.

[0372] By using such an insulator 255, even if heat treatment is performed in an oxygen-containing atmosphere after separation into the conductor 242a1 and the conductor 242b1 and before deposition of the insulator 250, the conductor 242a2 and the conductor 242b2 are not excessively oxidized.

[0373] In addition, the thickness of the insulator 255 is preferably not less than 0.5 nm and not more than 20 nm, more preferably not less than 0.5 nm and not more than 10 nm, and further preferably not less than 0.5 nm and not more than 3 nm. When the insulator 255 has the above thickness, the conductor 242a2 and the conductor 242b2 can be suppressed from being over-oxidized. Note that the insulator 255 only needs to have a region with a thickness of the above value in at least a portion thereof. In addition, since the insulator 255 is arranged in a manner in contact with the side wall of the opening formed in the insulator 280, etc., it is preferably deposited using an ALD method with high coverage. When the thickness of the insulator 255 is too large, the deposition time of the insulator 255 using the ALD method is long, resulting in a decrease in productivity, so it is preferred to set the thickness of the insulator 255 approximately within the above range.

[0374] In addition, the insulator 255 may also have a stacked structure of two or more layers. In this case, it is sufficient as long as at least one layer is the inorganic insulator that is not easily oxidized. Fig. 13C As shown, a laminated structure of an insulator 255a and an insulator 255b on the insulator 255a may be adopted. In addition, a structure in which the insulator 255b is arranged inside the insulator 255a may be regarded. Here, the bottom surface of the insulator 255b is sometimes in contact with the insulator 255a. The above-mentioned inorganic insulator that is not easily oxidized can be used for the insulator 255a.

[0375] Insulator 255b preferably uses an oxide insulator that can be used for insulator 250b. For example, silicon oxide can be used as insulator 255b. Insulator 255b preferably has a lower dielectric constant than insulator 255a. In this way, by increasing the thickness by adopting a two-layer structure as insulator 255, the distance between conductor 260 and conductor 242a or conductor 242b can be increased to reduce parasitic capacitance.

[0376] In addition, as the insulator 255b, an oxide insulator that can be used for the insulator 250a can also be used. For example, as the insulator 255b, aluminum oxide or hafnium oxide can be used. As described above, aluminum oxide and hafnium oxide have the function of capturing or fixing hydrogen. By using such an oxide insulator for the insulator 255b, the hydrogen concentration in the channel formation region of the insulator 250 and the oxide 230b and in the vicinity of the channel formation region can be reduced. Therefore, the V in the channel formation region can be reduced. O H makes the channel formation region i-type or substantially i-type.

[0377] Notice, Fig. 13C The structure in which the insulator 255a is arranged on the outside and the insulator 255b is arranged on the inside is shown, but the present invention is not limited to this. Fig.13DAs shown in FIG. 1 , a structure in which the insulator 255b is arranged on the outside and the insulator 255a is arranged on the inside may be adopted. Here, the bottom surface of the insulator 255a may be in contact with the insulator 255b.

[0378] Notice, Fig. 13C The structure in which the side surface of the insulator 255 on the side of the conductor 260 is substantially consistent with the side surface of the conductor 242a1 or the conductor 242b1 on the side of the conductor 260 is shown, but the present invention is not limited to this. Fig.13E As shown in FIG. 1 , the side surface of the insulator 255 on the conductor 260 side may be set back from the side surface of the conductor 242a1 or the conductor 242b1 on the conductor 260 side. In this case, the insulator 250a contacts a portion of the top surface of the conductor 242a1 or the conductor 242b1. By adopting this structure, the distance between the conductor 242a1 and the conductor 242b1 can be Fig. 13C The structure shown in FIG. 1 is the same as that shown in FIG. 1 while increasing the width of the top of the conductor 260. Fig. 13C Compared to the structure shown, Fig.13E The structure shown can reduce the resistance of the conductor 260 used as wiring.

[0379] In addition, when dividing into the conductor 242a1 and the conductor 242b1, the insulator 255 is used as a mask. Fig. 9B As shown in FIG. 2 and FIG. 3 , when the transistor 200 is cross-sectionally viewed, the side end portion of the insulator 255 is preferably aligned or substantially aligned with the side end portion of the conductor 242 a 1 and the side end portion of the conductor 242 b 1 .

[0380] When the side ends are consistent or roughly consistent in cross-section and when the top surface shapes are consistent or roughly consistent, it can be said that at least a portion of their contours overlap each other between the stacked layers when viewed from above. For example, this includes the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern. In addition, for example, this includes the case where the upper layer is used as a mask to process the lower layer. However, in reality, there are cases where the contours do not overlap, and sometimes a portion of the upper layer is located on the inner side of the lower layer or a portion of the upper layer is located on the outer side of the lower layer. In this case, it can also be said that "the side ends are consistent or roughly consistent" or "the top surface shapes are consistent or roughly consistent."

[0381] Here, in the conductor 242a1, the portion on the top surface of which the insulator 255 is formed is formed so as to protrude toward the conductor 260 side from the conductor 242a2. Similarly, in the conductor 242b1, the portion on the top surface of which the insulator 255 is formed is formed so as to protrude toward the conductor 260 side from the conductor 242b2. Fig. 10BAs shown, when the transistor 200 is cross-sectionally viewed in the channel length direction, the distance L2 between the conductors 242a1 and 242b1 is smaller than the distance L1 between the conductors 242a2 and 242b2. Specifically, the difference between L1 and L2 is equal to or substantially equal to twice the thickness of the insulator 255.

[0382] The distance L2 between the conductor 242a1 and the conductor 242b1 is preferably very small because it reflects on the channel length of the transistor 200. For example, the distance L2 is preferably less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm, or less than 10nm and more than 1nm or more than 5nm. For example, the distance L2 is more preferably about more than 2nm and less than 20nm. By adopting this structure, the distance between the source and the drain can be further shortened and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0383] like Fig.14A As shown, a recess may be formed in the portion of oxide 230b exposed from conductor 242a1 and conductor 242b1. In other words, on the top surface of oxide 230b, the height of the region sandwiched between conductor 242a1 and conductor 242b1 may be smaller than the region overlapping with conductor 242a1 and the region overlapping with conductor 242b1.

[0384] In addition, Fig. 10A In the transistor 200 shown in FIG. 1 , the sides of the conductors 242a1 and 242b1 facing each other and the sides of the conductors 242a2 and 242b2 facing each other are perpendicular or substantially perpendicular to the top surface of the oxide 230b, but the present invention is not limited thereto. Fig. 14B As shown, the mutually opposing side surfaces of the conductors 242a1 and 242b1 and the mutually opposing side surfaces of the conductors 242a2 and 242b2 may also be tapered. In this case, the side surfaces of the insulators 271a, 271b, 275, and 280 may be tapered.

[0385] In addition, the taper angle of the conductors 242a1 and 242b1 may be smaller than the taper angle of the conductors 242a2 and 242b2.

[0386] In addition, if Fig. 14C As shown in FIG. 1 , the upper portion of the side surface of the insulator 255 is sometimes tapered. Fig. 14C As shown in FIG. 1 , sometimes a tapered shape that is continuous or substantially continuous with the tapered shape of the side surface of the insulator 255 is formed on the upper portion of the insulator 280. Fig. 14CAs shown, the upper portion of the insulator 255 and the upper portion of the insulator 280 may have a curved surface. Here, the insulator 250a may be in contact with the tapered portion of the upper portion of the insulator 255 and the upper portion of the insulator 280. At this time, when the upper portions of the insulator 255 and the insulator 280 have a curved surface, the insulator 250a can be formed with high coverage.

[0387] Note that Fig.14D As shown, transistor 200 may also have FIG. 14A to FIG. 14C That is, the portion of the oxide 230b exposed from the conductors 242a1 and 242b1 may have a recess, the side surfaces of the conductors 242a1 and 242b1 and the side surfaces of the conductors 242a2 and 242b2 may be tapered, and the upper portion of the side surface of the insulator 255 may be tapered.

[0388] In addition, Fig. 9B The structure in which the entire side surface of the insulator 255 is consistent or substantially consistent with the side end of the conductor 242a1 and the side end of the conductor 242b1 is shown in FIG. 2 , but the present invention is not limited to this. Fig.15A As shown in FIG. 1 , a portion of the side surface of the insulator 255 may be aligned or substantially aligned with the side end of the conductor 242a1 and the side end of the conductor 242b1. Fig.15A As shown, the portion of the insulator 255 that contacts the top surface of the conductor 242a1 or the top surface of the conductor 242b1 forms a protrusion. The protrusion of the insulator 255 is shaped to protrude toward the center of the opening formed in the insulator 280 or the like more than other portions. In other words, the insulator 255 can also be said to have a so-called L-shaped shape in the cross section in the channel length direction.

[0389] In addition, Fig. 9B In the above description, a portion of the conductor 242a1 and the conductor 242b1 has a structure in which a portion protrudes from the conductor 242a2 and the conductor 242b2, but the present invention is not limited to this. Fig. 15B As shown, the ends of the conductors 242a1 and 242b1 may be aligned or substantially aligned with the ends of the conductors 242a2 and 242b2. In this case, the insulator 255 is in contact with the ends of the conductors 242a1, 242a2, 242b1, and 242b2. In other words, the insulator 255 is not in contact with the top surfaces of the conductors 242a1 and 242b1, but is in contact with the top surface of the oxide 230b.

[0390] In addition, Fig. 9B The structure of providing the insulator 255 is shown in FIG. 1 , but the present invention is not limited thereto. Fig. 15CAs shown, the insulator 255 may not be provided. In this case, the insulator 250 contacts the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, and the side surface of the conductor 242b2.

[0391] In addition, Fig. 9B The structure in which the conductor 242a has a laminated structure of the conductor 242a1 and the conductor 242a2 and the conductor 242b has a laminated structure of the conductor 242b1 and the conductor 242b2 is shown in the figure, but the present invention is not limited to this. Fig.15D As shown, the conductors 242a and 242b may have a single-layer structure. In this case, the conductors 242a and 242b are in contact with the top surface of the oxide 230b, so the conductors 242a and 242b are preferably made of a conductive material that can be used for the conductors 242a1 and 242b1.

[0392] The insulators 271a and 271b are inorganic insulators used as etching stop layers to protect the conductors 242a2 and 242b2 during the processing of the conductors 242a2 and 242b2. In addition, since the insulators 271a and 271b are in contact with the conductors 242a2 and 242b2, inorganic insulators that are not easily oxidized by the conductors 242a and 242b are preferably used. Fig. 10A As shown, it is preferred that the insulator 271a has a stacked structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a stacked structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 preferably use a nitride insulator that can be used for the insulator 250d so as not to oxidize the conductors 242a2 and 242b2. In addition, in order to function as an etching stop layer, the insulators 271a2 and 271b2 preferably use an oxide insulator that can be used for the insulator 250b.

[0393] Here, the insulator 271a1 is in contact with the top surface of the conductor 242a2 and a part of the insulator 275, and the insulator 271b1 is in contact with the top surface of the conductor 242b2 and a part of the insulator 275. In addition, the insulator 271a2 is in contact with the top surface of the insulator 271a1 and the bottom surface of the insulator 275, and the insulator 271b2 is in contact with the top surface of the insulator 271b1 and the bottom surface of the insulator 275. For example, silicon nitride can be used as the insulator 271a1 and the insulator 271b1, and silicon oxide can be used as the insulator 271a2 and the insulator 271b2.

[0394] The insulators to be insulators 271a and 271b are used as masks for the conductors to be conductors 242a and 242b, so that conductors 242a and 242b do not have a curved surface between the side and the top surface. Thus, the ends where the side and top surfaces of conductors 242a and 242b intersect are angular. When the ends where the side and top surfaces of conductors 242a and 242b intersect are angular, the cross-sectional areas of conductors 242a and 242b are increased compared to the case where the ends have a curved surface. Furthermore, by using a nitride insulator that is not easy to oxidize metal as insulators 271a1 and 271b1, it is possible to prevent conductors 242a and 242b from being over-oxidized. Thus, the resistance of conductors 242a and 242b is reduced, so the on-state current of the transistor can be increased.

[0395] like Fig. 9B and Fig. 9C As shown, the conductor 260 is arranged in the opening formed in the insulator 280, the insulator 275, the insulator 255, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 230, the insulator 224, and the insulator 222. In the opening, the conductor 260 is provided so as to cover the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. In addition, the top surface of the conductor 260 is arranged so as to be consistent or substantially consistent with the height of the uppermost portion of the insulator 250, the uppermost portion of the insulator 255, and the top surface of the insulator 280.

[0396] In the opening in which the conductor 260 and the insulator 250 are arranged, the side wall of the opening may be vertical or substantially vertical to the top surface of the insulator 222, or may have a tapered shape. The tapered side wall can improve the coverage of the insulator 255 and the insulator 250 etc. provided in the opening of the insulator 280, thereby reducing defects such as voids.

[0397] The conductor 260 is used as a first gate electrode of the transistor 200. Fig.9A and Fig. 9C As shown in FIG. 1 , the conductor 260 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 260 can be used as wiring when a plurality of transistors are arranged.

[0398] In the case of adopting the above structure, if Fig. 9C As shown, when the transistor 200 is cross-sectionally viewed in the channel width direction, a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0399] The curvature radius of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide 230 b in the region overlapping the conductor 242 a and the conductor 242 b or less than half the length of the region without the curved surface. Specifically, the curvature radius of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the insulator 250 and the conductor 260 to the oxide 230 b can be improved.

[0400] In this specification, etc., a transistor structure in which a channel forming region is surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from a Fin-type structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In addition, in this specification, etc., a Fin-type structure refers to a structure in which a gate electrode is configured in a manner that surrounds at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, or four surfaces, etc.). By adopting a Fin-type structure and an S-channel structure, resistance to short channel effects can be improved, in other words, a transistor that is not prone to short channel effects can be realized.

[0401] By adopting the above-mentioned S-channel structure as transistor 200, the channel formation region can be electrically surrounded. The S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is substantially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be regarded as the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor will be improved.

[0402] This embodiment adopts a structure in which the insulator 224 is set to an island shape. Fig. 9CAs shown, at least a portion of the bottom surface of the conductor 260 can be disposed below the bottom surface of the oxide 230b. Thus, the conductor 260 can be disposed in a manner opposite to the top surface and the side surface of the oxide 230b, so that the electric field of the conductor 260 can act on the top surface and the side surface of the oxide 230b. In this way, by adopting a structure in which the insulator 224 is disposed in an island shape, the transistor 200 can have an S-channel structure.

[0403] Note that as Fig. 9C The transistor 200 shown is an S-channel structure transistor, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, as a structure of a transistor that can be used in one embodiment of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure can also be used.

[0404] exist Fig. 9B In the embodiment, the conductor 260 has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion.

[0405] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0406] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0407] In addition, the conductor 260b preferably uses a conductor with high conductivity. For example, the conductor 260b can use a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials.

[0408] In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fit into an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged to overlap the region between the conductor 242a1 and the conductor 242b1 without alignment.

[0409] The dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 222. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0410] For example, the insulator 216 and the insulator 280 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores.

[0411] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, silicon oxide, silicon oxynitride, silicon oxide having pores and the like are preferred because they easily form a region containing oxygen released by heating.

[0412] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0413] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0414] In addition, if Fig.16A As shown in FIG. 2 , a conductor used as wiring may be provided on the insulator 283. Fig.16A In the structure shown, openings reaching the conductor 242a, the conductor 242b, and the conductor 260 are formed in the insulators 283, 282, 280, 275, 271a, and 271b. Here, the conductor 240a and the insulator 241a are formed in the opening reaching the conductor 242a. In addition, the conductor 240b and the insulator 241b are formed in the opening reaching the conductor 242b. In addition, the conductor 240c and the insulator 241c are formed in the opening reaching the conductor 260. In addition, the conductor 240a, the conductor 240b, and the conductor 240c are sometimes collectively referred to as the conductor 240 below. In addition, the insulator 241a, the insulator 241b, and the insulator 241c are sometimes collectively referred to as the insulator 241.

[0415] In addition, Fig.16AIn the structure shown, an insulator 285 is provided on an insulator 283, and an insulator 286 is provided on an insulator 285. An opening through which the conductor 240a is exposed, an opening through which the conductor 240b is exposed, and an opening through which the conductor 240c is exposed are formed in the insulator 285 and the insulator 286. Here, a conductor 246a is formed in the opening through which the conductor 240a is exposed. In addition, a conductor 246b is formed in the opening through which the conductor 240b is exposed. In addition, a conductor 246c is formed in the opening through which the conductor 240c is exposed. In addition, below, the conductor 246a, the conductor 246b, and the conductor 246c are sometimes collectively referred to as the conductor 246.

[0416] Here, the transistor 200 corresponds to the transistor 20 described in Embodiment 1. That is, the conductor 240a corresponds to the conductor 30a, the conductor 240b corresponds to the conductor 30b, the conductor 240c corresponds to the conductor 30c, the conductor 246a corresponds to the conductor 32a, the conductor 246b corresponds to the conductor 32b, the conductor 246c corresponds to the conductor 32c, the insulator 285 corresponds to the insulator 36, and the insulator 286 corresponds to the insulator 38.

[0417] As the insulator 285 and the insulator 286 , the insulators that can be used for the insulator 280 can be used.

[0418] Conductor 240 is a conductor used as a plug. Here, conductor 240a has a region in contact with conductor 242a and a region in contact with at least a portion of the bottom surface of conductor 246a. In addition, conductor 240b has a region in contact with conductor 242b and a region in contact with at least a portion of the bottom surface of conductor 246b. In addition, conductor 240c has a region in contact with conductor 260 and a region in contact with at least a portion of the bottom surface of conductor 246c. That is, conductor 240a is electrically connected to one of the source and drain of transistor 200, conductor 240b is electrically connected to the other of the source and drain of transistor 200, and conductor 240c is connected to the gate of transistor 200.

[0419] The conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper or aluminum. Alternatively, the conductor 240 may be a laminated structure of a first conductor provided along the sidewall and bottom of the opening and a second conductor on the first conductor.

[0420] When a laminated structure is used as the conductor 240, a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen is preferably used as the first conductor arranged near the insulator 280. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. In addition, a single layer or laminated layer of a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen can also be used. By adopting such a structure, impurities such as water and hydrogen contained in the layer above the insulator 283 can be prevented from passing through the conductor 240 and mixing into the oxide 230. In addition, the second conductor is also used as wiring, so it is preferred to use a conductor with high conductivity. For example, as the second conductor, a conductive material with tungsten, copper or aluminum as the main component can be used.

[0421] Notice, Fig.16A The conductor 240 shown has a structure in which a first conductor and a second conductor are stacked, but the present invention is not limited thereto. For example, the conductor 240 may also have a single-layer or three-layer or more stacked-layer structure.

[0422] The insulator 241 is provided in contact with the inner wall of the opening and the side surface of the conductor 240. Fig.16A In the embodiment, each insulator 241 has a structure in which a first insulator is provided in contact with an inner wall of the opening and a second insulator is provided inside the first insulator.

[0423] As the insulator 241, an insulator having a barrier property to one or both of hydrogen and oxygen is preferably used. For example, as the insulator 241, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used. By providing the insulator 241, impurities such as water and hydrogen contained in the insulator 280 can be suppressed from mixing into the oxide 230 through the conductor 240. In particular, silicon nitride is preferred because it has a high hydrogen barrier property.

[0424] Furthermore, by using an oxygen blocking insulator as the insulator 241 , it is possible to suppress absorption of oxygen contained in the insulator 280 by the conductor 240 .

[0425] The insulator 241 has a Fig.16A In the case of a stacked structure as shown, it is preferable to use an oxygen blocking insulator and a hydrogen blocking insulator in combination as a first insulator in contact with the inner wall of the opening formed in the insulator 280 or the like and a second insulator inside the opening.

[0426] For example, aluminum oxide deposited by ALD may be used as the first insulator, and silicon nitride deposited by PEALD may be used as the second insulator. By adopting such a structure, oxidation of the conductor 240 can be suppressed, and entry of hydrogen into the conductor 240 can be suppressed.

[0427] The conductor 246 preferably uses a conductive material mainly composed of tungsten, copper or aluminum. In addition, the conductor may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials. Fig.16A In the embodiment, the conductor 246 is formed in the openings of the insulator 285 and the insulator 286 and contacts a part of the side surface of the insulator 241. However, the present invention is not limited to this, and the following structure may be adopted: the conductor 246 forms an opening in the insulator 286, the top surface of the conductor 240 is exposed in the opening, and the bottom surface of the conductor 246 contacts the top surface of the conductor 240.

[0428] also, Fig.16A Although the structure in which the conductors 240c and 246c are formed in the region overlapping with the oxide 230b is shown similarly to the conductors 240a, 240b, 246a, and 246b, the present invention is not limited thereto. Fig. 16B As shown, a structure may be adopted in which only conductors 240a, 240b, 246a, and 246b are formed in a region overlapping oxide 230b, and conductors 240c and 246c are formed in a region not overlapping oxide 230b.

[0429] Note that regarding the components of the semiconductor device, reference can also be made to the description of [substrate], [insulator], [conductor], and [metal oxide] in Embodiment 1. In addition, each component constituting the semiconductor device may have a single-layer structure or a stacked-layer structure.

[0430] The semiconductor device according to this embodiment includes an OS transistor. The off-state current of the OS transistor is small, so a semiconductor device or a storage device with low power consumption can be realized. In addition, since the frequency characteristics of the OS transistor are high, a semiconductor device or a storage device with a fast operating speed can be realized. In addition, by using the OS transistor, a semiconductor device with good electrical characteristics, a semiconductor device with small uneven electrical characteristics of the transistor, a semiconductor device with large on-state current, and a semiconductor device or a storage device with high reliability can be realized.

[0431] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0432] (Implementation 3) In this embodiment, a memory device according to one embodiment of the present invention is described with reference to the drawings. A memory device according to one embodiment of the present invention is a memory device (hereinafter sometimes referred to as an OS memory device) using a transistor using an oxide for a semiconductor (hereinafter sometimes referred to as an OS transistor).

[0433] <Configuration Example of Storage Device> Fig.17A An example of the structure of an OS storage device is shown. The storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 is a circuit having the function of writing data to the memory cells in the memory cell array 1470 and reading data from the memory cells in the memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0434] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above-mentioned wiring is a wiring connected to the memory cell included in the memory cell array 1470, and its details are described below. The amplified data signal is output as a data signal RDATA to the outside of the memory device 1400 through the output circuit 1440. In addition, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0435] The memory device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. In addition, control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0436] The control logic circuit 1460 processes the control signals (CE, WE, RES) input from the outside to generate control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals can be input as needed.

[0437] The memory cell array 1470 includes a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in one column, etc. In addition, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in one row, etc.

[0438] In addition, although Fig.17A 14 shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited thereto. Fig. 17B As shown in FIG. 1 , the memory cell array 1470 may be provided so as to overlap with a part of the peripheral circuit 1411. For example, a structure in which a sense amplifier is provided so as to overlap under the memory cell array 1470 may be adopted.

[0439] Reference Fig.18A and Fig.18B A structural example of a memory cell that can be suitably used for the above-described memory cell MC will be described.

[0440] Fig.18A A circuit configuration example of a two-transistor gain unit type memory cell is shown. Fig.18A The memory cell 1471 shown includes a transistor M1 and a transistor M2. The transistor M1 and the transistor M2 are single-gate transistors. However, the present invention is not limited to this, and a structure in which a back gate is additionally provided may also be adopted.

[0441] A first terminal of transistor M1 is connected to a gate of transistor M2, a second terminal of transistor M1 is connected to wiring WBL, and a gate of transistor M1 is connected to wiring WOL. A first terminal of transistor M2 is connected to wiring SL, and a second terminal of transistor M2 is connected to wiring RBL.

[0442] The wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring WOL is used as a word line.

[0443] In the memory cell 1471, the gate capacitance of the transistor M2 is used as a storage capacitance. That is, the memory cell 1471 can also be called a capacitor-free memory cell. Therefore, it can be called a gain unit type memory cell with 2 transistors and 0 capacitor elements.

[0444] When an OS transistor is used as the transistor M1, by turning off the transistor M1, the charge of the node electrically connecting one of the source and drain of the transistor M1 and the gate of the transistor M2 can be retained for a long time, thereby realizing a nonvolatile memory cell.

[0445] As Fig.18A The storage unit 1471 shown can be used Figure 1A In this case, the transistor M1 corresponds to the transistor 40, and the transistor M2 corresponds to the transistor 20. In addition, the wiring WBL corresponds to the conductor 44, the wiring RBL corresponds to the conductor 32a, the wiring WOL corresponds to the conductor 50, and the wiring SL corresponds to the conductor 32b.

[0446] Fig.18B Another example of the circuit configuration of a two-transistor gain unit type memory cell is shown. Fig.18B The memory cell 1472 shown includes a transistor M1 and a transistor M2. The transistor M1 and the transistor M2 are single-gate transistors. However, the present invention is not limited thereto, and a structure in which a back gate is additionally provided may also be adopted.

[0447] The first terminal of the transistor M1 is connected to the gate of the transistor M2, the second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The first terminal of the transistor M2 is connected to the wiring SL, and the second terminal of the transistor M2 is connected to the wiring BIL.

[0448] The wiring BIL is used as a bit line, and the wiring WOL is used as a word line.

[0449] Similar to the memory cell 1471, in the memory cell 1472, the gate capacitance of the transistor M2 is used as a storage capacitance. When an OS transistor is used as the transistor M1, by turning off the transistor M1, the charge of the node electrically connected to one of the source and drain of the transistor M1 and the gate of the transistor M2 can be retained for a long time. Therefore, a nonvolatile memory cell can be realized.

[0450] As Fig.18A The storage unit 1472 shown can be used Figure 1A In this case, the transistor M1 corresponds to the transistor 40, and the transistor M2 corresponds to the transistor 20. In addition, the wiring WOL corresponds to the conductor 50, and the wiring SL corresponds to the conductor 32b. The conductor 44 may be used as the wiring BIL. Here, the conductor 24a is electrically connected to the conductor 44 using a through hole or wiring.

[0451] In addition, the memory cell MC is not limited to the memory cell 1471 and the memory cell 1472, and its circuit structure can be changed.

[0452] By using an OS transistor as the transistor M1, the transistor M1 can be formed in the BEOL (Back end of line) process of forming the wiring of the memory device. In addition, when a Si transistor is used in the peripheral circuit 1411 overlapping with the memory cell array 1470, a technology for directly forming an OS transistor above the Si transistor (which is referred to as BEOL-Tr technology) can be used. By using this technology, a 3D functional circuit can be formed while keeping the design rules unchanged, and high functionality can be achieved with low power consumption and low cost.

[0453] Fig.18C is a perspective view of a storage device 1400. The storage device 1400 includes a layer 1480 and a layer 1490. Fig.18D It is a perspective view for explaining the structure of the storage device 1400 , and is a view in which m layers 1490_1 to 1490 — m are stacked.

[0454] Layer 1480 is a layer including a transistor. The semiconductor layer including the channel formation region of the transistor can be formed using one or a combination of semiconductor materials such as a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor or an amorphous semiconductor. As the semiconductor material, for example, silicon or germanium can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors and nitride semiconductors can also be used. In addition, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide or silicon germanium that can be used for HEMT (High Electron Mobility Transistor) can also be used.

[0455] Layer 1490 is a layer including a transistor. The semiconductor layer including the channel formation region of the transistor can be formed using a semiconductor material capable of forming a thin film, such as an oxide semiconductor or silicon. By using BEOL-Tr technology, layer 1490 can be provided on layer 1480. Therefore, a highly integrated memory device 1400 can be realized.

[0456] For example, it is assumed that the transistors included in the layer 1480 are Si transistors. In this case, the peripheral circuit 1411 can be set in the layer 1480. In addition, it is assumed that the transistors included in the layer 1490 are OS transistors. In this case, the memory cell array 1470 can be set in the layer 1490. Here, Figure 5A and Figure 5B The storage device shown is used for Fig.18C The memory device 1400 is shown. In this case, the transistor 60 is formed in the layer 1480, and the memory cell composed of the transistor 20 and the transistor 40 is formed in the layer 1490.

[0457] Furthermore, if Fig.18DAs shown, by stacking m layers 1490_1 to 1490_m, the memory cell array 1470 can have a stacked structure. In this case, the transistor 60 is formed in the layer 1480, and the memory cells composed of the transistor 20 and the transistor 40 are formed in each of the layers 1490_1 to 1490_m.

[0458] Thus, the memory device 1400 can be manufactured using BEOL-Tr technology. Therefore, the occupied area of ​​the memory device 1400 can be reduced.

[0459] (Implementation 4) In this embodiment, an example of a chip on which a memory device according to one embodiment of the present invention is mounted is described with reference to FIG. 19 .

[0460] exist Fig.19A and Fig.19B A plurality of circuits (systems) are mounted on the illustrated chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0461] like Fig.19A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0462] Bumps (not shown) are provided on the chip 1200. Fig.19B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0463] In addition, a storage device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. The storage device described in the above embodiment may be used for these storage devices. Thus, low power consumption and large capacity of the storage device can be achieved.

[0464] CPU1211 preferably has multiple CPU cores. In addition, GPU1212 preferably has multiple GPU cores. In addition, CPU1211 and GPU1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by CPU1211 and GPU1212 may be provided on chip 1200. The above-mentioned DOSRAM may be used for the memory. In addition, GPU1212 is suitable for parallel calculation of multiple data, which may be used for image processing or product-sum calculation. The storage device shown in the above-mentioned embodiment may be used for the memory of GPU1212. Thus, low power consumption and large capacity of the memory of GPU1212 may be achieved.

[0465] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0466] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0467] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0468] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0469] The network circuit 1216 has a circuit for connecting to a network such as a LAN (Local Area Network) and may also have a circuit for network security.

[0470] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0471] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0472] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing a product-sum operation circuit using the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recursive neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0473] This embodiment mode can be combined with other embodiment modes as appropriate.

[0474] (Implementation method 5) In this embodiment, electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DC) that can use the storage device described in the above embodiment are described. Electronic components, electronic devices, large computers, space equipment, and data centers that use the storage device of one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0475] [Electronic components] Fig. 20A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig. 20A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig. 20A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0476] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0477] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0478] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0479] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0480] then, Fig. 20B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0481] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0482] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0483] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit disposed on the interposer 731 to the electrode disposed on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0484] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0485] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0486] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0487] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0488] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 20B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0489] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0490] [Storage device] Alternatively, the storage device described in the above embodiment is applied to various removable storage devices such as a memory card (eg, an SD card), a USB memory, and an SSD (solid state drive). FIG. 21A to FIG. 21E Several structural examples of the removable storage device are schematically shown. For example, the storage device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0491] Fig.21A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a frame 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the frame 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The storage device shown in the above embodiment can be assembled to the memory chip 1105 and the like.

[0492] Fig. 21B This is a schematic diagram of the appearance of an SD card. Fig. 21C 11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a frame 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the frame 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The storage device shown in the above embodiment can be assembled on the memory chip 1114, etc.

[0493] Fig.21D This is a schematic diagram of the appearance of SSD. Fig.21E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a frame 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the frame 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The storage device shown in the above embodiment can be assembled to the memory chip 1154, etc.

[0494] [Electronic equipment] then, Fig.22A A perspective view of electronic device 6500 is shown. Fig.22A The electronic device 6500 shown is a portable information terminal that can be used as a smart phone. The electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The storage device of one embodiment of the present invention can be used for the control device 6509, etc.

[0495] Fig. 22BThe electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a frame 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A storage device of one embodiment of the present invention can be used for the control device 6616, etc. In addition, by using a storage device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0496] [Mainframe computer] then, Fig. 22C A perspective view of a mainframe computer 5600 is shown. Fig. 22C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0497] Computer 5620 may have, for example, Fig.22D The structure of the stereogram is shown. Fig.22D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0498] Fig.22E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.22E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0499] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0500] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0501] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0502] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0503] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0504] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0505] [Space Equipment] The storage device of one embodiment of the present invention can be applied to space equipment such as equipment that processes and stores information.

[0506] A storage device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0507] exist Fig.23 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.23 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0508] In addition, although Fig.23 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0509] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0510] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0511] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0512] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, it is preferable to use a storage device of one embodiment of the present invention. Compared with Si transistors, the electrical characteristics of OS transistors change less due to irradiation with radiation. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0513] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0514] Note that in this embodiment, an artificial satellite is described as an example of a space device, but the present invention is not limited to this. For example, a storage device according to one embodiment of the present invention can be appropriately applied to space devices such as a spacecraft, a space capsule, and a space probe.

[0515] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0516] [Data Center] For example, a storage device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing long-term data, it is necessary to enlarge facilities, such as installing a storage device and a server for storing a large amount of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0517] By using a storage device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the storage device for data retention. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for data retention, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0518] In addition, the storage device of one embodiment of the present invention consumes less power, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the storage device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0519] Fig.24 A storage system that may be used in a data center is shown. Fig.24 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as a memory 7003 (shown as a memory). The host 7001 and the memory 7003 are shown to be connected via a storage area network 7004 (shown as a SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0520] The host 7001 is equivalent to a computer that accesses data stored in the memory 7003. The hosts 7001 may be connected to each other via a network.

[0521] In the memory 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a high-speed cache memory in the memory. In the storage system, in order to solve the problem of the high access speed of the memory 7003, a high-speed cache memory is generally provided in the memory to shorten the time required for data storage and output.

[0522] The cache memory described above is used in the storage control circuit 7002 and the memory 7003. Data exchanged between the host 7001 and the memory 7003 is stored in the cache memory in the storage control circuit 7002 and the memory 7003 and then output to the host 7001 or the memory 7003.

[0523] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0524] Note that by using a storage device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a storage device of one embodiment of the present invention. In addition, the storage device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0525] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode as appropriate. [Explanation of symbols]

[0526] BIL: wiring, MC: memory cell, RBL: wiring, SL: wiring, WBL: wiring, WOL: wiring, 20: transistor, 22: oxide semiconductor, 24a: conductor, 24b: conductor, 24: conductor, 26: conductor, 28: insulator, 30a: conductor, 30b: conductor, 30c: conductor, 32a: conductor, 32b: conductor, 32c: conductor, 34: insulator, 36: insulator, 38: insulator, 40: transistor, 42a: oxide semiconductor, 42b: oxide semiconductor, 42: oxide semiconductor, 44: conductor, 46a: conductor, 46b: conductor, 46: conductor, 48a: insulator, 48b: insulator , 48c: insulator, 48d: insulator, 48: insulator, 50: conductor, 52a: insulator, 52b: insulator, 52c: insulator, 52: insulator, 54: insulator, 56: insulator, 57: insulator, 58: insulator, 59: insulator, 60: transistor, 62: substrate, 63: semiconductor region, 64a: low resistance region, 64b: low resistance region, 66: conductor, 68: insulator, 70a: conductor, 70b: conductor, 70c: conductor, 70: conductor, 72a: conductor, 72b: conductor, 72c: conductor, 72: conductor, 73: insulator, 74: insulator, 76: insulator, 78: insulator, 200: crystal tube, 205a: conductor, 205b: conductor, 205: conductor, 215: insulator, 216: insulator, 221: insulator, 222: insulator, 224: insulator, 230a: oxide, 230b: oxide, 230c: oxide, 230: oxide, 240a: conductor, 240b: conductor, 240c: conductor, 240: conductor, 241a: insulator, 241b: insulator, 241c: insulator, 241: insulator, 242a: conductor, 242b: conductor, 246a: conductor, 246b: conductor, 246c: conductor, 246: conductor, 250a: insulator, 250b: insulator, 250c: insulator, 250d: insulator, 250: insulator, 255a: insulator, 255b: insulator, 255: insulator, 260a: conductor, 260b: conductor, 260: conductor, 271a: insulator, 271b: insulator, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 285: insulator, 286: insulator, 700: electronic component, 702: printed circuit board, 704: circuit board, 710: semiconductor device, 711: mold, 712: connection pad, 713: electrode pad, 714: lead, 715: drive circuit layer, 716: storage layer, 730: electronic component, 731: plug board, 732: packaging substrate,733: electrode, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cover, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201 : Package substrate, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog operation unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 1400: Storage device, 1411: Peripheral circuit, 1420: Row circuit, 1430: Column circuit, 1440: Output circuit, 1460: Control logic circuit, 1470: Memory cell array, 1471: Memory cell, 1472: Memory cell, 1480: Layer, 1490_1: Layer, 1490 _m: layer, 1490: layer, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: personal computer card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: frame, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 65 08: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: main body, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001sb: server, 7001: host, 7002: storage control circuit, 7003md: storage device, 7003: memory, 7004: storage area network,

Claims

1. A storage device, comprising: a first transistor; as well as a second transistor on the first transistor, Wherein, the first transistor comprises: a first oxide semiconductor; A first conductor and a second conductor separated from each other on the first oxide semiconductor; a first insulator disposed on the first conductor and the second conductor and including an opening between the first conductor and the second conductor; a second insulator disposed in the opening of the first insulator and disposed on the first oxide semiconductor; and a third conductor disposed in the opening of the first insulator and disposed on the second insulator, The second transistor comprises: a third insulator disposed on the first insulator and the third conductor and including an opening overlapping the first oxide semiconductor; a fourth conductor disposed on the third insulator and including an opening overlapping with the opening of the third insulator; a second oxide semiconductor disposed in the openings of the third insulator and the fourth conductor; a fourth insulator disposed on the second oxide semiconductor in the openings of the third insulator and the fourth conductor; and a fifth conductor disposed on the fourth insulator in the openings of the third insulator and the fourth conductor, Furthermore, the second oxide semiconductor passes through the third insulator and is electrically connected to the third conductor.

2. The storage device according to claim 1, wherein a sixth conductor is arranged under the second oxide semiconductor, The opening of the third insulator reaches the sixth conductor, And the sixth conductor is in contact with a portion of the second oxide semiconductor and is electrically connected to the third conductor.

3. The storage device according to claim 2, wherein the fourth conductor is used as one of a source electrode and a drain electrode of the second transistor, The fifth conductor is used as a gate electrode of the second transistor. And the sixth conductor is used as the other of the source electrode and the drain electrode of the second transistor.

4. The storage device according to claim 1, The channel length of the second transistor is at least smaller than the channel width of the second transistor.

5. The storage device according to claim 1, further comprising: The seventh conductor, wherein the fourth conductor extends in the first direction, The seventh conductor extends in the second direction, And the first direction and the second direction intersect each other.

6. The storage device according to claim 2, Another portion of the second oxide semiconductor, a portion of the fourth insulator, and a portion of the fifth conductor are located on the fourth conductor.

7. The storage device according to claim 6, Another portion of the second oxide semiconductor is in contact with the top surface of the fourth conductor.

8. The storage device according to claim 6, A portion of the fourth insulator covers another portion of the second oxide semiconductor.

9. The storage device according to claim 1, The openings of the third insulator and the fourth conductor have a circular shape or a substantially circular shape when viewed from a plane.

10. The storage device according to any one of claims 1 to 9, The second oxide semiconductor includes any one or more selected from In, Ga and Zn.

11. The storage device according to claim 10, wherein the third insulator has a laminated structure, The stacked structure includes a first layer, a second layer on the first layer, and a third layer on the second layer, The first layer comprises silicon and nitrogen, The second layer comprises silicon and oxygen, And the third layer includes silicon and nitrogen.

12. The storage device according to claim 10, The first oxide semiconductor includes any one or more selected from In, Ga and Zn.

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