Integrated method for improving mobility and conduction current in 3D NAND cells

Abstract

Embodiments of the present disclosure provided herein include apparatuses and methods for forming improved three-dimensional (3D) memory structures / cells that include channels including polysilicon channels, and methods of forming improved three-dimensional (3D) memory structures / cells that include polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, polysilicon channels, and polysilicon channels. The polysilicon channel has been processed to passivate and remove defects found in the channel structure of a 3D memory device, such as a 3D NAND device. In some embodiments, the process performed on the channel structure utilizes deposition of a fluorine-containing layer comprising a concentration of fluorine (F) atoms, which are then driven into the polysilicon channel layer using at least one annealing step, the at least one annealing step is performed in an environment containing hydrogen or deuterium to load the polysilicon layer with fluorine (F) atoms and hydrogen (H) atoms.

Description

background Technical Field

[0002] The present disclosure relates generally to memory devices and methods of making the same, and more particularly to device structures and methods of forming three-dimensional (3D) memory devices. Background Art

[0003] Memory devices are essential components in today's digital electronic devices. With today's advancement in technology, there is a need for increased memory capacity in most electronic devices. At the same time, there is also a need for smaller memory devices to meet the market's desire to create smaller electronic devices, where the memory devices are located within the smaller electronic devices.

[0004] In recent years, conventional (2D) NAND memory devices have encountered several challenges, including voltage drop related issues (e.g., electron depletion in current carrying elements due to continued reduction in cell size), retention loss, and overall reliability. In order to address these challenges encountered in scaling planar (2D) NAND memory devices to achieve higher density at lower cost per bit, ultra-high density three-dimensional (3D) stacked memory structures have been proposed. Such 3D memory structures are sometimes referred to as having a Bit Cost Scalable (BiCS) architecture and include a series of vertically integrated memory cells. Typically, the vertically aligned memory cells are formed by an array of alternating conductor and insulator layers, where the conductive layers correspond to the word lines of the memory structure.

[0005] As the number of vertically stacked memory cells in a 3D NAND device increases (e.g., chip density increases), the resistance of the memory cell string (e.g., channel structure) also increases, causing many performance issues. Due to the increase in resistance, more advanced circuits are required for current sensing. Typically, a memory cell string may include several word line layers. As the number of vertically stacked layers increases, the overall resistance of the vertically oriented channel structure of a 3D NAND memory increases, causing a decrease in the amount of current that can (1) flow in the channel structure and most importantly (2) be detected by a sense amplifier. Based on current design rules and pitch, at approximately 500 stacked word line layers, it may be impossible to detect any current flowing through the channel structure, which corresponds to a storage state. As a result, the difference between storage states will be indistinguishable. Currently, polysilicon channels are typically utilized in the channel structure of a 3D NAND device. Due to the use of polysilicon channels and the highly granular nature of polysilicon channels, 3D NAND devices can suffer from reduced mobility, on-current degradation, increased device variability, and retention degradation. In the past, macaroni-type 3D NAND devices were proposed and implemented to include filler oxides, which minimize the thickness of the polysilicon channel and thus reduce the number of grain boundaries (GBs), which are responsible for electron scattering, and improve on-current. Although the number of GBs in this approach is reduced, they still exist and cannot overcome the 500 WL stacking limitation.

[0006] Therefore, there exists a need for an improved memory device structure and a method of forming the improved memory device structure that solves the above-mentioned problems. Summary of the invention

[0007] Embodiments of the present disclosure may include a three-dimensional memory device, comprising: a plurality of alternating layers formed above a surface of a substrate, wherein the alternating layers include word line layers and inter-word line dielectric layers stacked in a first direction; a gate coupled to each of the word line layers of the plurality of alternating layers; a polysilicon channel layer having a first end, a second end and extending between a source region and a drain region in the first direction, the first end coupled to the source region, and the second end coupled to the drain region; and an ONO layer stack disposed between the gate and the polysilicon layer, wherein the ONO layer stack extends between the source region and the drain region in the first direction. The polysilicon channel layer may include a polysilicon layer, wherein the polysilicon layer includes a fluorine (F) concentration of >1×10 14 Atom / cm 3 , and >1×10 14 Atom / cm 3 The hydrogen (H) concentration.

[0008] Embodiments of the present disclosure may further include a method of forming a three-dimensional memory device, comprising: forming a channel structure within a plurality of openings formed through a plurality of alternating layers, the plurality of alternating layers being formed above a surface of a substrate, comprising: forming an ONO layer stack above a surface of each of the plurality of openings; and forming a polysilicon layer above a surface of the ONO layer stack; forming a fluorine-containing layer on the formed polysilicon layer; annealing the substrate, wherein annealing the substrate causes fluorine atoms originally disposed in the fluorine-containing layer to diffuse into the polysilicon layer; and selectively removing the fluorine-containing layer; annealing the substrate in a hydrogen-containing environment to cause hydrogen atoms from the hydrogen-containing environment to diffuse into the polysilicon layer; and forming a drain region layer above the plurality of alternating layers, wherein at least a portion of the formed channel structure is coupled to a portion of the drain region layer and to a portion of a source region layer of the three-dimensional memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more particular description of the present disclosure briefly outlined above may be obtained by referring to the embodiments, in which way the above-mentioned features of the present disclosure may be understood in detail, some of which are illustrated in the accompanying drawings. It will be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the present disclosure, and other equally effective embodiments may be allowed.

[0010] Figure 1 is a simplified diagrammatic example of a three-dimensional (3D) NAND memory structure 100 .

[0011] Figure 2 Illustrated is a method 200 of forming a channel structure within a 3D NAND memory structure according to one or more embodiments described herein.

[0012] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G ,and Figure 3H is a diagrammatic side cross-sectional view of a portion 301 of a 3D NAND memory structure used to illustrate activities performed in method 200 in accordance with one or more implementations described herein.

[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0014] In the following description, details are described by way of example to facilitate understanding of the disclosed subject matter. However, it should be apparent to those skilled in the art that the disclosed embodiments are exemplary and not exhaustive of all possible embodiments. Therefore, it should be understood that reference to the illustrated examples is not intended to limit the scope of the present disclosure. It is fully contemplated that any changes and further modifications to the described devices, instruments, methods, and any further applications of the principles of the present invention are what the technical personnel of the relevant fields involved in the present disclosure would normally think of. In particular, it is fully contemplated that the features, components, and / or steps described with respect to one embodiment may be combined with the features, components, and / or steps described with respect to other embodiments of the present disclosure. When used herein, the term "approximately" may refer to a variation of + / -10% from a nominal value. It will be understood that such a variation may be included in any numerical value provided herein.

[0015] Embodiments of the present disclosure provided herein include apparatus for forming an improved three-dimensional (3D) memory structure / cell and a method for forming an improved three-dimensional (3D) memory structure / cell, the three-dimensional (3D) memory structure / cell including a multi-layer channel, the multi-layer channel including a polysilicon channel, the polysilicon channel having been processed to passivate and remove defects found in the channel structure of a 3D memory device (such as a 3D NAND device). In some embodiments, the processing performed on the channel structure utilizes the deposition of fluorine-containing amorphous silicon (aSi), the fluorine-containing amorphous silicon (aSi) including a concentration of fluorine (F) atoms, and then driving the fluorine (F) atoms into the polysilicon channel layer using at least one annealing step, the annealing step being carried out in a hydrogen-containing (H 2 ) or deuterium (D 2 ) environment so that the polysilicon layer is loaded with fluorine (F) and hydrogen (H) atoms. By using the modified polysilicon layer during operation, it has been found that the modified polysilicon channel described herein provides a higher "on" current. It is believed that the process of modifying the polysilicon layer will reduce defects and electron scattering centers, which will increase the electron mobility in the channel layer, which will help increase the speed and reliability of 3D NAND devices because a larger amount of current can be conducted through the channel structure of the device. Due to the modification of the polysilicon channel, the channel structure and the entire memory string exhibit reduced resistance and variability. Therefore, the modified polysilicon channel in the channel structure can achieve a larger number of word lines (e.g., more than 500 word lines) in the 3D memory structure.

[0016] Embodiments disclosed herein may be beneficial for, but not limited to, channel structures in two-dimensional (2D) and 3D memories.

[0017] 3D NAND Memory Device Structure

[0018] Figure 1 1 is a simplified diagrammatic example of a 3D NAND memory structure 100. The 3D NAND memory structure includes a channel structure 117 positioned in a vertical direction such that the channel structure 117 is positioned perpendicular (e.g., in the Z-direction) to a major surface of a substrate 101, the substrate 101 including an etch stop layer (ESL) 102 and a common source line layer (CSL) 103 disposed on the substrate 101. The top of the vertical channel layer structure 117 includes a plurality of bit lines 118. The stacked layers are configured into stacked layer pairs 120, each of which includes a dielectric layer 116 and a word line layer 115. In this configuration, the word line layer 115 (e.g., in Figure 1 100) are stacked in a direction perpendicular to the main surface of the substrate to form a string of memory cells and the word line layers 115 each include a portion of one of the channel layer structures 117. At one end of each word line layer 115 is a stepped structure 110. In the stepped structure 110, one or more conductive columns 114 are used to connect the word line layer 115 to an external control circuit by using a connecting element line 113. In this way, in a 3D NAND memory structure, the memory cells can be manufactured in a vertical direction so that the memory capacity can be easily increased by stacking additional layers. The gate slit line 119 can also be formed to pass through the 3D NAND memory structure 100. It should be noted that in some embodiments, the word line layer 115 is deposited later in the process of forming a 3D NAND device by removing a dummy (second) dielectric material (e.g., a dummy nitride material) using an etching process, and then depositing a conductive layer at the same location where the dummy (second) dielectric material was located.

[0019] The 3D NAND memory structure 100 may also include a source region 126 (e.g., an N+ source layer), which may be part of or formed on the CSL 103, and a drain region 128 (e.g., an N+ drain layer), which may be part of or formed under the plurality of bit lines 118. The stair-like structure 110 formed on two opposite edges of the 3D NAND memory structure 100 requires a two-dimensional area (i.e., an XZ plane) to connect all the word line layers 115 to external elements outside the 3D NAND device.

[0020] Channel Formation Process Example

[0021] Figure 2 A method 200 is illustrated for use in the fabrication of a 3D memory cell, such as forming a portion 301 of a 3D NAND memory structure 300, in accordance with one or more embodiments described herein. Figure 3A , Figure 3B , Figure 3C , Figure 3D, Figure 3E , Figure 3F , Figure 3G ,and Figure 3H An illustration of a method of performing a Figure 2 3D NAND memory structure 300 during one or more activities. Figure 2 and Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G ,and Figure 3H They are described together in this article for clarity.

[0022] The method 200 begins with a mold deposition process at activity 202, where a plurality of alternating layers 125 are formed over a surface of a substrate 101. In some embodiments, forming the plurality of alternating layers 125 may include forming a plurality of dummy nitride layers 302 and a plurality of inter-wordline dielectric layers 116, the plurality of dummy nitride layers 302 and the plurality of inter-wordline dielectric layers 116 being sequentially stacked in a first direction (perpendicular to a major surface of the substrate 101, e.g., a Z-direction) over a common source line layer (CSL) 103 disposed over the surface of the substrate 101. Figure 3A A portion 301 of a 3D NAND memory structure 300 is illustrated in FIG.

[0023] At activity 204, a memory hole etching process is performed in which a plurality of openings 310 (eg, memory holes) extending from the CSL 103 and through the plurality of alternating layers 125 in a first direction are etched, such as Figure 3B As shown in . A high aspect ratio etching process may be used to etch the memory hole 310. In addition, the memory hole 310 extends from the CSL 103 through the plurality of alternating layers 125 in a first direction.

[0024] At activity 206, a memory hole channel layer deposition process is performed, wherein a channel structure 117 is formed within the memory hole 310. The process of forming the channel structure 117 includes depositing an oxide-nitride-oxide (ONO) layer stack 312 over a surface of each of the memory holes 310 in the portion 301 of the 3D NAND memory structure 100 by using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process, such as Figure 3C. Depositing the ONO layer stack 312 includes forming a first dielectric layer (e.g., a first oxide layer 322) over the surface of each of the memory holes 310 through the plurality of alternating layers 125 of the dummy nitride layer 302 and the dielectric layer 116. The process of depositing the first oxide layer 322 may include, for example, depositing aluminum oxide (Al2O3) on the inner surface of each of the memory holes 310 (e.g., on the sides of the plurality of openings formed in the plurality of alternating layers 125 and at the bottom of the memory holes 310) along the CSL 103 and / or the ESL 102. 2 O 3 or the like) and or silicon oxide (SiO x ) layer (e.g., a continuous layer). The first oxide layer 322 forms a so-called blocking oxide and high-k layer of the memory cell. The process of depositing the ONO layer stack 312 also includes depositing a silicon nitride layer (e.g., a charge trapping layer 323) on the first oxide layer 322 by using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process, such as Figure 3C As shown in FIG. 3 , the charge trapping layer 323 may include a capture silicon nitride (Si 3 N 4 ) layer, or even a polycrystalline silicon (poly-Si) layer (floating gate NAND cell architecture). The process of depositing the ONO layer stack 312 also includes forming a second dielectric layer (e.g., a second oxide layer 324) on the charge trapping layer 323 by using an atomic layer deposition (ALD), a plasma enhanced ALD (PEALD), a chemical vapor deposition (CVD), or a plasma enhanced chemical vapor deposition (PECVD) process, such as Figure 3C The second oxide layer 324 may include silicon oxide (SiO x ) layer or SiO 2 / SiN / SiO 2 The second oxide layer 324 or the combination of bandgap engineered layers can be used to form a tunnel oxide region of the device. The first oxide layer 322, the charge trapping layer 323, and the second oxide layer 324 together form a simplified ONO layer stack 312. The process of forming the channel structure 117 also includes depositing a channel layer 314 in the plurality of openings 310 on the second dielectric layer (e.g., the second oxide layer 324) using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process, such as Figure 3C As shown in . For example, the channel layer 314 may be a polysilicon layer.

[0025] At activity 208, a fluorine-containing layer deposition process is performed, wherein a fluorine-containing (F) layer 316 is formed over the deposited channel layer 314 within the memory hole 310. The process of forming the fluorine-containing (F) layer 316 includes depositing the fluorine-containing (F) layer 316 over the surface of each of the memory holes 310 of the 3D NAND memory structure 100 by using an atomic layer deposition (ALD), a plasma enhanced ALD (PEALD), a chemical vapor deposition (CVD), or a plasma enhanced chemical vapor deposition (PECVD) process, such as Figure 3D In some embodiments, depositing the fluorine (F)-containing layer 316 includes forming an amorphous silicon layer including a fluorine (F) concentration of about 5 at.% on the sidewalls of the channel layer 314, the channel layer 314 being disposed on the ONO layer stack 312, the ONO layer stack 312 being on the plurality of alternating layers 125 of the dummy nitride layer 302 and the dielectric layer 116.

[0026] At activity 210, if Figure 3E As shown in FIG. 1 , a first annealing process is performed on the 3D NAND memory structure 100 so that the mobile fluorine (F) atoms in the fluorine (F)-containing layer 316 diffuse into the channel layer 314 and passivate the defects in the polysilicon material in the channel layer 314. The first annealing process may be a spike annealing or other similar process capable of driving fluorine (F) atoms into the channel layer 314. Typically, the concentration of fluorine atoms in the channel layer 314 after the first annealing process is performed will be greater than 1×10 14 / cm 3 , or even greater than 1×10 15 / cm 3 In one embodiment, the first annealing process includes 2 ) or deuterium (D 2 ) environment (e.g., 5ATM).

[0027] At activity 212, an etching process is performed to selectively remove the fluorine (F) containing layer 316, such as Figure 3F The etching process may be performed using a selective removal plasma (SRP) etching process available from Applied Materials, Inc. in Santa Clara, California.

[0028] At operation 214, an optional second annealing process is performed. The second annealing process may include performing an annealing process in a hydrogen or deuterium containing environment so that after the etching process is performed in activity 212, the surface of the channel layer 314 is exposed to a hydrogen containing gas to help drive hydrogen atoms into the channel layer 314 to further passivate defects found in the channel layer 314. The annealing process may include a high pressure annealing process (e.g., ~5 ATM), a spike annealing process, or other similar processes capable of driving hydrogen (H) atoms into the channel layer 314. Typically, the concentration of hydrogen atoms in the channel layer 314 after performing the second annealing process will be greater than 1×10 14 Atom / cm 3 , or even greater than 1×10 15 Atom / cm 3 .

[0029] At activity 216, in some embodiments, a memory hole filling process is performed, wherein a filler layer 318 is deposited in each of the memory holes 310 in a portion of the 3D NAND memory structure 100 on the channel layer 314. For example, the filler layer 318 may be made of silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), or silicon nitride (Si 3 N 4 ) is formed. In some embodiments, the deposition of the filler layer 318 can fill the remaining portion of the memory hole 310 in the 3D NAND memory structure 100. The filler layer 318, such as an oxide layer, can be deposited using any suitable deposition process and / or equipment. For example, physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD) processes can be used to deposit the channel layer 314 and the second channel layer, the ONO layer stack 312, and the filler layer 318. Alternatively or additionally, a single device or a cluster tool can be used to perform the atomic layer deposition (ALD) process. Example equipment that can be configured to perform the above process includes, for example, an ALD device of the OLYMPIA series available from Applied Materials.

[0030] At activity 218, a mold pull-back process is performed to remove the dummy nitride layer 302, such as Figure 3H Subsequently, a word line layer 115 (shown in Figure 1 ) to replace the removed dummy nitride layer 302. In some subsequent steps, the drain region 128 (shown in Figure 1) is formed over the plurality of alternating layers 125. In some embodiments, at least a portion of the channel structure 117 formed in each of the memory holes 310 is coupled to a portion of the drain region 128 and a portion of the CSL 103. In some embodiments, the plurality of bit lines 118 (shown in Figure 1 The channel layer 314 and the filler layer 318 may be deposited on the top of the memory hole 310 in the 3D NAND memory structure 100. Due to the deposition of the plurality of bit lines 118, the channel layer 314 and the filler layer 318 may contact the drain region 128 (eg, N+ drain layer).

[0031] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which is to be determined by the claims which follow.

Claims

1. A three-dimensional memory device, comprising: a plurality of alternating layers formed above a surface of a substrate, wherein the alternating layers include word line layers and inter-word line dielectric layers, the word line layers and the inter-word line dielectric layers are stacked in a first direction; an ONO layer stack disposed over a surface of each of a plurality of memory holes formed through the plurality of alternating layers, wherein the ONO layer stack extends in the first direction; and a channel layer disposed above the ONO layer stack, the channel layer having a first end coupled to the source region, a second end coupled to the drain region, and extending through the plurality of alternating layers, The channel layer contains more than 1×10 14 Atom / cm 3 The fluorine (F) concentration is greater than 1×10 14 Atom / cm 3 The hydrogen (H) concentration.

2. The three-dimensional memory device of claim 1, wherein the channel layer comprises polysilicon.

3. The three-dimensional memory device of claim 1, wherein the channel layer further comprises a fluorine (F) concentration of >1×10 15 Atom / cm 3 , and >1×10 15 Atom / cm 3 The hydrogen (H) concentration.

4. The three-dimensional memory device of claim 1 , wherein the ONO stack comprises a first oxide layer, a charge trapping layer, and a second oxide layer, the first oxide layer being over a surface of each of the plurality of memory holes passing through the plurality of alternating layers, the charge trapping layer being on the first oxide layer, and the second oxide layer being on the charge trapping layer.

5. The three-dimensional memory device of claim 4, wherein the charge trapping layer comprises silicon nitride (Si3N4) or polycrystalline silicon (poly-Si).

6. A method of forming a three-dimensional memory device, comprising the steps of: Forming a channel structure in a plurality of openings formed through a plurality of alternating layers formed above a surface of a substrate, the forming step comprising the steps of: forming an ONO layer stack over a surface of each of the plurality of openings; and forming a polysilicon layer over a surface of the ONO layer stack; forming a fluorine-containing layer on the formed polysilicon layer; annealing the substrate, wherein annealing the substrate causes fluorine atoms originally disposed in the fluorine-containing layer to diffuse into the polysilicon layer; selectively removing the fluorine-containing layer; and annealing the substrate in a hydrogen-containing environment, wherein annealing the substrate causes hydrogen atoms from the hydrogen-containing environment to diffuse into the polysilicon layer; and A drain region layer is formed over the plurality of alternating layers, wherein at least a portion of the formed channel structure is coupled to a portion of the drain region layer and to a portion of a source region layer of the three-dimensional memory device. 7 . The method of claim 6 , wherein the step of forming the channel structure further comprises the step of forming a filler layer over the surface of the polysilicon layer after selectively removing the fluorine-containing layer.

8. The method of claim 7, wherein the plurality of alternating layers comprises: a word line layer and an inter-word line dielectric layer, the word line layer and the inter-word line dielectric layer are stacked above the source region layer in a first direction, the source region layer is disposed above the surface of the substrate; and The plurality of openings extend from the source region layer and through the plurality of alternating layers in the first direction.

9. The method of claim 8, wherein the step of annealing the substrate comprises a high pressure annealing process.

10. The method of claim 7, wherein fluorine and hydrogen passivate grain boundaries and interface traps in the polysilicon layer.

11. A method for forming a channel structure of a three-dimensional memory device, comprising the following steps: performing a mold deposition process to form a plurality of alternating layers of dummy nitride layers and inter-wordline dielectric layers over a surface of the substrate; performing a memory hole etching process to etch a plurality of memory holes through the plurality of alternating layers; performing a memory hole channel layer deposition process to form a channel structure within each of the plurality of memory holes, the memory hole channel layer deposition process comprising: depositing an oxide-nitride-oxide (ONO) layer stack over a surface of each of the memory holes, the ONO layer stack comprising a first oxide layer on an inner surface of each of the plurality of memory holes, a charge trapping layer on the first oxide layer, and a second oxide layer on the charge trapping layer; and depositing a channel layer on the second oxide layer; performing a fluorine-containing layer deposition process to form a fluorine (F)-containing layer over the channel layer; performing a first annealing process to diffuse migrating fluorine (F) atoms in the fluorine (F)-containing layer; and An etching process is performed to selectively remove the fluorine (F) containing layer.

12. The method of claim 11, wherein the channel layer comprises polysilicon.

13. The method of claim 11, wherein The fluorine-containing layer deposition process includes forming a fluorine (F)-containing amorphous silicon layer on the channel layer.

14. The method of claim 11, wherein The first annealing process includes a spike annealing process, and After the first annealing process, the concentration of fluorine atoms in the channel layer is greater than 1×10 14 / cm 3 .

15. The method of claim 11, further comprising the steps of: After the etching process, a second annealing process is performed to drive hydrogen atoms from an environment containing hydrogen or deuterium to diffuse into the channel layer.

16. The method of claim 15, wherein The second annealing process includes a spike annealing process, and After the second annealing process, the concentration of hydrogen atoms in the channel layer is greater than 1×10 14 / cm 3 .

17. The method of claim 11, further comprising the steps of: After the etching process, a memory hole filling process is performed to deposit a filler layer in each of the plurality of memory holes.

18. The method of claim 17, wherein the filler layer comprises silicon dioxide (SiO2), aluminum oxide (Al2O3), or silicon nitride (Si3N4).

19. The method of claim 17, further comprising the steps of: After the memory hole filling process, a mold pull-back process is performed to remove the dummy nitride layers of the plurality of alternating layers and deposit a word line layer.

20. The method of claim 19, further comprising the steps of: A drain region layer is formed over the plurality of alternating layers, wherein at least a portion of the formed channel structure is coupled to a portion of the drain region layer and to a portion of a source region layer of the three-dimensional memory device.

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