Laser Raman patterned TMDs, preparation thereof and application of laser Raman patterned TMDs in p-type TMDs field effect transistor

Abstract

The invention belongs to the field of two-dimensional field effect transistors, and particularly relates to laser Raman patterned TMDs, preparation of the laser Raman patterned TMDs and application of the laser Raman patterned TMDs in the field effect transistors, and the preparation method comprises the step that laser Raman scanning is conducted on a TMDs two-dimensional material through a laser confocal micro Raman spectrometer to achieve patterning processing, in the laser Raman scanning stage, the laser wavelength is 355-633 nm, and the power is 40-60 mw; the scanning mode is a line focusing scanning mode; and the value of a Raman peak in a scanning mode is 1-1000 cm <-1 >. According to the invention, patterning processing is carried out on the TMDs two-dimensional material based on a laser Raman scanning means, and combined control of parameters such as a scanning mode and conditions is further matched, so that synergy can be realized, nearly lossless patterning of the TMDs can be realized, and patterning and a subsequent field effect transistor preparation process are simplified; and the performance loss of the field effect transistor can be reduced, and the relatively stable performance can be maintained even when devices with different channels are prepared.

Description

Technical Field

[0001] The invention belongs to the field of nano-processing, and relates to the field of preparation technology for p-type field effect transistors. Technical Background

[0002] To realize the practical applications of two-dimensional (2D) materials, advanced processing and manufacturing strategies for various devices and integrated circuits must be developed. 1 Nanofabrication processes, including nanopatterning, play a key role in connecting the microstructures of 2D materials and integrating electronic and optoelectronic chips, which inevitably requires extensive research and exploration. Traditional manufacturing processes for device processing mainly include lithography (such as UV lithography, EBL) and etching (such as plasma etching, reactive ion etching), etc. However, due to the highly sensitive surface and interface properties of 2D materials, the intrinsic electrical properties of 2D p-type or n-type semiconductors are easily changed during device processing. 2-6 For example, high-energy electron beam irradiation of the channel region can lead to n-type doping and even damage the delicate atomic structure.

[0003] In addition to conventional microfabrication processes, various direct-write patterning techniques have been developed for 2D materials, including tip-induced oxidation, thermal decomposition, and mechanical scratching. These techniques can pattern single-layer 2D materials without using sacrificial resistors. However, achieving clean patterning of 2D semiconductors while maintaining their intrinsic electrical properties remains a major challenge.

[0004] (1)Zhang,X.; Zhao,H.; Wei,X.; Zhang,Y.; Zhang,Z.; Zhang,Y.;

[0005] (2)Stanford,MG;Lin,Y.-C.;Sales,MG;Hoffman,AN;Nelson,CT;Xiao,K.;McDonnell,S.;Rack,PD;

[0006] (3) Tang, B.; Yu, Z. G.; Huang, L.; Chai, J.; Wong, S. L.; Deng, J.; Yang, W.; Gong, H.; Wang, S.; Ang, K.-W.; et al.; Direct n-to p-type channel conversion in monolayer / few-layer WS2 field-effect transistors by atomic nitrogen treatment. ACS Nano 2018, 12, 2506 - 2513.

[0007] (4) Chen, M.; Nam, H.; Wi, S.; Ji, L.; Ren, X.; Bian, L.; Lu, S.; Liang, X.; Stable few-layer MoS2 rectifying diodes formed by plasma-assisted doping. Appl. Phys. Lett. 2013, 103, 142110.

[0008] (5) Liu, Y.; Tan, C.; Chou, H.; Nayak, A.; Wu, D.; Ghosh, R.; Chang, H.-Y.; Hao, Y.; Wang, X.; Kim, J.-S.; et al.; Thermal oxidation of WSe2 nanosheets adhered on SiO2 / Si substrates. Nano Lett. 2015, 15, 4979 - 4984.

[0009] (6) Suk, J. W.; Lee, W. H.; Lee, J.; Chou, H.; Piner, R. D.; Hao, Y.; Akinwande, D.; Ruoff, R. S.; Enhancement of the electrical properties of graphene grown by chemical vapor deposition via controlling the effects of polymer residue. Nano Lett. 2013, 13, 1462 - 1467. Summary of the Invention

[0010] In view of the problem that the existing method for preparing patterned TMDs is prone to damage the performance of its field effect transistor, the first purpose of the present invention is to provide a method for preparing laser Raman patterned TMDs, aiming to achieve lossless patterning of TMDs based on a new laser Raman method, thereby improving its performance and stability in p-type field effect transistors.

[0011] The second object of the present invention is to provide laser Raman patterned TMDs prepared by the preparation method and their application in the preparation of p-type field effect transistors.

[0012] The third object of the present invention is to provide a p-type field effect transistor prepared by laser Raman patterning TMDs as described in the present invention and a preparation method thereof.

[0013] For the preparation of TMDs two-dimensional material field effect transistors, the existing main means is to use electron beam irradiation, ultraviolet lithography, laser-thermal etching and other methods to pattern the two-dimensional materials. Such methods are complex in process and operation, and are also prone to damage the performance of field effect transistors. Moreover, as the device channel shrinks, this performance damage will be particularly obvious. To address this problem, the present invention provides a nearly lossless patterning process, specifically:

[0014] A method for preparing laser Raman patterned TMDs, wherein a laser confocal micro-Raman spectrometer is used to perform laser Raman scanning on TMDs two-dimensional materials to achieve patterning, wherein the laser wavelength in the laser Raman scanning stage is 355-633nm, the power is 40-60mw; the scanning mode is a line focus scanning mode; the value of the Raman peak in the scanning mode is 1-1000cm -1 .

[0015] The present invention performs patterning processing on TMDs two-dimensional materials based on laser Raman scanning, and further cooperates with the joint control of parameters such as scanning mode and conditions, so as to achieve synergy and realize nearly lossless patterning of TMDs, simplify the patterning and subsequent field effect transistor preparation process, and in addition, reduce the performance loss of the field effect transistor, and maintain relatively stable performance even when preparing devices with different channels.

[0016] In the present invention, the TMDs two-dimensional material is at least one of WS2, WSe2, MoS2, and MoSe2.

[0017] In the present invention, the TMDs two-dimensional material can be prepared based on known means, for example, the TMDs two-dimensional material is prepared by CVD or PVD method.

[0018] Preferably, the TMDs two-dimensional material is a single-layer or double-layer material.

[0019] In the present invention, the single-point radiation time of the laser Raman scanning is within 10 s, and further 0.0001 to 0.01 s.

[0020] In the present invention, the step spacing in the x-direction of the laser Raman scan is the width of the TMDs two-dimensional material minus the designed channel width; the step spacing in the y-direction is 0.1 to 0.5 μm; further, it can be 0.2 to 0.4 μm.

[0021] The present invention also provides laser Raman patterned TMDs prepared by the preparation method.

[0022] The present invention also provides an application of the laser Raman patterned TMDs prepared by the preparation method, and uses the TMDs to prepare p-type field effect transistors.

[0023] The application, the preparation method includes method 1 or method 2: wherein method 1 is: directly preparing the laser Raman patterned TMDs into a p-type field effect transistor;

[0024] Method 2 is: TMDs are prepared to form a p-type field effect transistor, and then the channel of the p-type field effect transistor prepared by the preparation method is subjected to the patterning treatment.

[0025] The process and ideas for forming the p-type field effect transistor in Mode 1 and Mode 2 of the present invention can be conventional. For example, in Mode 1, laser patterning is performed on the prefabricated TMDs, and then the metal electrode is point-to-point transferred to the patterned TMDs material to obtain the p-type field effect transistor. In Mode 2, PMMA can be pre-coated on the prepared TMDs, followed by EBL exposure, development and cleaning, source and drain electrode deposition, and gold stripping to obtain the p-type field effect transistor, and then the laser Raman processing process described in the present invention is used to non-destructively pattern the channel of the p-type field effect transistor.

[0026] The research of the present invention shows that the transistor prepared by transfer means can unexpectedly further optimize the performance of the prepared device.

[0027] Preferably, the channel width of the p-type field effect transistor is 3 to 25 μm, and can further be 12 to 16 μm; the channel length is 1 to 5 μm, and can further be 2 to 3 μm.

[0028] The present invention also provides a p-type field effect transistor described in the application.

[0029] Beneficial Effects

[0030] The present invention performs patterning processing on TMDs two-dimensional materials based on laser Raman scanning, and further cooperates with the joint control of parameters such as scanning mode and conditions, so as to achieve synergy and realize nearly lossless patterning of TMDs, simplify the patterning and subsequent field effect transistor preparation process, and in addition, reduce the performance loss of the field effect transistor, and maintain relatively stable performance even when preparing devices with different channels.

[0031] For example, the method of the present invention can produce a current density of 278.5 μA / μm and an on / off ratio of 3.9×10 7 High-performance device. And it can achieve stable performance under different channel widths. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 .High-performance double-layer WSe2 FET fabricated by combining laser patterning with transfer electrodes. (a) Schematic diagram of damage-free fabrication by combining laser patterning with transfer electrodes, where (i) laser patterning; (ii) transfer electrode alignment; (iii) conductive contact window opening. (bc) Transfer and output curves. Inset is device OM image, scale bar is 2μm. W=14.1μm, L=2.8μm.

[0033] Figure 2 Laser patterning of two-dimensional p-type WSe2 FETs. (a, b) Typical transfer curves (a, V) of three WSe2 FETs fabricated by laser patterning (w = 24 μm, black curve), (w = 14 μm, red curve), (w = 4 μm, blue curve) ds is -2V) and the output curve (b, V gs =-60 V); the inset is the OM image of the corresponding WSe2 FET, the scale bar is 10 μm. The area marked by the white box is the channel area.

[0034] Figure 3 .3×4 array of WSe2FETs fabricated by laser patterning with gold contacts on the same bilayer WSe2. Transfer curves of WSe2 FETs with a channel length of 2.0μm and a width of 5.0μm. Inset is a diagram of the device structure. Scale bar: 10μm.

[0035] Figure 4 Transfer curves of single-layer MoS2 FETs (channel length 3.0μm, width 20μm) fabricated using laser patterning and transfer electrodes. The inset is a diagram of the device structure.

[0036] Figure 5.Effects of EBL patterning and plasma etching process on double-layer p-type WSe2FET. (ae) Schematic diagram of each step in WSe2FET patterning, the upper right inset is the OM image of the device. Scale bar: 20μm. The white dashed box is the conductive channel of the device. (fg) Transfer curves of WSe2 FET at each process step in Figure a (Figure (f), V ds is 1V) and the output curve (Figure (g), V gs h, The values ​​extracted from Figures (f) and (g) indicate the on-state current density and threshold voltage of the WSe2 channel at the specified process steps.

[0037] Figure 6 .The effect of UV lithography on 2D p-type WSe2FET. (ab) Representative outputs of bilayer WSe2FETs fabricated at numerically specified process steps (a, V ds is -60V) and the transfer curve (b, V ds When V is -1V, gs (c) On-current and threshold voltage of WSe2 channel at the process step specified by the numbers extracted from Figure b. (d) Current density at each process step during UV photolithography patterning extracted from 9 WSe2 devices.

[0038] Figure 7 .Transfer curve of a double-layer WSe2 FET prepared after patterning in point-by-point scanning mode. The inset is the device structure. The scale is 20μm. DETAILED DESCRIPTION

[0039] The present invention is further described below through implementation cases, but the content of the present invention is not limited to the following content.

[0040] In the present invention, the TMDs can be prepared by conventional means.

[0041] For example, the material is two-dimensional WSe2, and the growth conditions for obtaining single crystal nanosheets by physical vapor deposition method are: growth temperature is 1120-1190°C, WSe2 solid powder sample is 3g, growth time is 2-5min, and carrier gas flow rate is 70-110sccm.

[0042] When the material is MoS2, the growth conditions for obtaining single crystal nanosheets by physical vapor deposition method are: growth temperature of 1180-1200°C, MoS2 solid powder sample of 3g, growth time of 8-25min, and carrier gas flow rate of 80-110sccm.

[0043] Preferably, the carrier gas is a protective gas.

[0044] The specific plan is as follows:

[0045] Embodiment 1:

[0046] Step 1: Preparation of bilayer WSe2

[0047] Weigh 3g of WSe2 solid powder sample and load it into an alumina boat, which is placed in a tubular furnace quartz tube (single and double-layer WSe2 nanosheets are grown using a bidirectional airflow CVD system. First, weigh a certain amount of WSe2 powder and spread it in a clean porcelain boat, and then push the porcelain boat into the central temperature zone of a single-temperature zone vacuum tube furnace. Place a blank silicon wafer with a 285nm oxide layer on another porcelain boat as a growth substrate, and then place them together in the downstream variable temperature zone of the temperature zone. The single-temperature tube furnace is packaged, and the entire system is pretreated with ultra-high purity argon (99.999%) for 10 Minutes to remove water vapor and gases such as oxygen in the gas path. Then use 70sccm argon as the carrier gas, adjust the carrier gas direction to the reverse gas flow direction (from the substrate to the WSe2 raw material), and heat to 1165°C at a rate of 25°C / min. When the center temperature of the heating zone reaches 1165°C, keep this temperature for two minutes to make the temperature of the reaction chamber completely constant. Then adjust the gas flow to a positive gas flow and grow at a constant temperature for 3 minutes until the growth is completed. Pull out the silicon wafer and wait for it to cool down. The high temperature area of ​​the silicon wafer tends to synthesize a double layer of WSe2, and the low temperature area is more likely to synthesize a single layer of WSe2.

[0048] Step 2: Laser Raman Processing

[0049] Laser patterning: WSe2 was placed on the stage under the Raman microscope lens, and a focused laser (488nm, 50mw) was used for line focus scanning mode. The single point irradiation of WSe2 channel material was 0.0001s. The Raman peak value in the scanning mode was 520cm -1 The step spacing in the x-direction of the laser Raman scan is the width of the two-dimensional material (40±2μm in this case)-the channel width (14.1μm in this case); the step spacing in the y-direction is 0.3μm.

[0050] Step 3: Preparation of WSe2 Field Effect Transistor

[0051] 1. Preparation of transferred Au electrodes: A 50 nm thick Au electrode was prepared on a sacrificial silicon substrate by photolithography and thermal evaporation. The beam current and dose used in the EBL process were 5029 pA and 280 μC cm, respectively. -2 The rate of thermal evaporation is The vacuum degree is 5×10 -4 The prepared Au electrode was placed in a sealed hexamethyldisilazane (HMDS) chamber at 80° C. for 15 to 20 minutes, and then spin-coated with PMMA twice at a spin-coating speed of 3000 rpm.

[0052] 2. Transfer alignment: The Au electrodes were peeled off using a PDMS stamp and transferred to the patterned TMDs to produce WSe2 FETs (the channel width W in this case was 14.1 μm and the length was 2.8 μm).

[0053] Test results see Figure 1 This method (combining laser patterning with transfer electrodes) avoids unintentional doping and damage caused by various steps (electron beam exposure, solvents, plasma, etc.), while effectively improving the gold semiconductor contact interface. The WSe2 FETs prepared in this case (channel width W is 14.1μm and length is 2.8μm) have a high on-state current of 278.5μA / μm, a 2 / V·s, and a high on / off ratio of 3.95×10 7 .

[0054] Example 2

[0055] Compared with Example 1, the only difference is that in step 2, laser Raman irradiation is used to obtain two-dimensional materials with channel widths of 24 μm (Example 2-1 Group), 14 μm (Example 2-2 Group), and 4 μm (Example 2-3 Group);

[0056] In step 3, the device is formed by evaporation:

[0057] Subsequently, the evaporation method was used to construct the patterned materials of different channels for electrode preparation, and the steps were as follows: 1. PMMA coating: polymethyl methacrylate (PMMA (A8)) was spin-coated on the sample twice at a speed of 4000 rpm and baked at 130°C for 2 minutes.

[0058] 2. EBL exposure: Electron beam lithography (EBL) was performed using a Raith 150Two to make exposure marks for subsequent positioning. The beam current and dose used in the EBL process were 5029pA and 280μC cm, respectively. -2 .

[0059] 3. Development and cleaning: The sample was developed in a solution of isopropyl alcohol: water (IPA:H2O) = 3:1 for 40 seconds and then immediately fixed (cleaned in IPA for 30 seconds).

[0060] 4. Source and drain electrode deposition: thermal evaporation process is used, where the deposition rate is The pressure is 5×10 -4 Pa, the deposition thickness is 50nm, and the evaporated metal is Au.

[0061] 5. Gold stripping: Soak in acetone for 1 hour.

[0062] Different devices were made. The test results are shown in Figure 2 The current densities of the three transistors are 22.4μA / μm, 25.9μA / μm, and 25.4μA / μm, respectively, and the on / off ratios are 1×10 8 , 1.5×10 8 , 2.3×10 8 The results show that the electrical performance of the three transistors remains highly consistent, indicating that the laser patterning method is able to maintain the intrinsic high quality of the material.

[0063] Example 3

[0064] Compared with Example 2, the only difference is that a 3×4 matrix is ​​etched on the same two-dimensional WSe2 single crystal using a line scanning laser patterning method, and a 3×4 transistor array with a channel length of 2 μm and a width of 5 μm is constructed based on the evaporation method of Example 2. The test results are shown in Figure 3 , compared with Example 2, the current density of multiple crystal units in the array is maintained between 20μA / μm and 25μA / μm, demonstrating the stability and reliability of laser processing.

[0065] Example 4

[0066] Compared with Example 1, the only difference is that the prepared substrate is MoS2 (preparation method is the same as above), and then the line scanning laser patterning method of Example 1 is used to pattern the two-dimensional single-layer MoS2 single crystal on the silicon nitride substrate, and then the transfer method of Example 1 is used to prepare the MoS2 FET. The test results are shown in Figure 4 The MoS2FETs (channel width W is 20 μm and length is 3.0 μm) prepared in this case have a high on-state current of 90.5 μA / μm and a high switching ratio of 4.5×10 7 .

[0067] Comparative Example 1

[0068] Compared with Example 2-2, the only difference is that step 2 uses a conventional electron beam irradiation method to replace the laser Raman treatment, and the difference in step 2 is:

[0069] Patterned printing: PMMAA8 positive electron beam gel coating: spin coating once at 3000 rpm and bake at 130 °C for 2 minutes.

[0070] EBL exposure: The electron beam is exposed according to the designed pattern. The beam current and dose used in the EBL process are 5029pA and 280μC cm respectively. -2 .

[0071] Development and cleaning: The sample was developed in a solution of isopropanol:water = 3:1 for 40 seconds and then immediately fixed (cleaned in isopropanol for 30 seconds).

[0072] N2 plasma treatment: power 80W; gas flow 80sccm; cleaning time 120s.

[0073] Sol: Soak in acetone for 40 minutes.

[0074] Then, the device is formed according to the evaporation electrode preparation method of Example 2.

[0075] Results Figure 5 , the data analysis shows that electron beam exposure has a great influence on the performance of WSe2 FET. -2 After electron beam irradiation and various processing steps, the current density is reduced from the original 1.87μA / μm to 0.23μA / μm, which is reduced by one order of magnitude. And the threshold voltage (V th ) shifts from -32.6 V to a negative gate voltage (-46 V). This indicates that this patterning method is not suitable for p-type two-dimensional materials.

[0076] Comparative Example 2

[0077] Compared with Example 2-2, the only difference is that step 2 is replaced by conventional UV patterning treatment, and the steps and conditions are as follows:

[0078] Patterning printing: BP212 positive photoresist coating: spin coat once at 3000 rpm and bake at 105 °C for 2 minutes.

[0079] UV lithography: lithography time is 300ms

[0080] Development and cleaning: put it into a NaOH solution with a volume fraction of 4‰ for development for 30 seconds, and then fix it (clean it in deionized water for 10 seconds).

[0081] N2 plasma treatment: power 80W; gas flow 80sccm; cleaning time 120s.

[0082] Sol: Soak in acetone solution for 30 to 40 minutes to remove residual BP212 positive photoresist.

[0083] Then, the device is formed according to the evaporation electrode preparation method of Example 2.

[0084] Results Figure 6, UV lithography and N2 plasma etching were used to pattern the material, which would damage the material and directly lead to a significant decrease in electrical performance. Finally, the current density of the WSe2 FET dropped sharply (to 0.85μA / μm), equivalent to 63% of the original value. In addition, by extracting the current density changes of 9 devices, it can be seen that the electrical performance of p-type WSe2 dropped to 16% to 60% of the original value, further confirming that this patterning method will unintentionally dope or damage the two-dimensional material and cannot maintain the original performance of the two-dimensional device.

[0085] Comparative Example 3:

[0086] Compared with Example 2-2, the only difference is that the focused laser scanning mode is point-by-point scanning mode, the scanning power is 20mw, and the scanning step length in the x direction is 0.3μm. The single point irradiation WSe2 channel material is 5s. The results are shown in Figure 7 The WSe2 FET (channel width 22 μm, length 3 μm) prepared in this way has a current density of 9.7 μA / μm and a switching ratio of 5.4×10 6 This is mainly because the point-by-point scanning method takes longer (more than 10 times) than the line scanning method, and long-term energy irradiation reduces device performance.

[0087] The devices of various embodiments and comparative examples were tested, and the results are shown in Table 1:

[0088] Table 1

[0089] Case Current density On / Off Ratio Example 1 278.5μA / μm <![CDATA[3.9×10 7 ]]> Example 2-1 22.4μA / μm <![CDATA[1×10 8 ]]> Example 2-2 25.9μA / μm <![CDATA[1.5×10 8 ]]> Example 2-3 25.4μA / μm <![CDATA[2.3×10 8 ]]> Example 4 90.5μA / μm <![CDATA[4.5×10 7 ]]> Comparative Example 1 0.23μA / μm <![CDATA[7.5×10 6 ]]> Comparative Example 2 0.85μA / μm <![CDATA[1.83×10 6 ]]> Comparative Example 3 9.7μA / μm <![CDATA[5.4×10 6 ]]>

[0090] The present invention performs patterning processing on TMDs two-dimensional materials based on laser Raman scanning, and further cooperates with the joint control of parameters such as scanning mode and conditions, so as to achieve synergy and realize nearly lossless patterning of TMDs, simplify the patterning and subsequent field effect transistor preparation process, and in addition, reduce the performance loss of the field effect transistor, and maintain relatively stable performance even when preparing devices with different channels.

Claims

1. A method for preparing laser Raman patterned TMDs, characterized in that: Laser confocal micro-Raman spectrometer was used to perform laser Raman scanning on TMDs two-dimensional materials to achieve patterning. The laser wavelength in the laser Raman scanning stage was 355-633 nm, the power was 40-60 mW, the scanning mode was line focus scanning mode, and the Raman peak value in the scanning mode was 1-1000 cm -1 .

2. The method for preparing laser Raman patterned TMDs according to claim 1, characterized in that: The TMDs two-dimensional material is at least one of WS2, WSe2, MoS2, and MoSe2.

3. The method for preparing laser Raman patterned TMDs according to claim 2, characterized in that: The TMDs two-dimensional material is prepared by CVD or PVD method; Preferably, the TMDs two-dimensional material is a single-layer or double-layer material.

4. The method for preparing laser Raman patterned TMDs according to claim 1, characterized in that: The single-point radiation time of the laser Raman scanning is within 10 seconds, and further 0.0001 to 0.01 seconds.

5. The method for preparing laser Raman patterned TMDs according to claim 1, characterized in that: The step spacing in the x-direction of the laser Raman scan is the width of the TMDs two-dimensional material minus the designed channel width; the step spacing in the y-direction is 0.1 to 0.5 μm. 6 . Laser Raman patterned TMDs prepared by the preparation method according to any one of claims 1 to 5 .

7. An application of laser Raman patterned TMDs prepared by the preparation method according to any one of claims 1 to 5, characterized in that: A p-type field effect transistor was prepared.

8. The use according to claim 7, characterized in that The preparation method includes method 1 or method 2: wherein method 1 is: directly preparing the laser Raman patterned TMDs into a p-type field effect transistor; Method 2 is: TMDs are prepared to form a p-type field effect transistor, and then the channel of the p-type field effect transistor prepared by the method according to any one of claims 1 to 5 is subjected to the patterning treatment.

9. The use according to claim 8, characterized in that The preparation method includes method 1 or method 2: wherein, in method 1, laser patterning is performed on the prefabricated TMDs, and then the metal electrode is point-to-point transferred to the patterned TMDs material to obtain the p-type field effect transistor; Alternatively, in the method 2, PMMA may be coated on the prepared TMDs in advance, followed by EBL exposure, development and cleaning, source and drain electrode deposition, and gold stripping to obtain the p-type field effect transistor, and then the laser Raman processing process of the present invention may be used to perform non-destructive patterning on the channel of the p-type field effect transistor, to obtain; Preferably, the channel width of the p-type field effect transistor is 3 to 25 μm; and the channel length is 1 to 5 μm.

10. A p-type field effect transistor as described in any one of claims 7 to 9.

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