Trigger resource detection method and device, equipment and medium

Abstract

The invention relates to the technical field of chip testing, and discloses a trigger resource detection method, device and equipment and a medium, the method is applied to an FPGA chip, and the FPGA chip comprises a plurality of triggers; the method comprises the steps of obtaining to-be-detected triggers in an FPGA chip, and dividing the to-be-detected triggers into a plurality of target test groups; the target test group comprises at least one trigger to be detected; constructing a cascade link, wherein the cascade link is connected with each target test group; a test signal is sent to the inlet end of the cascade link, and an output signal of the cascade link is received; and comparing the test signal with the output signal, and generating detection information of the trigger to be detected based on a comparison result. The trigger resource detection efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a trigger resource detection method, device, equipment and medium. Background Art

[0002] Field Programmable Gate Array is a programmable hardware platform with the characteristics of general flexibility, reconfiguration and parallel computing. It is widely used in many important fields such as national defense, medical treatment, computing acceleration and communication signal processing. The hardware logic circuit can be reconfigured through programming to adapt it to different application scenarios. Flip-Flop (FF) is one of the most basic logic resources in FPGA (Field-Programmable Gate Array) and is used to store data and status. In the FPGA production process, the trigger resource needs to be tested.

[0003] In the related art, all triggers on the routes of the input pins and output pins of the FPGA chip are usually connected in series. However, when the area of ​​the FPGA chip is large, the chip testing time will be long, increasing the testing cost.

[0004] In view of this, an efficient trigger resource detection method is needed. Summary of the invention

[0005] In view of this, the present invention provides a trigger resource detection method, which can improve the efficiency of trigger resource detection.

[0006] In a first aspect, the present invention provides a trigger resource detection method, which is applied to an FPGA chip, wherein the FPGA chip includes a plurality of triggers; the method includes: obtaining the triggers to be detected in the FPGA chip, and dividing the triggers to be detected into a plurality of target test groups; the target test group includes at least one trigger to be detected; constructing a cascade link, the cascade link connecting each target test group; sending a test signal to an input end of the cascade link, and receiving an output signal of the cascade link; comparing the test signal and the output signal, and generating detection information of the trigger to be detected based on the comparison result.

[0007] In this embodiment, the trigger to be detected of the FPGA chip is divided into several target test groups, and then the target test groups are connected to build a cascade link. By sending a test signal to the input end of the cascade link and receiving the output signal of the cascade link, the detection information of the trigger is obtained. The delay from the input end to the output end can be reduced, the simulation time of the trigger resource can be reduced, and the efficiency of the trigger resource detection can be improved.

[0008] In an optional implementation, dividing the triggers to be detected into several target test groups includes: obtaining routing resources of the FPGA chip, and determining a target number based on the routing resources; dividing the triggers to be detected into several target test groups, the target test groups including a target number of triggers to be detected.

[0009] In this implementation, the target quantity is determined according to the routing resources of the FPGA chip to determine the number of triggers to be detected in each target test group, which can improve the adaptability and flexibility of the method.

[0010] In an optional implementation, the number of input terminals of the target test group corresponds to the number of triggers to be detected of the target test group; the number of output terminals of the target test group is the same as the number of input terminals of the target test group.

[0011] In this embodiment, the number of input terminals of the target test group corresponds to the number of triggers to be detected in the target test group, and the number of output terminals is the same as the number of input terminals. When testing the trigger resources, the triggers to be detected in the target test group can be tested at the same time, thereby improving the efficiency of trigger resource detection.

[0012] In an optional embodiment, constructing a cascade link includes: determining a connection order of the cascade link; connecting an output end of a first target test group to an input end of a second target test group according to the connection order; and the second target test group is the next target test group of the first target test group in the connection order.

[0013] In this implementation, by acquiring the connection sequence of the cascade links and connecting the target test group according to the connection sequence, the signal transmission of the cascade links can be made more regular, thereby improving the convenience of trigger resource detection.

[0014] In an optional implementation, building a cascade link includes: determining the distribution status of each target test group on the FPGA chip; based on the distribution status, serially cascading the target test groups in the same column and parallel cascading the target test groups between different columns.

[0015] In this embodiment, by obtaining the distribution status of the target test groups on the FPGA chip, the target test groups in the same column are serially cascaded, and the target test groups in different columns are cascaded in parallel, which can reduce the test delay from the input end to the output end of the cascade link.

[0016] In an optional embodiment, the FPGA chip also includes a lookup table module in the target column; the lookup table module is used to obtain the output of the end target test group of the previous column of the target column, and the output of the previous target test group of the end target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the end target test group of the target column.

[0017] In this embodiment, the lookup table module is used to obtain the output of the end target test group of the previous column of the target column, and the output of the previous target test group of the end target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the end target test group of the target column. This can enable the test signals between different columns to be transmitted in parallel, reduce the delay of trigger resource detection, and improve the efficiency of trigger resource detection.

[0018] In an optional embodiment, the test signal and the output signal are compared, and based on the comparison result, detection information of the trigger to be detected is generated, including: comparing the test signal and the output signal, and based on the comparison result, obtaining the similarity between the test signal and the output signal; based on the similarity, generating detection information of the trigger to be detected.

[0019] In this implementation, by comparing the similarity between the test signal and the output signal, the trigger resource can be quickly detected, thereby improving the detection efficiency.

[0020] In the second aspect, the present invention provides a trigger resource detection device, which includes: a division module, used to obtain the triggers to be detected in the FPGA chip, and divide the triggers to be detected into several target test groups; the target test group includes at least one trigger to be detected; a construction module, used to construct a cascade link, the cascade link connects each target test group; a test module, used to send a test signal to the input end of the cascade link, and receive the output signal of the cascade link; a generation module, used to compare the test signal and the output signal, and generate detection information of the trigger to be detected based on the comparison result.

[0021] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the trigger resource detection method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0022] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the trigger resource detection method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a flow chart of a trigger resource detection method according to an embodiment of the present invention;

[0025] Figure 2 is a target test group connection schematic diagram according to an embodiment of the present invention;

[0026] Figure 3 is a flow chart of another trigger resource detection method according to an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of a cascade link according to an embodiment of the present invention;

[0028] Figure 5 is a flow chart of another trigger resource detection method according to an embodiment of the present invention;

[0029] Figure 6 is a structural block diagram of a trigger resource detection device according to an embodiment of the present invention;

[0030] Figure 7 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0032] During the FPGA production process, FPGA chips are susceptible to process defects, electrostatic discharge, temperature and stress, which may cause them to fail to meet expectations. FPGA chips need to undergo a series of mass production tests before leaving the factory, including wafer testing (Circuit Probe, CP) and package testing (Final Test, FT), to conduct detailed fault coverage tests on key resources in FPGA.

[0033] Important considerations in mass production design include coverage and test time. It is necessary to cover as many faults as possible with the fewest number of tests to ensure test quality while reducing the cost of mass production testing.

[0034] Flip-Flop (FF) is one of the most basic logic resources in FPGA, used to store data and status. In mass production design, it is necessary to efficiently achieve full coverage of FF resources to ensure the synchronous logic function of FF.

[0035] FF captures the value of the input signal at the rising or falling edge of the clock, and updates its output in the next clock cycle, that is, it needs to beat once every FF. In the related art, when testing FF, a cascade method is usually adopted. The specific cascade method is to connect all FFs in series on the route from INPAD (input end) to OUTPAD (output end), and the input-to-output delay is proportional to the number of FFs cascaded in the route. Therefore, when the FPGA chip area is large, it is easy to cause the test time to be too long and increase the test cost. A method that can efficiently realize FF resource detection is needed.

[0036] The embodiment of the present invention provides a trigger resource detection method, which divides the trigger to be detected of the FPGA chip into a plurality of target test groups, and then connects each target test group to build a cascade link. By sending a test signal to the input end of the cascade link and receiving the output signal of the cascade link, the detection information of the trigger resource is obtained. The time delay from the input end to the output end can be reduced, and the simulation time of the trigger resource can be reduced to improve the efficiency of the trigger resource detection.

[0037] According to an embodiment of the present invention, an embodiment of a trigger resource detection method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0038] In this embodiment, a trigger resource detection method is provided. The method is applied to an FPGA chip. The FPGA chip includes a plurality of triggers. Figure 1 is a flow chart of a trigger resource detection method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0039] Step S101, obtaining triggers to be detected in the FPGA chip, and dividing the triggers to be detected into a plurality of target test groups; each target test group includes at least one trigger to be detected.

[0040] When testing the trigger, you can first install the FPGA chip on a suitable development board and ensure that the power supply of the development board is stable and the pins are connected correctly. Then configure the development tool to enable it to identify the FPGA chip model on the development board. After successful identification, use the resource viewing function of the development tool to view the internal triggers, quantity and location of the FPGA chip. Determine the trigger to be tested based on the actual situation.

[0041] After the trigger to be detected is determined, it can be divided into several target test groups according to the position or function of the trigger to be detected. Each target test group contains at least one trigger to be detected.

[0042] In a specific implementation, the FPGA chip includes several tiles (tile modules), and each tile includes several triggers. According to the test purpose, the triggers to be tested can be selected from the triggers on the tile, and the triggers to be tested can be divided into several target test groups.

[0043] In an actual application, if all triggers in the FPGA chip need to be tested, the triggers can be divided into several test groups according to the type and distribution of the triggers; the test groups containing the same type and number of triggers can be constructed as target test sequences for subsequent testing. The number of target test sequences can be determined according to actual conditions.

[0044] During each test, the test group included in a target test sequence is used as the target test group for testing; after the test, the test group included in the next target test sequence is used as the target test group for the next round of testing until all target test sequences are tested. The number of target test sequences is the number of configurations covering all triggers on the FPGA chip. In subsequent tests, if there is a problem with the test information, it proves that the trigger in the target test group that the route passes through has a fault; if the test information is normal, it proves that the trigger in the target test group that the route passes through has no fault.

[0045] Step S102: construct a cascade link, the cascade link connecting each target test group.

[0046] Among them, the cascade link can be constructed according to the distribution status of the target test group. In some optional implementations, after determining a target test group in the cascade link, the target test group closest to the previous target test group can be selected from the remaining target test groups as the next connection test group of the cascade link, until all target test groups are connected to obtain a complete cascade link.

[0047] In some optional embodiments, such as Figure 2As shown in the figure, FFA, FFB, FFC and FFD represent four types of triggers. There are several tiles in the FPGA chip, and each tile has four types of triggers: FFA, FFB, FFC and FFD. According to the distribution of these four types of triggers, they are combined into several FF Groups, i.e., target test groups. Each FF Group includes one FFA, FFB, FFC and FFD type trigger. This means that this test can cover all FFA, FFB, FFC and FFD type triggers on the FPGA chip. The connection of the cascade link is as follows: Figure 2 As shown, the output of the Nth FF Group is connected to the input of the N+1th FF Group; FF_IN[0:3] represents the input of the FF Group, and the input has four lines connected to the inputs of the four types of triggers in the FF Group. BUS[0:3] represents the output of the FF Group, and the output has four lines connected to the outputs of the four types of triggers in the FF Group. That is, the outputs of the FFA, FFB, FFC, and FFD types of triggers in the Nth FF Group are connected to the inputs of the FFA, FFB, FFC, and FFD types of triggers in the N+1th FF Group.

[0048] Step S103: sending a test signal to the ingress end of the cascade link, and receiving an output signal of the cascade link.

[0049] The test signal may be a rectangular wave of a fixed frequency. The output signal is the output signal of the last target test group on the cascade link.

[0050] The output signal is directly connected to the last target test group on the cascade link for receiving, and an oscilloscope can also be connected after the output end of the cascade link to collect the data of the oscilloscope as the output signal.

[0051] Step S104, comparing the test signal and the output signal, and generating detection information of the trigger to be detected based on the comparison result.

[0052] Among them, the timing and waveform integrity of the output signal can be checked to obtain the test results of the trigger to be detected. After obtaining the detection information of the trigger to be detected, the test results of the trigger to be detected can be displayed on the screen display device. If the test results are abnormal, the staff can be reminded through the alarm device.

[0053] In a specific implementation, the test signal can be an excitation signal of a certain period. If the output signal of the cascade link is the same as the test signal, it means that there is no fault in the trigger to be detected. If the output signal does not meet expectations, that is, there is a large difference from the test signal, it means that there is a fault in the trigger to be detected on the cascade link.

[0054] In a practical application, there are multiple tiles on the FPGA chip to be tested, and each tile has the same type and number of FFs to be tested; the FFs to be tested on each tile are divided into several FF Groups, and each tile has the same division result for the FFs to be tested, that is, each tile includes the same number of FF Groups, and each FF Group includes the same type and number of FFs to be tested.

[0055] The number of detection configurations of the FF to be tested is the same as the number of FF Group types, that is, the first configuration detects the first type of FF Group on each Tile, and the second configuration detects the second type of FF Group on each Tile, until all types of FF Groups are detected. For each configuration, the corresponding FF Group on each Tile will be detected. In each configuration, the corresponding FF Groups on different Tiles are connected by cascading. The cascade routing can be solved locally and replicated across the entire chip without being limited by the chip scale.

[0056] The trigger resource detection method provided in this embodiment divides the trigger to be detected of the FPGA chip into several target test groups, and then connects each target test group to build a cascade link. By sending a test signal to the input end of the cascade link and receiving the output signal of the cascade link, the detection information of the trigger resource is obtained. The time delay from the input end to the output end can be reduced, and the simulation time of the trigger resource can be reduced to improve the efficiency of trigger resource detection.

[0057] In this embodiment, a trigger resource detection method is provided. The method is applied to an FPGA chip. The FPGA chip includes a plurality of triggers. Figure 3 is a flow chart of a trigger resource detection method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0058] Step S201, obtaining the triggers to be detected in the FPGA chip, and dividing the triggers to be detected into a plurality of target test groups; each target test group includes at least one trigger to be detected.

[0059] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0060] In some optional implementations, the above step S201 includes:

[0061] Step S2011, obtain the routing resources of the FPGA chip, and determine the target quantity based on the routing resources.

[0062] The routing resources of the FPGA chip can be obtained according to the data sheet of the FPGA chip, or the routing resources of the FPGA chip can be obtained by using an FPGA development tool.

[0063] Under the premise that routing resources allow, the number of triggers to be detected in each target test group should be as large as possible, and the number of target test groups should be as small as possible, so as to realize simultaneous detection of multiple triggers in the target test group in each detection configuration, reduce the number of detection configurations, and improve the detection efficiency of trigger resources.

[0064] Step S2012, dividing the triggers to be detected into a plurality of target test groups, where the target test groups include a target number of triggers to be detected.

[0065] The detection triggers can be divided according to their locations on the FPGA chip to reduce unnecessary wiring waste.

[0066] According to the routing resources of the FPGA chip, the number of triggers to be detected in each target test group is determined, which can improve the adaptability and flexibility of the method.

[0067] In some optional implementations, the number of input terminals of the target test group corresponds to the number of triggers to be detected of the target test group; the number of output terminals of the target test group is the same as the number of input terminals of the target test group.

[0068] The number of input terminals of the target test group is the number of triggers to be detected in the target test group. The number of output terminals of the target test group is the same as the number of input terminals of the target test group. When the number of triggers to be detected in the target test group is not 1, multiple detection signals can be simultaneously input to the triggers to be detected, and the output signals of the triggers to be detected can be received to achieve simultaneous detection of the triggers to be detected in the target test group, thereby improving the efficiency of trigger resource detection.

[0069] Step S202: construct a cascade link, the cascade link connecting each target test group.

[0070] Specifically, the above step S202 includes:

[0071] Step S2021, determine the distribution status of each target test group on the FPGA chip.

[0072] The distribution status of the target test group on the FPGA chip can be obtained through the FPGA development tool or directly through the FPGA data manual.

[0073] Step S2022, based on the distribution status, the target test groups in the same column are serially cascaded, and the target test groups in different columns are parallel cascaded.

[0074] Among them, the target test groups can be divided into columns according to their distribution status. After the division, adaptive adjustments can be made according to actual conditions. After the adjustment, the target test groups in the same column are serially cascaded, that is, the output end of the previous target test group is connected to the input end of the next target test group. The target test groups between different columns are cascaded in parallel, that is, the input end of the first target test group of each column of target test groups is connected to the inlet end of the cascade link to receive the test signal.

[0075] In some optional embodiments, the FPGA chip also includes a lookup table module in the target column; the lookup table module is used to obtain the output of the end target test group of the previous column of the target column, and the output of the previous target test group of the end target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the end target test group of the target column.

[0076] Among them, the lookup table module has three input signals, namely: the output of the end target test group of the previous column of the target column, the output of the previous target test group of the end target test group of the target column, and a control signal. These three input signals jointly control the lookup table and generate corresponding data signals for transmission to the input end of the end target test group of the target column.

[0077] The function of this control signal is to merge the output of the end target test group of the previous column of the target column and the output of the previous target test group of the end target test group of the target column. When the test data signal is 0, the control signal is used to control the lookup table module to perform an OR operation; when the test data signal is 1, the control signal is used to control the lookup table module to perform an AND operation.

[0078] The number and distribution of the lookup table modules can be determined according to actual conditions. In some optional implementations, the number of lookup table modules can be determined according to the number of columns of the target test group. In a specific implementation, if the cascade link has N columns of target test groups, then N-1 lookup table modules can be set.

[0079] In a practical application, each target test group includes only one trigger, and the construction result of the cascade link is as follows: Figure 4As shown, there are X columns of target test groups, each column of target test groups has Y rows of target test groups, and each target test group includes only one trigger, so FF is directly used to represent the target test group. Among them, CLK represents the clock signal, DATA represents the data signal, CTRL represents the control signal, and LUT (Look-Up Table) represents the lookup table module; clk represents the clock input terminal of the trigger, D represents the data input terminal of the trigger, and Q represents the data output terminal of the trigger. The clock signal is connected to the clock input terminal of each FF to control the sampling time of the FF. The DATA signal coming in from the entrance of the cascade link is passed to the FF at the bottom of each column and is serially cascaded from bottom to top. After the DATA signal of the first column enters the top FF serially, the output of the FF is combined with the DATA signal output by the second to last FF in the next column through the LUT as the input of the top FF in the next column. As shown Figure 4 The connection mode shown in the figure, the delay from input to output of the cascade link is k*(X+Y-1); if Figure 4 The same number of target test groups, each target test group includes only one trigger, and each trigger is connected in series. Then the delay of the cascade link from input to output is k*X*Y, where k is the proportional coefficient, which can be determined according to actual conditions.

[0080] By combining data signals of different columns using a lookup table module, the DATA signals between columns can be transmitted in parallel, and the test signal can reach the output end of the cascade link after passing through fewer triggers. This can greatly reduce the input-to-output delay, reduce test time and test cost.

[0081] Step S203: sending a test signal to the ingress end of the cascade link, and receiving an output signal of the cascade link.

[0082] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0083] In some optional implementations, the test signal may be flipped between 0 and 1 at regular intervals to fully detect all triggers on the FPGA chip.

[0084] Step S204, comparing the test signal and the output signal, and generating detection information of the trigger to be detected based on the comparison result.

[0085] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0086] In some optional implementations, the above step S204 includes:

[0087] Step S2041, comparing the test signal and the output signal, and obtaining the similarity between the test signal and the output signal based on the comparison result.

[0088] The signal features of the test signal and the output signal can be extracted, and the similarity between the output signal and the test signal can be obtained by comparing the signal features of the test signal and the output signal. Among them, the signal features can be determined according to the actual situation, and may include signal frequency, signal amplitude, signal phase, signal oscillation amplitude, etc. Through different signal features, the reliability of the detection result can be improved.

[0089] In some optional embodiments, multiple signal features can be extracted for comparison. According to the actual situation, the target signal feature type to be compared can be selected, the reference feature of the test signal can be extracted, and the reference sequence can be constructed; the output feature corresponding to the output signal can be extracted to construct the output sequence. The reference feature and the output feature correspond to the target signal feature type. Matching feature parameter pairs are determined in the reference sequence and the output sequence, and the parameter ratio of each feature parameter pair is calculated, and then the similarity between the reference sequence and the output sequence is generated based on each ratio result.

[0090] The similarity can be obtained by weighted fusion or averaging of the ratios of various parameters to improve the accuracy of the trigger resource detection result.

[0091] Step S2042: Generate detection information of the trigger to be detected based on the similarity.

[0092] Among them, a similarity threshold can be set, and the detection information of the trigger to be detected can be generated by judging the relationship between the similarity and the similarity threshold. If the similarity is greater than the similarity threshold, it means that the trigger resource is normal. If the similarity is less than the similarity threshold, the trigger resource is abnormal. It needs to be handled by staff.

[0093] By comparing the similarity between the test signal and the output signal, the trigger resources can be quickly detected to improve the detection efficiency.

[0094] The trigger resource detection method provided in this embodiment obtains the distribution status of the target test group in the cascade link, serially cascades the target test groups in the same column, and parallelly cascades the target test groups in different columns, thereby reducing the test delay from the input end to the output end of the cascade link.

[0095] In this embodiment, a trigger resource detection method is provided. The method is applied to an FPGA chip. The FPGA chip includes a plurality of triggers. Figure 5 is a flow chart of a trigger resource detection method according to an embodiment of the present invention. Figure 5 As shown, the process includes the following steps:

[0096] Step S301, obtaining the triggers to be detected in the FPGA chip, and dividing the triggers to be detected into a plurality of target test groups; each target test group includes at least one trigger to be detected.

[0097] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0098] Step S302: construct a cascade link, the cascade link connecting each target test group.

[0099] Specifically, the above step S302 includes:

[0100] Step S3021, determining the connection order of the cascade links.

[0101] The connection sequence may be determined according to the distribution state of the target test groups. In some optional implementations, connecting adjacent target test groups can reduce the waste of wiring resources and improve the efficiency of trigger detection.

[0102] Step S3022, connecting the output end of the first target test group to the input end of the second target test group according to the connection sequence; the second target test group is the next target test group of the first target test group in the connection sequence.

[0103] The connection between the first target test group and the second target test group can be as follows: Figure 2 shown.

[0104] Step S303: sending a test signal to the ingress end of the cascade link, and receiving an output signal of the cascade link.

[0105] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0106] Step S304, comparing the test signal and the output signal, and generating detection information of the trigger to be detected based on the comparison result.

[0107] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0108] The trigger resource detection method provided in this embodiment can make the signal transmission of the cascade link more regular and improve the convenience of trigger resource detection by obtaining the connection order of the cascade link and connecting the target test group according to the connection order.

[0109] In this embodiment, a trigger resource detection device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0110] This embodiment provides a trigger resource detection device, such as Figure 6 As shown, including:

[0111] The division module 401 is used to obtain the triggers to be detected in the FPGA chip and divide the triggers to be detected into several target test groups; each target test group includes at least one trigger to be detected.

[0112] A construction module 402 is used to construct a cascade link, the cascade link connecting each target test group;

[0113] The test module 403 is used to send a test signal to the ingress end of the cascade link and receive an output signal of the cascade link.

[0114] The generating module 404 is used to compare the test signal and the output signal, and generate detection information of the trigger to be detected based on the comparison result.

[0115] In some optional implementations, the division module 401 includes:

[0116] The quantity determination unit is used to obtain the routing resources of the FPGA chip and determine the target quantity based on the routing resources.

[0117] The division unit is used to divide the triggers to be detected into a plurality of target test groups, where the target test groups include a target number of triggers to be detected.

[0118] In some optional implementations, the number of input terminals of the target test group corresponds to the number of triggers to be detected of the target test group; the number of output terminals of the target test group is the same as the number of input terminals of the target test group.

[0119] In some optional implementations, the construction module 402 includes:

[0120] The sequence determination unit is used to determine the connection sequence of the cascade links.

[0121] The connection unit is used to connect the output end of the first target test group with the input end of the second target test group according to the connection sequence; the second target test group is the next target test group of the first target test group in the connection sequence.

[0122] In some optional implementations, the construction module 402 includes:

[0123] The distribution determination unit is used to determine the distribution status of each target test group on the FPGA chip.

[0124] The cascading unit is used to serially cascade the target test groups in the same column and parallelly cascade the target test groups in different columns based on the distribution state.

[0125] In some optional embodiments, the FPGA chip also includes a lookup table module in the target column; the lookup table module is used to obtain the output of the end target test group of the previous column of the target column, and the output of the previous target test group of the end target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the end target test group of the target column.

[0126] In some optional implementations, the generating module 404 includes:

[0127] The comparison unit is used to compare the test signal and the output signal, and obtain the similarity between the test signal and the output signal based on the comparison result.

[0128] The information generating unit is used to generate detection information of the trigger to be detected based on the similarity.

[0129] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0130] The trigger resource detection device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0131] The embodiment of the present invention also provides a computer device having the above Figure 6 The trigger resource detection device is shown.

[0132] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0133] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0134] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0135] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0136] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0137] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0138] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0139] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0140] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0141] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A trigger resource detection method, characterized in that: The method is applied to an FPGA chip, wherein the FPGA chip includes a plurality of triggers; the method includes: Acquire the triggers to be detected in the FPGA chip, and divide the triggers to be detected into a plurality of target test groups; the target test groups include at least one trigger to be detected; Constructing a cascade link, wherein the cascade link connects each target test group; Sending a test signal to an inlet end of the cascade link, and receiving an output signal of the cascade link; The test signal and the output signal are compared, and based on the comparison result, detection information of the trigger to be detected is generated.

2. The method according to claim 1, characterized in that The step of dividing the trigger to be detected into a plurality of target test groups includes: Acquire routing resources of the FPGA chip, and determine a target quantity based on the routing resources; The triggers to be detected are divided into a plurality of target test groups, each of which includes a target number of triggers to be detected.

3. The method according to claim 1, characterized in that: The number of input terminals of the target test group corresponds to the number of triggers to be detected of the target test group; the number of output terminals of the target test group is the same as the number of input terminals of the target test group.

4. The method according to claim 1, characterized in that: The step of constructing a cascade link includes: Determining a connection order of the cascade links; According to the connection sequence, the output end of the first target test group is connected to the input end of the second target test group; the second target test group is the next target test group of the first target test group in the connection sequence.

5. The method according to claim 1, characterized in that The step of constructing a cascade link includes: Determine the distribution status of each target test group on the FPGA chip; Based on the distribution status, the target test groups in the same column are cascaded in series, and the target test groups in different columns are cascaded in parallel.

6. The method according to claim 5, characterized in that The FPGA chip also includes a lookup table module in the target column; the lookup table module is used to obtain the output of the end target test group of the previous column of the target column, and the output of the previous target test group of the end target test group of the target column, and generate a corresponding control signal to be transmitted to the input end of the end target test group of the target column.

7. The method according to claim 1, characterized in that The comparing the test signal and the output signal, and generating detection information of the trigger to be detected based on the comparison result, comprises: Comparing the test signal with the output signal, and obtaining a similarity between the test signal and the output signal based on the comparison result; Based on the similarity, detection information of the trigger to be detected is generated.

8. A trigger resource detection device, characterized in that: The device comprises: A division module is used to obtain the triggers to be detected in the FPGA chip, and divide the triggers to be detected into a plurality of target test groups; each target test group includes at least one trigger to be detected; A construction module, used for constructing a cascade link, wherein the cascade link connects each target test group; A test module, used for sending a test signal to an inlet end of the cascade link and receiving an output signal of the cascade link; A generating module is used to compare the test signal with the output signal, and generate detection information of the trigger to be detected based on the comparison result.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the trigger resource detection method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the trigger resource detection method according to any one of claims 1 to 7.

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