Clock architecture and processing module

Abstract

The invention relates to the technical field of clock design, and relates to a clock architecture and a processing module. Comprising an M1 main clock module, an M2 standby clock module, a local clock generator module, a multipath selection circuit, a PLL circuit and a BMC circuit; the F function module is used for realizing functions in the system and comprises information acquisition and processing and data storage, a clock design part of the F function module consists of a PLL (Phase Locked Loop) circuit and slave equipment, and an input port of the PLL circuit is respectively connected with clock signals output by the master clock board and the standby clock board at the same level and outputs clock signals of a plurality of channels; and the C1 connector is used for connecting the M clock board and the F function board so as to ensure stable transmission of the clock signal. The method has the remarkable beneficial effects of improving the system stability, enhancing the fault-tolerant capability, simplifying the design complexity, improving the frequency stability and the like.

Description

Technical Field

[0001] The present application relates to the technical field of clock design, and more particularly to a clock architecture and a processing module. Background Art

[0002] At present, with the vigorous development and widespread application of artificial intelligence technology, the demand for high-speed data interfaces is showing an explosive growth trend. In this context, the requirements for bandwidth, rate and low latency characteristics of data transmission are becoming more and more stringent, which undoubtedly brings unprecedented challenges to high-speed circuit design. As a core component of high-speed circuit design, the importance of clock circuit is self-evident. The clock is like the heart of a digital circuit. Its stability and accuracy directly determine whether the system can perform at its best.

[0003] In complex and ever-changing circuit systems, multi-level circuit cascades are common, and efficient and accurate data communication needs to be achieved between modules to ensure the smooth operation of the entire system. To achieve this, frequency synchronization between modules is particularly critical. Frequency synchronization is the basis for ensuring accurate data transmission between modules. Once there is a large deviation in frequency or phase between two modules, data communication will be affected, and may even cause data transmission errors, which will pose a serious threat to the stability and reliability of the entire system.

[0004] In addition, in the design of circuit systems, clock redundancy and fault tolerance mechanisms are also indispensable and important links. In practical applications, the main clock may fail or be abnormal for various reasons. If there is no backup clock that can be switched immediately, the entire system may be paralyzed. This risk of single point failure is undoubtedly unacceptable for systems that pursue high reliability. Therefore, when designing circuit systems, clock redundancy and fault tolerance must be fully considered to ensure that the system can quickly switch to the backup clock when the main clock fails, thereby maintaining the normal operation of the system.

[0005] However, existing clock design solutions often have problems such as complex structure, high cost, and difficult maintenance, which are difficult to meet the actual needs of modern high-speed and high-reliability systems. Therefore, in the design of complex circuit systems, how to ensure frequency synchronization between different communication modules and how to achieve flexible switching between the main and standby clocks have become key issues that designers need to give priority to and focus on solving. In the future, with the continuous advancement and innovation of technology, we have reason to believe that these problems will be solved more effectively, thereby promoting more vigorous development in the field of high-speed circuit design.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a clock architecture and a processing module to solve the frequency synchronization and master-slave clock switching problems between different communication modules in a complex system, thereby improving the stability and reliability of the system.

[0009] include:

[0010] M1 master clock module, including local clock generator module, multi-way selection circuit, PLL circuit and BMC circuit, wherein the multi-way selection circuit has three input terminals, namely, upper level access, intra-station cascade in and local clock generator, the enable port of the multi-way selection circuit is controlled by the output signal of the BMC circuit, and the output signal of the multi-way selection circuit is connected to the input terminal of the PLL circuit;

[0011] M2 backup clock module, including local clock generator module, multiplexer circuit, PLL circuit and BMC circuit, used to provide backup clock signal when the main clock is abnormal;

[0012] The F functional module is used to realize the functions in the system, including information collection and processing, and data storage. Its clock design part is composed of PLL circuit and slave device. The input port of the PLL circuit is respectively connected to the clock signals output by the main clock board and the backup clock board of the same level, and outputs clock signals of multiple channels, which are respectively connected to the FPGA module, CPU module, GPU module, switch, high-speed serdes circuit, Retimer, BMC circuit, other communication modules and external connectors;

[0013] The C1 connector is used to connect the M clock board and the F function board to ensure stable transmission of the clock signal.

[0014] Preferably, the BMC circuit is connected to the PC end through an Ethernet port, and the PC end writes configuration information through the Ethernet port, so that the BMC circuit selects the output enable signal, controls the enable port of the multi-way selection circuit, and performs the gating of the clock signal. Through the Ethernet connection between the BMC circuit and the PC end, the user can conveniently write configuration information, thereby dynamically selecting the output enable signal, controlling the enable port of the multi-way selection circuit, and realizing flexible gating of the clock signal. This design not only improves the flexibility of the system, but also makes clock management more convenient and can adapt to the changes in requirements of different application scenarios.

[0015] Preferably, the PLL circuit in the F functional module performs clock skew removal and phase alignment to ensure frequency synchronization between different modules. The PLL circuit in the F functional module performs clock skew removal and phase alignment to ensure high-precision frequency synchronization between different modules. This not only improves the accuracy and stability of data transmission, but also helps to optimize overall system performance, especially in time-sensitive applications such as high-speed communication, real-time control, etc.

[0016] Preferably, the first channel of the PLL output is connected to the FPGA module; the second channel of the PLL output is connected to the CPU module; the third channel of the PLL output is connected to the GPU module; the fourth channel of the PLL output is connected to the switch; the fifth channel of the PLL output is connected to the high-speed serdes circuit; the sixth channel of the PLL output is connected to the Retimer; the seventh channel of the PLL output is connected to the BMC circuit; the eighth channel of the PLL output is connected to other communication modules; the ninth channel of the PLL output is connected to the external connector, which is a PCIE interface; the PLL output is used as the working reference clock of its connected part. The multiple channels of the PLL output are respectively connected to the FPGA, CPU, GPU, switch, high-speed serdes circuit, Retimer, BMC circuit and other communication modules, and even include external connectors such as PCIE interfaces, providing comprehensive clock support. This design enables the system to integrate a variety of high-performance components while maintaining the stability and consistency of the clock signal.

[0017] Preferably, the F functional module includes an F1 module, an F2 module and an F3 module.

[0018] Preferably, the clock sources of the local clock generators in the M1 main clock module and the M2 backup clock module include passive crystals, standard packaged active crystal oscillators, voltage-controlled crystal oscillators, crystal oscillators with temperature compensation, or constant temperature crystal oscillators. The local clock generators in the M1 main clock module and the M2 backup clock module use a variety of clock source options, including passive crystals, standard packaged active crystal oscillators, voltage-controlled crystal oscillators, crystal oscillators with temperature compensation, or constant temperature crystal oscillators, ensuring the diversity and high reliability of the clock sources. When the main clock fails, the backup clock can be quickly switched to avoid system paralysis, thereby improving the fault tolerance and stability of the system.

[0019] Preferably, the C1 connector adopts a backplane form, the insertion loss of the high-speed connector on the backplane does not exceed 1dB, and the insertion loss of the entire signal routing on the backplane does not exceed 6dB. The C1 connector adopts a backplane form, the insertion loss of the high-speed connector on the backplane does not exceed 1dB, and the insertion loss of the entire signal routing does not exceed 6dB, which effectively reduces the loss during signal transmission and ensures the integrity and quality of the clock signal.

[0020] Preferably, the clock architecture and processing module support intra-station cascading and multi-stage cascading. The clock architecture and processing module support intra-station cascading and multi-stage cascading, so that the system can be easily expanded to adapt to larger-scale network or system requirements. At the same time, the frequency of the output clock signal adopts second pulses through the Ethernet network port as the output interface, which further enhances the compatibility and scalability of the system.

[0021] Preferably, the clock signals outputted by the cascaded M1 main clock module and the M2 standby clock module within the station are outputted via an Ethernet port as an output interface, and the frequency of the output clock signal adopts pulse per second.

[0022] The clock architecture and processing module provided in the embodiment of the present disclosure propose an innovative clock architecture and processing module design method for the frequency synchronization and master-slave clock switching problems between different communication modules in a complex system. The design scheme has the following significant beneficial effects:

[0023] A separate clock board is used to generate the system clock and supply it to other functional boards, effectively ensuring the clock synchronization of the entire station. This design solves the communication error problem caused by excessive clock frequency phase deviation and improves the stability and reliability of the system.

[0024] Independent master and backup clock boards are designed. When the master clock module fails, the backup clock module can quickly take over the work to ensure that the system can continue to work normally. This redundant design greatly improves the system's fault tolerance and risk resistance.

[0025] The clock design is relatively simple, which not only solves the frequency synchronization problem between different modules, but also facilitates multi-level cascading, and can meet the needs of different scenarios. Whether it is intra-station cascading or inter-station cascading, it can be achieved through simple interfaces and configurations, which improves the flexibility and scalability of the system.

[0026] The local clock generator provides a variety of clock source options, including the oven-controlled crystal oscillator (OCXO) with high frequency stability, which is suitable for scenarios with high requirements for frequency stability, further improving the accuracy and stability of the system clock.

[0027] In summary, the clock architecture and processing module design method proposed in the present invention have shown significant beneficial effects in improving system stability, enhancing fault tolerance, simplifying design complexity, and improving frequency stability.

[0028] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0030] Figure 1 It is a schematic diagram of the clock architecture and processing module;

[0031] Figure 2 It is a schematic diagram of the connection between the clock module and the functional module in the station;

[0032] Figure 3 It is a schematic diagram of the internal structure of the functional module;

[0033] Figure 4 is a schematic diagram of a local clock generator in a clock module;

[0034] Figure 5 This is a schematic diagram of inter-station cascading. DETAILED DESCRIPTION

[0035] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0036] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0037] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0038] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0039] Unless otherwise stated, the term "plurality" means two or more.

[0040] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0041] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0043] Example 1

[0044] A clock architecture and processing module. The present invention proposes an innovative clock architecture and processing module design method, which aims to solve the frequency synchronization and master-slave clock switching problems between different communication modules in a complex system. The method generates and supplies the system clock through a separate clock board to ensure the clock synchronization in the entire station, thereby improving the stability and reliability of the system. At the same time, independent master-slave clock boards are designed to achieve redundant backup, thereby enhancing the system's fault tolerance and risk resistance. In addition, the clock design is simple and flexible, supports multi-level cascading, meets the needs of different scenarios, and further improves the accuracy and stability of the system clock by providing a variety of clock source options, such as a constant temperature crystal oscillator OCXO. In summary, the present invention has shown significant beneficial effects in improving system stability, enhancing fault tolerance, simplifying design complexity, and improving frequency stability.

[0045] The design of the clock architecture and processing module is distributed throughout the station. Figure 1 As shown, M1 is the main clock module, M2 is the backup clock module, C1 is the connector, and F1, F2 and F3 are all functional modules.

[0046] include:

[0047] M1 master clock module, including local clock generator module, multi-way selection circuit, PLL circuit and BMC circuit, wherein the multi-way selection circuit has three input terminals, namely, upper level access, intra-station cascade in and local clock generator, the enable port of the multi-way selection circuit is controlled by the output signal of the BMC circuit, and the output signal of the multi-way selection circuit is connected to the input terminal of the PLL circuit;

[0048] M2 backup clock module, including local clock generator module, multiplexer circuit, PLL circuit and BMC circuit, used to provide backup clock signal when the main clock is abnormal;

[0049] The F functional module is used to realize the functions in the system, including information collection and processing, and data storage. Its clock design part is composed of PLL circuit and slave device. The input port of the PLL circuit is respectively connected to the clock signals output by the main clock board and the backup clock board of the same level, and outputs clock signals of multiple channels, which are respectively connected to the FPGA module, CPU module, GPU module, switch, high-speed serdes circuit, Retimer, BMC circuit, other communication modules and external connectors;

[0050] The C1 connector is used to connect the M clock board and the F function board to ensure stable transmission of the clock signal.

[0051] As a refinement of the above embodiment, the BMC circuit is connected to the PC end through an Ethernet port, and the PC end writes configuration information through the Ethernet port, so that the BMC circuit selects to output an enable signal, controls the enable port of the multi-way selection circuit, and selects the clock signal.

[0052] Through the Ethernet connection between the BMC circuit and the PC, users can easily write configuration information to dynamically select the output enable signal, control the enable port of the multi-way selection circuit, and realize flexible gating of the clock signal. This design not only improves the flexibility of the system, but also makes clock management more convenient and can adapt to the changing needs of different application scenarios.

[0053] As a refinement of the above embodiment, the PLL circuit in the F functional module performs clock skew removal and phase alignment to ensure frequency synchronization between different modules.

[0054] The PLL circuit in the F functional module removes clock skew and aligns the phase internally, ensuring high-precision frequency synchronization between different modules. This not only improves the accuracy and stability of data transmission, but also helps optimize the overall system performance, especially in time-sensitive applications such as high-speed communication, real-time control, etc.

[0055] As a refinement of the above embodiment, Figure 3 As shown, the A and B ends of the PLL circuit input port are connected to the clock signals output by the main clock board and the standby clock board of the same level respectively. The first channel of the PLL output is connected to the FPGA module as the reference clock for its work; the second channel of the PLL output is connected to the CPU module as the reference clock for its work; the third channel of the PLL output is connected to the GPU module as the reference clock for its work; the fourth channel of the PLL output is connected to the switch as the reference clock for its work; the fifth channel of the PLL output is connected to the high-speed serdes circuit as the reference clock for its work; the sixth channel of the PLL output is connected to the Retimer as the reference clock for its work; the seventh channel of the PLL output is connected to the BMC circuit as the reference clock for its work; the eighth channel of the PLL output is connected to other communication modules as the reference clock for their work; the ninth channel of the PLL output can be connected to an external connector, such as a PCIE interface, as the reference clock for its work.

[0056] The multiple channels of PLL output are connected to FPGA, CPU, GPU, switch, high-speed serdes circuit, Retimer, BMC circuit and other communication modules, and even external connectors such as PCIE interface, providing comprehensive clock support. This design enables the system to integrate multiple high-performance components while maintaining the stability and consistency of the clock signal.

[0057] As a refinement of the above embodiment, the clock sources of the local clock generators in the M1 main clock module and the M2 backup clock module include passive crystals, standard packaged active crystal oscillators, voltage-controlled crystal oscillators, crystal oscillators with temperature compensation or constant temperature crystal oscillators.

[0058] The local clock generators in the M1 master clock module and the M2 backup clock module use a variety of clock source options, including passive crystals, standard packaged active crystal oscillators, voltage-controlled crystal oscillators, crystal oscillators with temperature compensation or constant temperature crystal oscillators, ensuring the diversity and high reliability of the clock source. When the master clock fails, the backup clock can be quickly switched to avoid system paralysis, improving the system's fault tolerance and stability.

[0059] As a refinement of the above embodiment, the C1 connector is in the form of a backplane, the insertion loss of the high-speed connector on the backplane does not exceed 1dB, and the insertion loss of the entire signal routing on the backplane does not exceed 6dB.

[0060] The C1 connector adopts a backplane form. The insertion loss of the high-speed connector on the backplane does not exceed 1dB, and the insertion loss of the entire signal routing does not exceed 6dB, which effectively reduces the loss during signal transmission and ensures the integrity and quality of the clock signal.

[0061] As a refinement of the above embodiment, the clock architecture and processing module support intra-station cascading and multi-stage cascading.

[0062] As a refinement of the above embodiment, the in-station cascade is that the clock signal output by the M1 master clock module is connected to the M2 standby clock module. Similarly, the clock signal output by the M2 standby clock module can also be connected to the M1 master clock module. The output interface adopts an Ethernet network port, and the frequency of the output clock signal adopts the form of second pulses.

[0063] Multi-level cascade, such as Figure 5 As shown. The clock signal of the upper level is connected to the M1 main clock module and the M2 backup clock module. The clock signal output by this station can also be output to the next level system.

[0064] The clock architecture and processing module support intra-station cascading and multi-level cascading, making the system easily expandable and adaptable to larger-scale network or system requirements. At the same time, the Ethernet port is used as the output interface, and the frequency of the output clock signal adopts second pulses, which further enhances the compatibility and scalability of the system.

[0065] Figure 1 and Figure 2In the BMC circuit, the baseboard management controller communicates with the host computer through the Ethernet port. The input source clocks include the local clock generator, the clock signal cascaded within the station, and the clock signal input from the external station. The BMC selects the input source clock by configuring the enable signal of the multiplexer. The output signal of the multiplexer is sent to the PLL circuit. The phase-locked loop of the first channel in the PLL circuit multiplies the output of the main clock signal PLL_CLK, and the second channel in the PLL circuit follows the output PLL_PP1S.

[0066] The F functional module outputs PLL_CLK and PLL_PP1S for the functional module, and is connected to its PLL circuit. The PLL circuit de-skews the clock internally, aligns the phases of PLL_CLK and PLL_PP1S, and ensures frequency synchronization between different modules. After the PLL circuit is synchronized, clock outputs of different frequencies are generated. Clocks of different frequencies are given to each slave device as reference clocks for the slave device to work.

[0067] The local clock generators in the M1 clock module and the M2 clock module, such as Figure 4 As shown. The local clock generator has a variety of clock source options, including passive crystal, standard package active crystal oscillator SPXO, voltage-controlled crystal oscillator VCXO, temperature-compensated TCXO, and constant temperature crystal oscillator OCXO. The frequency stability of SPXO, VCXO, and TCXO is generally at the ppm level, while the frequency stability of constant temperature crystal oscillator OCXO can reach the ppb level. In scenarios with high requirements for frequency stability, OCXO can be selected as the clock source of the local clock generator.

[0068] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0069] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other.

[0070] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0071] In the embodiments disclosed herein, the disclosed system can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units can be only a logical function division, and there can be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0072] The flow chart and block diagram in the accompanying drawings show the system architecture, function and operation that may be realized according to the system of the disclosed embodiment. In this regard, each square frame in the flow chart or block diagram can represent a part of a module, program segment or code, and the part of the module, program segment or code comprises one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in the opposite order sometimes, which can be determined according to the function involved.

Claims

1. A clock architecture and processing module, characterized in that: include: M1 master clock module, including a local clock generator module, a multi-way selection circuit, a PLL circuit and a BMC circuit, wherein the multi-way selection circuit has three input terminals: upper access, intra-station cascade and local clock generator, the enable port of the multi-way selection circuit is controlled by the output signal of the BMC circuit, and the output signal of the multi-way selection circuit is connected to the input terminal of the PLL circuit; M2 backup clock module, including local clock generator module, multiplexer circuit, PLL circuit and BMC circuit, used to provide backup clock signal when the main clock is abnormal; The F functional module is used to realize the functions in the system, including information collection and processing, and data storage. Its clock design part is composed of PLL circuit and slave device. The input port of the PLL circuit is respectively connected to the clock signals output by the main clock board and the backup clock board of the same level, and outputs clock signals of multiple channels, which are respectively connected to the FPGA module, CPU module, GPU module, switch, high-speed serdes circuit, Retimer, BMC circuit, other communication modules and external connectors; The C1 connector is used to connect the M clock board and the F function board to ensure stable transmission of the clock signal.

2. The clock architecture and processing module according to claim 1, characterized in that: The BMC circuit is connected to the PC end through an Ethernet port. The PC end writes configuration information through the Ethernet port, so that the BMC circuit selects to output an enable signal, controls the enable port of the multi-way selection circuit, and performs clock signal gating.

3. The clock architecture and processing module according to claim 1, characterized in that: The PLL circuit in the F functional module performs clock skew removal and phase alignment to ensure frequency synchronization between different modules.

4. The clock architecture and processing module according to claim 1, characterized in that: The first channel of PLL output is connected to the FPGA module; the second channel of PLL output is connected to the CPU module; the third channel of PLL output is connected to the GPU module; the fourth channel of PLL output is connected to the switch; the fifth channel of PLL output is connected to the high-speed serdes circuit; the sixth channel of PLL output is connected to the Retimer; the seventh channel of PLL output is connected to the BMC circuit; the eighth channel of PLL output is connected to other communication modules; The ninth channel output by the PLL is connected to an external connector, and the external connector is a PCIE interface; the PLL output serves as a working reference clock of the connected part.

5. The clock architecture and processing module according to claim 1, characterized in that: The F functional modules include an F1 module, an F2 module and an F3 module.

6. The clock architecture and processing module according to claim 1, characterized in that: The clock sources of the local clock generators in the M1 main clock module and the M2 standby clock module include passive crystals, standard packaged active crystal oscillators, voltage-controlled crystal oscillators, crystal oscillators with temperature compensation or constant temperature crystal oscillators.

7. The clock architecture and processing module according to claim 1, characterized in that: The C1 connector is in the form of a backplane.

8. The clock architecture and processing module according to claim 7, characterized in that: The insertion loss of the high-speed connector of the backplane does not exceed 1dB, and the insertion loss of the entire signal routing on the backplane does not exceed 6dB.

9. The clock architecture and processing module according to claim 1, characterized in that: The clock architecture and processing module support intra-station cascading and multi-stage cascading.

10. The clock architecture and processing module according to claim 9, characterized in that: The clock signals outputted by the cascaded M1 main clock module and the M2 standby clock module in the station are outputted via an Ethernet port as an output interface, and the frequency of the output clock signal adopts second pulses.

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