Voltage drop protection method and circuit

Abstract

The present technology relates to mitigating voltage drop conditions in systems with dynamic voltage and frequency scaling, and discloses a method of controlling a dynamic voltage and frequency scaling circuit, the method comprising: detecting a voltage drop relative to a current nominal voltage and frequency state; in response to the current nominal voltage and frequency state having a corresponding fallback state in a safe operating region of voltage and frequency, switching activity from a nominal source to a fallback source; and suspending the activity of the dynamic voltage and frequency scaling circuit when the current nominal voltage and frequency state cannot be fallback to the safe operating region.

Description

[0001] The present technology relates to methods and electronic circuits for mitigating voltage drop conditions in systems with dynamic voltage and frequency scaling.

[0002] Some computer circuits (eg, a central processing unit (CPU) or a graphics processing unit (GPU)) may experience performance issues. For example, the CPU may experience a voltage drop due to a large change in the current required from the power delivery network (PDN).

[0003] Mitigation measures are needed to address such performance issues.

[0004] The present technology is directed to solving or mitigating such performance issues or improving upon known mitigation techniques.

[0005] In a method for addressing some difficulties in alleviating voltage drop conditions in a system with dynamic voltage and frequency scaling, the present technology provides a method for controlling a dynamic voltage and frequency scaling circuit in a first method, the method comprising: detecting a voltage drop relative to a current nominal voltage and frequency state; switching activity from a nominal source to a fallback source in response to the current nominal voltage and frequency state having a corresponding fallback state in a safe operating area of ​​voltage and frequency; and suspending activity of the dynamic voltage and frequency scaling circuit when the current nominal voltage and frequency state cannot fall back to the safe operating area.

[0006] The dynamic voltage and frequency scaling circuit may include a clock circuit, wherein the nominal source may include a first phase locked loop, and wherein the back-off source may include a second phase locked loop.

[0007] The safe operating area may include a region of the voltage domain in which there is sufficient available frequency reduction to allow continued operation at a maximum possible voltage drop, and wherein outside the safe operating area may include at least one region of the voltage domain in which the maximum possible voltage drop risks rendering the circuit inoperable.

[0008] In another method, a method for controlling a dynamic voltage and frequency scaling circuit is provided, the method comprising: detecting a voltage drop relative to a current nominal voltage and frequency state; and suspending the activity of the dynamic voltage and frequency scaling circuit when the current nominal voltage and frequency state cannot fall back to a safe operating area.

[0009] In another method, an electronic circuit is provided, the electronic circuit comprising electronic logic components operable to perform the steps of the above method.

[0010] In another method, a non-transitory computer-readable medium is provided, which includes a structure of data and commands operable to cause a device to construct a set of electronic logic components, which when embedded in an electronic device and activated thereon causes the electronic device to perform the steps of the above method.

[0011] In another method, a system is provided, the system comprising: the above electronic circuit implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.

[0012] In another method, a chip-containing product is provided, the chip-containing product including the above system assembled on a separate board with at least one other product component.

[0013] In another method, a non-transitory computer readable medium for storing computer readable code for manufacturing the above-mentioned electronic circuit is provided.

[0014] Therefore, methods and circuits according to the present technology can be used to alleviate voltage drop conditions in systems with dynamic voltage and frequency scaling, and the method can be implemented in the form of a non-transitory computer-readable medium, which includes a structure of data and commands that can be operated to cause a device to construct a set of electronic logic components, which, when embedded in an electronic device and activated thereon, causes the electronic device to perform the steps of the method of the present technology as described above.

[0015] As will be apparent to those skilled in the art, a hybrid approach may also be employed where hardware logic, firmware and / or software may be used in any combination to implement the present technology.

[0016] Specific implementations of the disclosed technology will now be described, by way of example only, with reference to the accompanying drawings,

[0017] in:

[0018] Figure 1 A simplified example of a method of operation according to a specific implementation of the present technology is shown;

[0019] Figure 2A A voltage-frequency diagram is shown to give an example of a specific implementation of the present technology;

[0020] Figure 2B A simplified voltage-frequency diagram is shown to give an example of a specific implementation of the present technology;

[0021] Figure 3 A simple example of a multiplexing arrangement according to a specific implementation of the present technology is shown; and

[0022] Figure 4 Systems and products-in-a-chip are illustrated.

[0023] In integrated circuits, a voltage drop is a (usually) instantaneous decrease in voltage in a circuit. This is a well-known phenomenon, and may occur because, for example, the power supply has for some reason dropped below the normal operating voltage of the circuit, because a conductive element has drawn more current than normal, or because signal interference or noise on the power supply has caused voltage fluctuations.

[0024] Voltage drops can affect the operation of the circuit, for example by reducing the performance of the circuit and thus causing longer processing times. But there can also be more serious effects, for example, if the circuit draws more current to maintain performance levels, this can lead to increased power consumption and accompanying heat dissipation problems, which can lead to a reduced life of the device and in severe cases to a reduced life of the entire device. Voltage drops can also lead to data corruption or errors in the output. This is a very serious problem for applications that rely on the accuracy and reliability of the chip, for example, in safety-critical applications such as automotive or avionics systems.

[0025] The present technology solves some of the problems inherent in implementing dynamic voltage and frequency scaling (DVFS) circuits in conjunction with voltage drop mitigation schemes. Use cases for the present technology may include, for example, systems where it is necessary to maintain the accuracy of, for example, clock output signals. Such systems may include, for example, systems that require fault tolerance for safety reasons, such as automotive and avionics control systems, medical device control systems, etc.

[0026] In a dynamic voltage and frequency scaling (DVFS) circuit (such as a clock circuit) with a voltage drop mitigation scheme, a first clock source (e.g., PLL0) can provide a first clock called a "NOM clock", and a second clock source (e.g., PLL1) provides a second clock called a "FB clock". The frequency of the FB clock can be set lower than the frequency of the "NOM clock", thereby compensating for the voltage drop effect by reducing the frequency of the clock pulses. The NOM (for "nominal") clock is typically used to drive the output clock. In the event of a power supply voltage drop event, the FB (for "fallback") clock is used to drive the output clock as a voltage drop mitigation technique.

[0027] The voltage drop mitigation techniques contemplated herein are techniques that allow for voltage drops by providing the ability to reduce the frequency of the clock operation of the circuit to match the reduced voltage produced by the voltage drop. This is accomplished by providing a back-off frequency, typically by switching from a normal clock source (which may be referred to as a "nominal" clock) to a clock source having a lower frequency (which may be referred to as a "back-off" clock).

[0028] However, there are limitations to using this back-off approach in mitigating the effects of voltage sag, and so the present technique addresses the problem of allowing back-off to occur when there is sufficient “safe zone” margin in the system—that is, where the lowest point of any possible voltage drop protected by the back-off frequency is still above the circuit’s lower operating limit—to allow this, and to provide for a pause in activity in the event that there is not sufficient margin to allow further back-off.

[0029] Therefore, the present technology relates to how to perform a voltage drop mitigation scheme in conjunction with DVFS (dynamic voltage and frequency scaling). In particular, the present technology proposes a way to handle voltage drop events in the lowest DVFS mode. In the voltage drop mitigation scheme, the clock operates at the nominal frequency. The clock can switch to a lower fallback frequency when a voltage drop event is detected. Due to the nature of the voltage drop event, the supply voltage will also drop. This means that for the duration of the voltage drop event, the voltage and frequency operating point will move further along the DFVS curve. As long as the hold time is closed at the lowest voltage in the DVFS curve, it is safe to mitigate the voltage drop event in this way. For the lowest voltage in the DVFS curve, it may be unsafe to mitigate the voltage drop event in this way due to hold time violations - this can be called a sign-off event. Therefore, instead of switching to fallback, the present technology provides a method of pausing the clock during the duration of the voltage drop event.

[0030] Thus, the termination event is a voltage drop for which applying the fallback clock frequency is insufficient to ensure correct execution of the circuit functionality. This may be due to a rare deep voltage drop event, a power outage, or a programmed response when the nominal operating point of the circuit is already at a voltage floor, where the voltage drop includes the risk of hold timing failures, rather than setup timing failures that are addressed by the frequency reduction. Thus, in a particular implementation of the present technique, the response to the termination event is to hold the clock and rely on static data retention within the circuit until the termination event has passed.

[0031] First turn Figure 1 , a simplified flow chart of a method 100 of controlling a dynamic voltage and frequency scaling (DVFS) circuit according to one specific implementation of the present technology is shown. An example of the method begins at 102, and first, a circuit is operated 104 using an input NOM as a source. The voltage at NOM can be supplied at a predetermined frequency by a phase locked loop (PLL), for example, in a clock circuit. At 106, the presence of a voltage drop is detected. At 108, it is determined whether there is room in the safe operating region for falling back to a lower frequency of the DVFS circuit.

[0032] If there is a lower frequency back-off that is within the safe operating region (or where the safe operating region is available), i.e., where the back-off frequency and voltage are sufficient to meet the needs of the circuit during the voltage sag condition, the circuit is switched to use the back-off as the source instead of the NOM, and this instance of the method 100 ends at 114. As will be immediately apparent to one of ordinary skill in the art, this ending applies to a single instance of the method 100, and in a real world scenario, multiple instances of the method 100 may begin at 102 and complete at 114.

[0033] If no lower frequency is available at 108, where the back-off frequency and voltage are sufficient to meet the needs of the circuit (typically, where the lowest point of any voltage drop, and therefore the lowest frequency / voltage point of the back-off source, will be below a safe operating region where the circuit can operate properly), then activity is suspended at 112 for the duration of the voltage drop condition, and this instance of method 100 ends at 114. As will be immediately apparent to one of ordinary skill in the art, this termination applies to a single instance of method 100, and in a real world scenario, multiple instances of method 100 may be initiated at 102 and completed at 114.

[0034] Reference now Figure 2A , a voltage-frequency graph 200A is shown to give a simple example of a specific implementation of the present technology. Figure 2A An example of voltage and frequency behavior of a system that may operate according to a specific implementation of the present technology is shown. The red numbers 0-5 show the nominal frequency and voltage in a given DVFS mode. The green numbers 0-5 show the operating point under voltage drop mitigation, where the back-off frequency is used and the voltage is dropped by the voltage drop magnitude. As shown, under voltage drop mitigation in modes 1-5, the operating point can be made to stay on the DVFS curve. In mode 0, rather than switching to the back-off frequency, the clock is simply paused or gated.

[0035] Reference now Figure 2B, a simplified version of the same voltage-frequency diagram 200B is shown to give an example of a specific implementation of the present technology. As can be seen in the figure, in the case of frequency relative to voltage mapping, the changes in frequency and voltage can be represented by a DVFS curve. As the voltage decreases, the voltage drop mitigation technique according to the present technology provides a fallback to the source at a reduced frequency to compensate. For example, in this example, the nominal voltage / frequency 5N is the highest voltage supply source and operates at the highest available frequency. The corresponding fallback for the voltage drop shown by sliding back along the curve is 5FB, where the source that can be selected can operate at a reduced frequency when a voltage drop is detected. The difference is represented by the dotted nominal and feedback, between which is the area where the voltage drop can be accommodated at this level. Similarly, a fallback of 4FB can be provided to the nominal source 4N, and so on. Additional levels can continue with 3N / 3FB, etc., not shown here. All of these example pairings of N and FB are within a safe zone where possible voltage drops can be mitigated by switching the power supply to the corresponding FB frequency.

[0036] However, there is a limit at the bottom of the curve below which the possible backoff to accommodate the voltage drop is below the acceptable voltage and frequency levels sufficient to maintain proper operation of the circuit. This is shown as ON, where the possible lowest point of the voltage drop (i.e., the difference between nominal and backoff) will supply voltage and invoke a backoff that will fall outside the safe operating zone of the circuit's operating possibilities for the current nominal voltage / frequency state (where the safe operating zone is not available for the current nominal voltage / frequency state). In this case, the present technique is arranged to determine that any further reduction from ON in the event of a voltage drop will cause the circuit to leave its safe operating zone by invoking a backoff to a voltage / frequency state below the circuit's acceptable operating level, and therefore provide a pause function to pause activity at least until the voltage drop condition has ended.

[0037] Figure 3 One possible multiplexer structure operable to implement at least a portion of the process of the present technique in hardware is shown. Figure 3 A multiplexer 300 arrangement operable in an electronic circuit is shown. A clock MUX 306 is operable to receive an input NOM clock 302, which represents the nominal source at the current normal voltage and frequency tuning, and a FB clock 304, which represents the current available fallback source at the voltage drop mitigation voltage and frequency. The clock MUX 306 is controlled by clksel 308 to select the source for providing the output clkout 310.

[0038] therefore, Figure 3 A specific implementation of a glitch-free multiplexer is shown that can have three possible results for clkout 310:

[0039] If clksel[1:0]=0'b01, NOM clock is selected

[0040] If clksel[1:0] = 0'b10, select FB clock

[0041] If clksel[1:0] = 0'b00, the clock is not selected. In other words, clock propagation is stopped.

[0042] Therefore, an operating method, an electronic circuit, and a non-transitory computer readable medium including data and commands are provided, each according to an aspect of the present technology. The method provides a method of controlling a dynamic voltage and frequency scaling circuit, the method comprising: detecting a voltage drop relative to a current nominal voltage and frequency state; in response to the current nominal voltage and frequency state having a corresponding fallback state in a safe operating region of voltage and frequency, switching activity from a nominal source to a fallback source; and when the current nominal voltage and frequency state cannot fall back to the safe operating region, suspending the activity of the dynamic voltage and frequency scaling circuit.

[0043] The dynamic voltage and frequency scaling circuit may include a clock circuit. The nominal source may include a first phase-locked loop. The fallback source may include a second phase-locked loop. The safe operating area may include an area of ​​the voltage domain in which there is sufficient available frequency reduction to allow continued operation with a maximum possible voltage drop. In one specific implementation, the area outside the safe operating area may include at least one area of ​​the voltage domain in which the maximum possible voltage drop has a risk of rendering the circuit inoperable. The present technology may be implemented in an electronic circuit comprising an electronic logic component operable to perform the steps of the method. In one variation, the present technology may be implemented in the form of a non-transitory computer-readable medium comprising a structure of data and commands operable to cause a device to construct a set of electronic logic components that, when embedded in an electronic device and activated thereon, causes the electronic device to perform the steps of the method defined above.

[0044] like Figure 4As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the above-mentioned electronic circuit (or circuit system) is implemented on one chip or distributed on two or more of these chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package, which includes a protective housing (for example, made of metal, plastic, glass or ceramic) for accommodating a semiconductor device that implements the above-mentioned circuit system and a connector (such as a pad, solder ball or pin) for connecting the semiconductor device to the external environment. In the case of providing more than one chip 400, these chips can be provided as separate integrated circuits (provided as separate packages), or can be packaged into a multi-chip semiconductor package by a semiconductor provider (for example, using an interposer, or by using three-dimensional integration to provide a multi-layer chip product including two or more vertically stacked integrated circuit layers).

[0045] In some examples, a collection of chiplets (i.e., small modular chips with specific functionality) may themselves be referred to as a chip. A chiplet may be packaged individually in a semiconductor package and / or packaged with other chiplets into a multi-chiplet semiconductor package (e.g., using an interposer, or by using three-dimensional integration to provide a multi-layer chiplet product including two or more vertically stacked integrated circuit layers).

[0046] One or more packaged chips 400 are assembled on board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, for example, plastic, glass, ceramic, or a flexible substrate material such as paper, plastic, or textile material. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include, for example, any one or more of the following: another packaged chip (e.g., provided by a different manufacturer or produced at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0047] A chip-containing product 416 is manufactured, which includes a system 406 (including board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product component 412 includes one or more additional components that are not part of system 406. As a non-exhaustive list of examples, one or more product components 412 may include user input / output devices such as keyboards, touch screens, microphones, speakers, display screens, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical movement; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 can be assembled onto an additional board 414.

[0048] Plate 402 or additional plates 414 may be disposed on or within a device housing or other structural support (eg, a frame or blade) to provide a product that is manipulable by a user and / or intended for operational use by a person or company.

[0049] System 406 or chip-containing product 416 may be at least one of an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automated control system. For example, as a non-exhaustive list of examples, the chip-containing product may be any of the following: telecommunications equipment, mobile phones, tablet computers, laptop computers, computers, servers (e.g., rack servers or blade servers), infrastructure equipment, networking equipment, vehicles or other automotive products, industrial machines, consumer devices, smart cards, credit cards, smart glasses, avionics equipment, robotic equipment, cameras, televisions, smart TVs, DVD players, set-top boxes, wearable devices, home appliances, smart meters, medical devices, heating / lighting control equipment, sensors, and / or control systems for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0050] As will be appreciated by those skilled in the art, the present technology may be embodied as a method, a circuit, or a computer-readable medium including data and commands that cause the construction of a circuit. Thus, the present technology may take the form of a full hardware implementation, a full software implementation, or an implementation that combines software and hardware. Where the word "component" is used, it will be understood by those skilled in the art to refer to any portion of any of the above implementations.

[0051] The concepts described herein may be embodied in computer readable code for manufacturing devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying the concepts. The above computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification and / or testing of devices embodying the concepts described herein.

[0052] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register transfer level (RTL) abstraction for defining one or more logic circuits of an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions embodying concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of concepts that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0053] Additionally or alternatively, the computer readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representation to generate definitions for manufacturing devices embodying the present technology. Alternatively or additionally, one or more logic synthesis processes may generate from the computer readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts prior to manufacturing the integrated circuit, or the FPGA may be deployed directly in a product.

[0054] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to make a device embodying the present technology. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to make a device and computer readable code defining instructions to be executed by the defined device once manufactured.

[0055] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless code transmission over a network) or non-transitory computer readable medium such as a semiconductor, a magnetic disk, or an optical disk. An integrated circuit manufactured using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concepts alone or collectively.

[0056] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0057] In the present application, a feature list beginning with the phrase "at least one of..." means that any one or more of those features may be provided individually or in combination. For example, "at least one of [A], [B], and [C]" covers any of the following options: only A (without B or C), only B (without A or C), only C (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0058] Although exemplary embodiments of the present technology have been described in detail herein with reference to the accompanying drawings, it should be understood that the present technology is not limited to those precise embodiments and that various changes and modifications may be implemented therein by those skilled in the art without departing from the scope of the present technology as defined by the appended claims.

Claims

1. A method for controlling a dynamic voltage and frequency scaling circuit, the method comprising: Detect voltage drops relative to current nominal voltage and frequency conditions; In response to the current nominal voltage and frequency state having a corresponding fallback state in a safe operating region of voltage and frequency, switching activity from a nominal source to a fallback source; as well as When the current nominal voltage and frequency state cannot fall back to the safe operation area, the activity of the dynamic voltage and frequency scaling circuit is suspended. 2 . The method of claim 1 , wherein the dynamic voltage and frequency scaling circuit comprises a clock circuit. The method of claim 2 , wherein the nominal source comprises a first phase locked loop. The method of claim 2 , wherein the back-off source comprises a second phase locked loop.

5. A method according to any preceding claim, wherein the safe operating region comprises a region of the voltage domain in which there is sufficient available frequency reduction to allow continued operation at a maximum possible voltage drop.

6. A method according to any preceding claim, wherein outside the safe operating area comprises at least one region of the voltage domain in which a maximum possible voltage drop risks rendering the circuit inoperable.

7. A method for controlling a dynamic voltage and frequency scaling circuit, the method comprising: Detect voltage drops relative to current nominal voltage and frequency conditions; When the current nominal voltage and frequency state cannot fall back to the safe operation area, the activity of the dynamic voltage and frequency scaling circuit is suspended.

8. An electronic circuit comprising electronic logic components operable to perform the steps of the method according to any one of claims 1 to 7.

9. A non-transitory computer-readable medium comprising a structure of data and commands operable to cause a device to construct a set of electronic logic components, which, when embedded in an electronic device and activated thereon, causes the electronic device to perform the steps of a method according to any one of claims 1 to 7.

10. A system, comprising: The electronic circuit according to claim 8 implemented in at least one packaged chip; at least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

11. A chip-containing product, comprising the system according to claim 10, the system being assembled on another board with at least one other product component. 12 . A non-transitory computer readable medium for storing a computer readable code for manufacturing the electronic circuit according to claim 8 .

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