Binary translation method and apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application provide a binary translation method, device, electronic equipment and readable storage medium. The method comprises: after obtaining a first sequence by translating a to-be-processed block, adding a first instruction sequence in the first sequence; the first instruction sequence is used for writing a guest virtual address of a jump block corresponding to a function call instruction into a preset address record stack; translating the jump block to obtain a host virtual address of the jump block, and adding a second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block; if the to-be-translated guest instruction is a return instruction, obtaining a second sequence by translating the return instruction, and adding a third instruction sequence in the second sequence; the third instruction sequence is used for obtaining a record address corresponding to a return address of the return instruction from the address record stack as a target address, and jumping to the target address. The efficiency of the binary translator is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a binary translation method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] In the field of computer technology, a binary translation technology is usually used, that is, a translator is used to translate client instructions into host instructions, so that a program compiled by one Instruction Set Architecture (ISA) can run on a hardware platform of another Instruction Set Architecture.

[0003] With the application of the binary translation technology in various scenarios, there are usually a large number of return instructions in the client instructions. When the return instructions are translated, the host address corresponding to the return address of the return instruction needs to be determined. Therefore, in order to ensure the efficiency of binary translation, how to determine the host address corresponding to the return address has become a problem to be solved. SUMMARY

[0004] The purpose of the embodiment of the present application is to provide a binary translation method, device, electronic equipment and readable storage medium to solve the problem of how to determine the host address corresponding to the return address. The specific technical solutions are as follows:

[0005] In the first aspect of the present application, a binary translation method is first provided, which comprises:

[0006] After obtaining the first sequence by translating the to-be-processed block, a first instruction sequence is added in the first sequence; the first instruction sequence is used to write the client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the to-be-processed block is a to-be-translated basic block in which the function call instruction exists; the jump block is a basic block in which the next client instruction of the function call instruction is located;

[0007] The jump block is translated to obtain the host virtual address of the jump block, and a second instruction sequence is added in the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack;

[0008] If the to-be-translated client instruction is a return instruction, the return instruction is translated to obtain a second sequence, and a third instruction sequence is added in the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0009] In a second aspect of the present application, a binary translation device is provided, the device comprising:

[0010] a first adding module, configured to add a first instruction sequence in the first sequence after the first sequence is obtained by translating the to-be-processed block; the first instruction sequence is used to write a client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the to-be-processed block is a to-be-translated basic block in which the function call instruction exists; the jump block is a basic block in which a next client instruction of the function call instruction is located;

[0011] a first translation module, configured to translate the jump block to obtain a host virtual address of the jump block, and add a second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack;

[0012] a second translation module, configured to, if the to-be-translated client instruction is a return instruction, translate the return instruction to obtain a second sequence, and add a third instruction sequence in the second sequence; the third instruction sequence is used to obtain a record address corresponding to a return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0013] In a third aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus;

[0014] the memory is used to store a computer program;

[0015] the processor is used to execute the program stored on the memory, and implement the method in the first aspect.

[0016] In a fourth aspect of the present application, a computer readable storage medium is provided, the computer readable storage medium stores instructions, when the instructions are run on a computer, the computer executes the method in the first aspect.

[0017] In a fifth aspect of the present application, a computer program product containing instructions is provided, when the instructions are run on a computer, the computer executes the method in the first aspect.

[0018] The binary translation method provided by the embodiment of the present application stores the guest virtual address and the host virtual address of the jump block in the address record stack, adds the first instruction sequence and the second instruction sequence in the first sequence, and writes the guest virtual address and the host virtual address of the jump block into the address record stack in advance through the first instruction sequence and the second instruction sequence when the translated to-be-processed block is executed, so as to realize the pre-extraction of the jump address. Further, the third instruction sequence for obtaining the target address and jumping is additionally added when the return instruction is translated, so that the host computer can directly obtain the host address corresponding to the return address from the address record stack and jump when the host computer executes the return instruction, which improves the execution efficiency of the translated instruction to some extent, and thus improves the efficiency of the binary translator. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced.

[0020] Figure 1 is a step flow chart of a binary translation method in the embodiment of the present application;

[0021] Figure 2 is a flow chart of a binary translation method provided by the embodiment of the present application;

[0022] Figure 3 is a jump schematic diagram of a function call instruction and a return instruction provided by the embodiment of the present application;

[0023] Figure 4 is a translation schematic diagram of a jump block provided by the embodiment of the present application;

[0024] Figure 5 is a translation schematic diagram of a jump block provided by the embodiment of the present application;

[0025] Figure 6 is a schematic diagram of a first instruction sequence in the embodiment of the present application;

[0026] Figure 7 is a structure schematic diagram of a binary translation device in the embodiment of the present application;

[0027] Figure 8 is a schematic diagram of an electronic device in the embodiment of the present application. DETAILED DESCRIPTION

[0028] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0029] The terms "first", "second" and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a particular order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second" and the like are generally of a kind and are not limited in number, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the relationship between the associated objects, which means that there are three kinds of relationships, for example, A and / or B can represent the existence of A alone, the existence of A and B together, and the existence of B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "a plurality of" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0030] Figure 1 A flow chart of the steps of a binary translation method in an embodiment of the present application is shown in Figure 1 The method comprises:

[0031] Step 101, after obtaining a first sequence by translating a to-be-processed block, a first instruction sequence is added in the first sequence; the first instruction sequence is used to write a client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the to-be-processed block is a to-be-translated basic block in which the function call instruction exists; the jump block is a basic block in which a next client instruction of the function call instruction is located.

[0032] Step 102, the jump block is translated to obtain a host virtual address of the jump block, and a second instruction sequence is added in the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack.

[0033] Step 103, if the to-be-translated client instruction is a return instruction, a second sequence is obtained by translating the return instruction, and a third instruction sequence is added in the second sequence; the third instruction sequence is used to obtain a record address corresponding to a return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0034] For the above steps 101-103, the embodiments of the present application can be applied to any translator (also referred to as binary translator), which can be a user-level translator, and can also be a system-level translator, and the embodiments of the present application do not limit this. Specifically, the binary translation technology can realize the function of making the executable file compatible across ISAs. The dynamic binary translator can be divided into a user-level binary translator and a system-level binary translator. The user-level binary translator is mainly limited to the running of a single user state program, is suitable for executing target programs on different architectures without running the entire operating system, and is commonly used in software compatibility solutions that are cross-architecture but not cross-operating system. The system-level binary translator covers the running of the entire system, including the operating system kernel and the user state program, and can simulate a complete computer system on different architectures, and is usually used in software compatibility solutions that are both cross-architecture and cross-operating system, such as being used for running a Microsoft operating system (Windows) of a complex instruction set (CISC) architecture on a Linux system of a reduced instruction set (RISC) architecture, and also being used for running an Android system (Android) of a RISC architecture on a Windows of a CISC architecture, which are not listed one by one here. The system-level binary translator can also be used in scenarios such as virtualization, embedded development, and operating system migration.

[0035] Among them, the translator is used to translate a source program A in a guest (GUEST) into a target program B in a host (HOST), and execute the target program B in the host. The instructions in the source program A can be referred to as guest instructions, and the instructions in the target program B can be referred to as host instructions, and the guest instructions and the host instructions are instructions from different instruction set architectures.

[0036] Further, after reading the binary file, the translator usually translates and executes in units of a basic block (TB). Therefore, the basic block in the embodiments of the present application refers to the translation unit TB of the translator. The instructions in a basic block are sequentially executed from the first instruction of the basic block to the last instruction of the basic block by the processor, and there is no jump to other places or jump from other places to the non-first instruction of the basic block.

[0037] Figure 2 is a flowchart of binary translation provided by the embodiments of the present application, as shown in Figure 2As shown, after the translator reads the executable program (i.e., binary file) of the client platform, the translation and execution are usually performed in the granularity of basic blocks. Before executing a basic block, the target program is read in the code cache first. If a translated basic block is found, the code block is executed. If the basic block is not found in the code cache, the translation is performed and the translated code is put into the code cache, and then the basic block is executed. After executing a basic block, the next basic block is searched in the code cache, and the cycle is repeated until the program execution ends. Wherein, the basic block 0~basic block n correspond to different basic block translated host instruction units, and each host instruction unit contains translated host instructions (Code).

[0038] Wherein, the above-mentioned to-be-processed block refers to a to-be-translated basic block with a function call instruction. At this time, the to-be-processed block contains client instructions that have not been translated. The above-mentioned function call instruction refers to an instruction for calling a function or a subroutine. When the processor (Central Processing Unit, CPU) executes the function call instruction, it jumps to the called function or subroutine for execution. The function call instruction also depends on the return instruction, which is the core part of the function call and return mechanism, especially in the scene of supporting recursion or multi-layer function call, which is used to jump to the caller's code position for execution after the called function or subroutine is executed. At present, the function call instruction and the return instruction are used frequently in most programs, and the return instruction depends on the search of the return address, which has a large jump overhead, so that in the binary translation scene, the translation of the return instruction has a great influence on the efficiency of the binary translator.

[0039] Wherein, the above-mentioned jump block refers to the basic block where the next client instruction of the function call instruction is located. Specifically, in the instruction set architecture, the next instruction of the function call instruction is the default return address of the return instruction matched with the function call instruction, so the next instruction of the function call instruction is the TB where the corresponding return instruction jumps.

[0040] Exemplarily, Figure 3 is a jump schematic diagram of a function call instruction and a return instruction provided by an embodiment of the present application, as shown in Figure 3 As shown, the basic block 1~basic block 3, the basic block x, and the basic block y represent different basic blocks. Figure 3 The instruction (inst) in the above-mentioned basic block represents other instructions in the basic block, such as Figure 3As shown, the function call instruction (call) in TB1 indicates to jump to TB3 for execution, the jump instruction in TB3 indicates to jump to TBx for execution, and the return instruction (ret) in TBy represents to return to TB2 for execution. Since the function call instruction in TB1 is continuous with the address of instruction 1 in TB2, the TB starting from the next instruction of the call instruction is the target TB of the corresponding ret instruction, and thus the default return address of the ret instruction matched with the call instruction is the address of instruction 1, i.e., the next instruction of the call instruction.

[0041] The first sequence refers to a host instruction sequence obtained after processing a block. The GVA of the jump block corresponding to the function call instruction refers to the virtual address of a basic block in which a next instruction of the function call instruction is located in the guest machine. The address record stack can be preset and used to store required instruction addresses. The address record stack can be in the form of a data table or a stack, and can be set according to actual needs. The embodiments of the present application do not limit this.

[0042] The first instruction sequence is used to write the GVA of the jump block corresponding to the function call instruction into the preset address record stack. Specifically, the first instruction sequence can include a plurality of host instructions, which are used to write the GVA of the jump block of the function call instruction into the preset address record stack. Alternatively, the number of host instructions included in the first instruction sequence can be one or more, which is determined according to the instruction set architecture of the host machine. For example, if the instruction set architecture of the host machine uses at least n instructions to write any GVA into the memory, the first instruction sequence includes n host instructions.

[0043] Specifically, the first instruction sequence can be added to the end of the first sequence, or can be added to other positions according to actual conditions. The embodiments of the present application do not limit this.

[0044] The HVA of the jump block refers to the virtual address of the first host instruction of the jump block in the host machine. Further, after determining the jump block, the jump block can be translated to obtain the HVA of the jump block. Further, the second instruction sequence can be added to the first instruction sequence of the block to be processed corresponding to the jump block. The second instruction sequence is used to write the HVA as a record address corresponding to the GVA of the jump block into the address record stack.

[0045] Specifically, the GVA of the function call instruction and the record address in the address record stack can correspond to the same table entry. That is, the address record stack can include multiple table entries, and one table entry is used to record the GVA and the HVA of one jump block.

[0046] The second sequence refers to the host instruction sequence obtained by translating the return instruction. The return address refers to the client virtual address corresponding to the instruction to which the return instruction returns. Further, if the return instruction is translated, a third instruction sequence can be added in the second sequence corresponding to the return instruction, and the third instruction sequence is used to obtain the record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address. Specifically, after the return instruction is translated, the embodiment of the present application can search the preset record stack based on the return address of the return instruction, and if the record address corresponding to the return address is found, it indicates that the HVA of the jump block has been obtained. At this time, the third instruction sequence can be added to the second sequence.

[0047] In summary, the binary translation method provided by the embodiment of the present application adds the first instruction sequence in the first sequence after obtaining the first sequence by translating the to-be-processed block. The first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into the preset address record stack. The to-be-processed block is a basic block to be translated which contains the function call instruction. The jump block is a basic block in which the next client instruction of the function call instruction is located. The jump block is translated to obtain the host virtual address of the jump block, and the second instruction sequence is added in the first instruction sequence of the to-be-processed block corresponding to the jump block. The second instruction sequence is used to write the host virtual address as the record address corresponding to the client virtual address of the jump block into the address record stack. If the to-be-processed client instruction is a return instruction, the return instruction is translated to obtain the second sequence, and the third instruction sequence is added in the second sequence. The third instruction sequence is used to obtain the record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address. In this way, the embodiment of the present application stores the client virtual address and the host virtual address of the jump block in the address record stack, and adds the first instruction sequence and the second instruction sequence in the first sequence. When the to-be-processed block after translation is executed, the first instruction sequence and the second instruction sequence are used to write the client virtual address and the host virtual address of the jump block into the address record stack in advance, so as to realize the pre-extraction of the jump address. Further, the third instruction sequence for obtaining the target address and jumping is additionally added when the return instruction is translated. When the host executes the return instruction, the host address corresponding to the return address is directly obtained from the address record stack and jumps, which improves the execution efficiency of the translated instruction to a certain extent, thereby improving the efficiency of the binary translator.

[0048] Optionally, the first instruction sequence at least contains a to-be-replaced instruction sequence, and the to-be-replaced instruction sequence at least contains a self-jump instruction; and the operation of adding the second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block can specifically include the following operations:

[0049] S21, replacing the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence.

[0050] The self-jump instruction refers to an instruction jumping to itself, and a loop can be formed through the self-jump instruction, so that the processor continuously executes the instruction.

[0051] Specifically, before the second instruction sequence is added to the first instruction sequence, there can be a case that other threads execute the to-be-processed block, and at this time, the second instruction sequence has not been added to the first instruction sequence, which can cause a case that the instruction cannot be executed or is executed incorrectly or inefficiently. In order to avoid this problem, the embodiment of the present application can set a self-jump instruction in the first instruction sequence, and the self-jump instruction can realize interception of subsequent instructions, so as to prevent the case that other threads continue to execute forward when the second instruction sequence has not been added to the first instruction sequence.

[0052] Further, before the first instruction sequence is added to the first sequence, the host virtual address of the jump block has not been obtained, in order to facilitate subsequent addition of the second instruction sequence to the first instruction sequence, the embodiment of the present application can set the to-be-replaced instruction sequence containing the self-jump instruction in the first instruction sequence, to realize a placeholder operation.

[0053] Correspondingly, when the second instruction sequence is added to the first instruction sequence, the to-be-replaced instruction sequence in the first instruction sequence can be replaced with the second instruction sequence. Specifically, the embodiment of the present application can set a variable (for example, inst_ptr) to record the address of the to-be-replaced instruction sequence after the first instruction sequence is added to the first sequence, to facilitate replacement.

[0054] Optionally, the number of instructions contained in the to-be-replaced instruction sequence in the host architecture can be determined based on the instruction set of the host architecture. Since in some cases (for example, the host uses a RISC instruction set architecture), the host architecture needs multiple instructions to load an immediate number representing an address into an address recording stack, in this case, the to-be-replaced instruction sequence in the embodiment of the present application can also contain at least one no-operation instruction. The no-operation instruction (nop) refers to an instruction that does not have any impact on the state, register or memory of the processor, and it simply consumes one or more clock cycles. In the field of binary translation, the no-operation instruction is used for placeholder operation of an instruction before it is determined how to generate the instruction.

[0055] For example, if the host architecture assumes that at least n instructions can be used to load any 64-bit immediate address representation HVA into memory, then n-1 nops are needed in the replacement instruction sequence, in addition to the self-jump instruction.

[0056] In an embodiment of the present application, the first instruction sequence includes at least a to-be-replaced instruction sequence, and the to-be-replaced instruction sequence includes at least a self-jump instruction. The second instruction sequence is used to replace the to-be-replaced instruction sequence in the first instruction sequence. In this way, the self-jump instruction can be used to avoid the situation that other threads continue to execute forward when the second instruction sequence has not been added to the first instruction sequence. Meanwhile, the to-be-replaced instruction sequence can be used to implement placeholder, which facilitates the addition of the second instruction sequence to the first instruction sequence.

[0057] Optionally, after the first instruction sequence is added to the first sequence, an embodiment of the present application can further include:

[0058] S31, adding a to-be-modified mark to the first sequence.

[0059] After the second instruction sequence is used to replace the to-be-replaced instruction sequence in the first instruction sequence, an embodiment of the present application can further include:

[0060] S32, clearing the to-be-modified mark of the first sequence.

[0061] Before any of the first sequences is executed, an embodiment of the present application can further include:

[0062] S33, in the case where the first sequence includes the to-be-modified mark, modifying the self-jump instruction in the first sequence to a no-operation instruction.

[0063] Or, S34, in the case where the first sequence does not include the to-be-modified mark, executing the first sequence.

[0064] Specifically, in the process of system-level binary translation, the simulation of the entire operating system of the client is involved. In system-level binary translation, the mapping relationship between the client virtual address and the client physical address is directly managed by the client operating system. When a program accesses a virtual address that has not been mapped to the physical memory, a page fault exception is triggered. If an exception such as a page fault is triggered in the translation process, the processor will jump to the exception handling process for execution, and then jump to the address pointed to by the current program instruction pointer (Instruction Pointer, IP) after the execution of the exception handling process.

[0065] And since the modification of the to-be-replaced instruction sequence in the first instruction sequence depends on the translation of the jump block, if an exception such as a page fault is triggered in the translation process of the jump block, the current thread will be re-jumped to the to-be-processed block for execution, and at this time, the to-be-replaced instruction containing the self-jump instruction exists in the first sequence of the to-be-processed block, and thus executing the to-be-processed block will cause continuous looping at the self-jump instruction, which may cause the CPU to be stuck.

[0066] To avoid the above problem, the embodiment of the present application can add a to-be-modified mark to the first sequence after adding the first instruction sequence to the first sequence. The to-be-modified mark is used to indicate that the first sequence contains the self-jump instruction and needs to be modified. Specifically, the to-be-modified mark can be realized by setting a mark value for a preset variable, for example, a variable spot=1 can be set for the first sequence of the to-be-processed block to indicate that the to-be-modified mark is added to the first sequence. Of course, the to-be-modified mark can also be realized by other means, which are not limited in the embodiment of the present application.

[0067] Further, after adding the second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block, the to-be-modified mark of the first sequence can be cleared, indicating that the first sequence does not contain the self-jump instruction and does not need to be modified and can be executed normally. Alternatively, the to-be-modified mark can be cleared by switching the preset variable from the mark value to the initial value, for example, a variable spot=0 can be set for the first sequence of the to-be-processed block to indicate that the to-be-modified mark of the first sequence is cleared. Of course, the to-be-modified mark can also be cleared by other means, which are not limited in the embodiment of the present application.

[0068] Further, before executing the first sequence of any to-be-processed block, it can be determined whether the first sequence contains the to-be-modified mark. If it contains, the self-jump instruction in the first sequence is modified to a no-operation instruction before the first sequence is executed. Correspondingly, if it does not contain, the first sequence can be directly executed.

[0069] It should be noted that since the binary translator usually uses multiple threads to translate and execute the client program, the binary translation method provided by the embodiment of the present application can be applied to any thread in the binary translator.

[0070] Further, through the self-jump instruction in the above step S21, the embodiment of the present application can avoid the situation that the current thread executes incorrectly or inefficiently when other threads execute the to-be-processed block before the second instruction sequence is added to the first instruction sequence. The self-jump instruction can intercept the subsequent instructions to prevent other threads from continuing to execute forward when the second instruction sequence has not been added to the first instruction sequence.

[0071] Further, the current thread can be caused to recognize whether the first sequence contains the to-be-modified mark before executing any first sequence, execute the first sequence again in the case of not containing the to-be-modified mark, and correspondingly modify the self-jump instruction in the first sequence into a no-operation instruction and execute again in the case of containing the to-be-modified mark, so as to avoid the problem of continuously looping at the self-jump instruction caused by executing the to-be-processed block when the current thread triggers a page fault or the like in the translation process of the jump block.

[0072] In the embodiment of the present application, the first instruction sequence is added with the to-be-modified mark after the first instruction sequence is added with the first instruction sequence, the to-be-modified mark of the first instruction sequence is cleared after the second instruction sequence is used to replace the to-be-replaced instruction sequence in the first instruction sequence, the self-jump instruction in the first sequence is modified into a no-operation instruction in the case of containing the to-be-modified mark before executing any first sequence, or the first sequence is executed in the case of not containing the to-be-modified mark. In this way, the execution deadlock caused by translation exception before the to-be-replaced instruction sequence is replaced can be avoided.

[0073] Optionally, after the operation of adding the second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block, the embodiment of the present application can further include:

[0074] S41, if the jump block contains a function call instruction, the jump block is taken as a new to-be-processed block, a basic block in which a next client instruction of the function call instruction of the jump block is taken as a jump block corresponding to the new to-be-processed block, and the operation of translating the jump block to obtain the host virtual address of the jump block is executed again until the current jump block does not contain a function call instruction.

[0075] Specifically, since the next instruction of the function call instruction is also likely to exist in the TB (jump block), the jump block of the jump block can be translated in a recursive manner on this basis.

[0076] Specifically, if the jump block contains a function call instruction, the jump block is taken as a new to-be-processed block, a basic block in which a next client instruction of the function call instruction of the jump block is taken as a jump block corresponding to the new to-be-processed block, and the operation of translating the jump block to obtain the host virtual address of the jump block is executed again until the current jump block does not contain a function call instruction.

[0077] Specifically, Figure 4 is a translation schematic diagram of a jump block provided by the embodiment of the present application, as Figure 4As shown in the figure, for the basic block 1 (TB1) to be executed, it is firstly judged whether the TB1 has been translated, if yes, the TB1 is executed, if no, the normal translation process is executed on the TB1, and it is judged whether the just translated TB (i.e. TB1) ends with a function call instruction (i.e. whether there is a function call instruction call), if no, it indicates that the TB1 is not a block to be processed, and the TB1 can be executed normally. If yes, it indicates that the TB1 is a block to be processed, and the host virtual address of the jump block (next TB) needs to be obtained, and the next TB needs to be translated. It can be firstly judged whether the next TB of the call instruction has been translated, if yes, it indicates that the next TB does not need to be translated, and it is directly judged whether the TB ends with the call. If no, the next TB needs to be pre-translated to obtain the host virtual address. Further, if a pre-translation exception occurs, an exception processing process is executed, and after the exception processing is completed, the original TB1 is jumped to for execution. Correspondingly, if no pre-translation exception occurs, it is continuously judged whether the TB ends with the call, until the current jump block does not contain the function call instruction, and the TB1 can be executed normally.

[0078] Optionally, the embodiment of the present application can further include:

[0079] S51, in the case that any basic block is updated to an invalid state, a predecessor basic block of the basic block is obtained.

[0080] S52, if the predecessor basic block contains a function call instruction, a first instruction sequence in a first sequence corresponding to the predecessor basic block is replaced with a null operation instruction.

[0081] The invalid state refers to that the basic block is invalidated, and the basic block is marked as invalid when the translated basic block cannot correctly reflect the actual behavior of the program, which usually occurs in the scene of program self-modification.

[0082] In the case that any basic block is updated to an invalid state, the basic block should not be executed any more, but if the basic block is a jump block of a block to be processed, since the first instruction sequence is added in the first sequence and the third instruction sequence is added in the second sequence in the foregoing steps, the return instruction is directly jumped to the basic block for execution, and the program execution error occurs.

[0083] In order to avoid the above situation, the embodiment of the present application can obtain the predecessor basic block of the basic block updated to the invalid state.

[0084] The aforementioned predecessor basic block refers to a basic block where a last instruction of the basic block is located. If the predecessor basic block has a function call instruction, it indicates that the predecessor basic block is a to-be-processed block, and the current basic block is a jump block. At this time, in order to avoid that a return instruction corresponding to the to-be-processed block directly jumps to an invalid basic block when the return instruction is executed, a first instruction sequence in a first sequence corresponding to the predecessor basic block can be replaced by a null operation instruction.

[0085] In the embodiment of the present application, in a case where any basic block is updated to an invalid state, a predecessor basic block of the basic block is obtained. If the predecessor basic block has a function call instruction, a first instruction sequence in a first sequence corresponding to the predecessor basic block is replaced by a null operation instruction. In this way, a case where a return instruction corresponding to a to-be-processed block directly jumps to an invalid basic block when the return instruction is executed can be avoided, so that program execution errors are avoided.

[0086] Optionally, the embodiment of the present application can further include the following steps.

[0087] S61, a first parameter is configured for each basic block.

[0088] S62, after translating any basic block, in a case where a predecessor basic block of the basic block has a function call instruction, a parameter value of the first parameter of the basic block is obtained as a first determination value.

[0089] S63, if the first determination value is an initial value, the parameter value of the first parameter is updated to a basic block pointer of the predecessor basic block.

[0090] The operation of obtaining the predecessor basic block of the basic block can include the following steps.

[0091] S64, the predecessor basic block is obtained based on the parameter value of the first parameter of the basic block.

[0092] Specifically, the embodiment of the present application can configure a first parameter for each basic block, and after translating any basic block, it is determined whether a predecessor basic block has a function call instruction. If the predecessor basic block has the function call instruction, a parameter value of the first parameter of the basic block is obtained as a first determination value.

[0093] The initial value refers to an initial value when the first parameter is configured. The initial value can be 0 or null. The basic block pointer refers to a pointer of a basic block structure. The basic block structure is used to store information related to the basic block. Specifically, if the first determination value is the initial value, it indicates that the basic block currently has only one predecessor basic block. At this time, the parameter value of the first parameter can be updated to the basic block pointer of the predecessor basic block. Correspondingly, if the first determination value is not the initial value, it indicates that the basic block already has other predecessor basic blocks and the other predecessor basic blocks have been translated before the current predecessor basic block.

[0094] Further, the embodiment of the present application can obtain the predecessor basic block of a basic block through the parameter value of the first parameter of the basic block.

[0095] In the embodiment of the present application, the first parameter is configured for each basic block; after translating any basic block, if there is a function call instruction in the predecessor basic block of the basic block, the parameter value of the first parameter of the basic block is obtained as a first determination value; if the first determination value is an initial value, the parameter value of the first parameter is updated as the basic block pointer of the predecessor basic block; and the predecessor basic block is obtained based on the parameter value of the first parameter of the basic block. In this way, the basic block pointer of the predecessor basic block of each basic block can be stored in the first parameter, so that the predecessor basic block of a basic block can be obtained in time, and the processing efficiency is improved.

[0096] Optionally, the embodiment of the present application can further include:

[0097] S71, the second parameter is configured for each basic block.

[0098] S72, after translating any basic block, if there is the same function call instruction between the basic block and another basic block which has been translated, the parameter value of the second parameter of the other basic block is obtained as a second determination value.

[0099] S73, if the second determination value is an initial value, the parameter value of the second parameter of the other basic block is updated as the basic block pointer of the basic block.

[0100] The operation of obtaining the predecessor basic block based on the parameter value of the first parameter of the basic block, the embodiment of the present application can include:

[0101] S641, the first predecessor basic block of the basic block is obtained based on the parameter value of the first parameter of the basic block.

[0102] S642, the first predecessor basic block is taken as an initial basic block, and the linked basic block of the initial basic block is obtained based on the parameter value of the second parameter of the initial basic block.

[0103] S643, the linked basic block is taken as a new initial basic block, and the operation of obtaining the linked basic block of the initial basic block based on the parameter value of the second parameter of the initial basic block is executed again.

[0104] S644, the first predecessor basic block and the obtained linked basic block are determined as the predecessor basic block of the basic block.

[0105] It should be noted that in system-level binary translation, due to self-modification and the like, a basic block can jump to an exception handling process before being completely executed, and after the exception handling is completed, a TB is regenerated from a certain instruction in the middle and executed.

[0106] Figure 5 is a translation schematic diagram of a jump block provided by an embodiment of the present application, as shown in Figure 5 Basic block 1 (TB1) is a TB in which a predecessor function call instruction of basic block 2 (TB2) is located, that is, TB1 is a to-be-processed block corresponding to TB2, and TB2 is a jump block corresponding to TB1. Since TB1 jumps to an exception handling process before being completely executed, there are multiple TBs (basic block 1, basic block 1', and basic block 1'') ending with the same call instruction, and these multiple TBs all jump to the same jump block through a return instruction for execution, and thus all belong to the predecessor basic blocks of basic block TB2.

[0107] On this basis, an embodiment of the present application can configure a second parameter for each basic block, and after translating any basic block, if the basic block has the same function call instruction as another basic block that has been translated, it indicates that the basic block and the other basic block belong to the same basic block. On this basis, an embodiment of the present application can obtain a parameter value of the second parameter of the other basic block as a second determination value, and if the second determination value is an initial value, it indicates that the basic block is the first basic block that belongs to the same basic block as the other basic block. At this time, the parameter value of the second parameter of the other basic block can be updated to the basic block pointer of the basic block, so as to pass the affiliation of the basic block through the parameter value of the second parameter.

[0108] Further, the above operation of obtaining the predecessor basic block can first obtain the first predecessor basic block of the basic block based on the parameter value of the first parameter of the basic block. At the same time, the first predecessor basic block can be taken as an initial basic block, and a linked basic block of the initial basic block can be obtained based on the parameter value of the second parameter of the initial basic block. The above operation is repeatedly executed until the parameter value of the second parameter of the initial basic block is an initial value. At this time, the first predecessor basic block and the obtained linked basic block can be determined as the predecessor basic block.

[0109] Exemplarily, the first parameter can be P, and the second parameter can be PList, and the above step can include:

[0110] Step a: whenever the translation of a TB is completed, it is determined whether the predecessor TB1 of the TB ends with call. If it ends with call, it is determined whether P in the TB basic block structure is empty. If P is empty, step b is executed, and if P is not empty, step c is executed.

[0111] Step b, store the basic block pointer of the previous TB1 to P of the TB, and end the following step.

[0112] Step c, read the PList in the basic block TBn pointed by P, if the PList is empty, execute the following step e, otherwise execute the following step d.

[0113] For example, the P in TB2 is used to represent the basic block pointer of the first previous basic block TB1 of the TB. The Plist in TB1 stores the basic block pointer of TB1'. The Plist in TB1' stores the basic block pointer of TB1''. Figure 5

[0114] Step d, read the basic block pointer pointed by the PList in the basic block TBn, judge whether the PList in the basic block is empty, if not, make TBn= the basic block corresponding to the basic block pointer pointed by the PList in the basic block TBn; repeat the step until the basic block with empty PList is found, and then store the basic block pointer of the current TBn to the PList of the basic block with empty PList.

[0115] Step e, store the basic block pointer of TB1 to the PList of the basic block with empty PList.

[0116] Further, after the basic block is invalidated, the previous basic block of the basic block is obtained by the following steps:

[0117] Step f, judge whether the P in the basic block structure of the invalidated TB is empty, if yes, end the following steps, otherwise execute the following step g.

[0118] Step g, TBx = the basic block pointed by P, replace the first instruction sequence in TBx with nop, and set the P in TB as NULL.

[0119] Step h, judge whether the PList in TBx is empty, if yes, end the following steps, otherwise execute the following step i.

[0120] Step i, read the basic block pointer TBy pointed by the PList in TBx, replace the first instruction sequence in TBy with nop, set the PList in TBx as NULL, and judge whether the PList in TBy is empty, if yes, end the execution, otherwise TBx = TBy, repeat the step until the PList is empty.

[0121] In the embodiment of the application, all the previous basic blocks of the basic block can be obtained through the first parameter and the second parameter, the omission of the search of the previous basic block is avoided, and the accuracy of the program execution is further ensured. ​

[0122] Optionally, the embodiments of the present application can further include:

[0123] S81, in the case of flushing the translation lookaside buffer, or the storage data of the address record stack reaches a preset storage threshold, clearing the storage data in the address record stack.

[0124] The translation lookaside buffer (TLB) refers to a page table cache used by the memory management unit to improve the speed of virtual address to physical address translation. When the TLB is flushed, it indicates that process scheduling switching may occur, and at this time, in order to avoid jumping to the wrong address in program execution, the storage data in the address record stack can be cleared.

[0125] The preset storage threshold refers to the maximum number of storage data, which can be pre-set, and the embodiments of the present application do not limit it. Accordingly, when the storage data of the address record stack reaches the preset storage threshold, it indicates that the address record stack is full, and in order to avoid address record stack overflow, the storage data in the address record stack can be cleared at this time.

[0126] Optionally, the address record stack can be a stack structure. The stack is a linear data structure that can only be inserted and deleted at one end. This end is called the top of the stack, and the other end is called the base of the stack. Its characteristic is to follow the principle of last in first out, that is, the last element put in is taken out first. Accordingly, the address record stack can also be called a return address stack (RAS). The depth of RAS is N, N is 2 raised to the power of n, and each item consists of GVA and HVA. GVA refers to the GVA of the target TB returned by the ret instruction, and HVA refers to the HVA of the target TB returned by the ret instruction.

[0127] On this basis, the operation of clearing the data of the address record stack can be achieved by pointing the stack pointer to the initial position. Specifically, in order to avoid stack data overflow, a mask mechanism can be used to automatically clear the RAS stack when the RAS stack is full. Specifically, taking the depth of the RAS as N as an example, the mask is set to N-1, and the top of the stack based on the item number index of the stack bottom is n when the stack is pressed. Then, before each stack is pressed, n = n&mask is set, so that the stack pointer can be automatically pointed to the initial position when the stack is overflowed.

[0128] Further, when the address record stack is a stack structure, the first instruction sequence can further include instructions for loading the top of the RAS stack, instructions for pressing the GVA into the top of the RAS stack, and instructions for updating the pointer of the top of the RAS stack. Illustratively, Figure 6As shown in a schematic diagram of a first instruction sequence in an embodiment of the present application, Figure 6 the first instruction sequence includes: an instruction for loading a return address stack (RAS) top (load top), an instruction for pushing a guest virtual address (GVA) into the RAS top (push gva), a self-jump instruction (b0), a no-operation instruction (nop), and an instruction for updating the RAS top pointer (update top).

[0129] Further, when the address record stack is a stack structure, the second instruction sequence is an instruction sequence of the push hva semantics. The third instruction sequence can include an instruction for loading the RAS top, an instruction for taking out the GVA in the RAS top, an instruction for taking out the HVA in the RAS top, an instruction for updating the RAS top pointer, an instruction for judging whether the GVA is consistent with the return target guest virtual address, and an instruction for jumping to the HVA to continue executing the subsequent code if consistent, or an instruction for executing the return instruction operation of the normal path if inconsistent.

[0130] Figure 7 As shown in a structural schematic diagram of a binary translation device in an embodiment of the present application, Figure 7 the device 20 can include:

[0131] a first adding module 201, configured to add a first instruction sequence in a first sequence obtained by translating a to-be-processed block; the first instruction sequence is used for writing a guest virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the to-be-processed block is a basic block to be translated and containing the function call instruction; the jump block is a basic block in which a next guest instruction of the function call instruction is located;

[0132] a first translation module 202, configured to translate the jump block to obtain a host virtual address of the jump block, and add a second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used for writing the host virtual address as a record address corresponding to the guest virtual address of the jump block into the address record stack;

[0133] a second translation module 203, configured to, if a to-be-translated guest instruction is a return instruction, translate the return instruction to obtain a second sequence, and add a third instruction sequence in the second sequence; the third instruction sequence is used for obtaining a record address corresponding to a return address of the return instruction from the address record stack as a target address, and jumping to the target address.

[0134] Optionally, the first instruction sequence at least includes a to-be-replaced instruction sequence, and the to-be-replaced instruction sequence at least includes a self-jump instruction; the first translation module includes:

[0135] a first replacing sub-module, configured to replace the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence.

[0136] Optionally, the apparatus further comprises a mark adding module, configured to add a to-be-modified mark to the first sequence after the first adding module adds the first instruction sequence in the first sequence.

[0137] The apparatus further comprises a first clearing module, configured to clear the to-be-modified mark of the first sequence after the replacing sub-module replaces the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence.

[0138] The apparatus further comprises:

[0139] a modifying module, configured to, before execution of any of the first sequences, modify a self-jump instruction in the first sequence to a no-operation instruction if the first sequence contains the to-be-modified mark, or execute the first sequence if the first sequence does not contain the to-be-modified mark.

[0140] Optionally, the apparatus further comprises:

[0141] an executing module, configured to, after the first translating module adds the second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block, if the jump block contains a function call instruction, take the jump block as a new to-be-processed block, take a basic block in which a next client instruction of the function call instruction of the jump block is located as a jump block corresponding to the new to-be-processed block, and perform the operation of translating the jump block to obtain the host virtual address of the jump block again until the current jump block does not contain a function call instruction.

[0142] Optionally, the apparatus further comprises:

[0143] a first obtaining module, configured to, if any of the basic blocks is updated to an invalid state, obtain a precedent basic block of the basic block.

[0144] a second replacing module, configured to, if the precedent basic block contains a function call instruction, replace a first instruction sequence in a first sequence corresponding to the precedent basic block with a no-operation instruction.

[0145] Optionally, the apparatus further comprises a first configuring module, configured to configure a first parameter for each of the basic blocks.

[0146] a second obtaining module, configured to, after translation of any of the basic blocks, if the precedent basic block of the basic block contains a function call instruction, obtain a parameter value of the first parameter of the basic block as a first determination value.

[0147] The first updating module is configured to update a parameter value of the first parameter to a basic block pointer of the preceding basic block if the first determination value is an initial value.

[0148] The first obtaining module is specifically configured to:

[0149] obtain the preceding basic block based on the parameter value of the first parameter of the basic block.

[0150] Optionally, the apparatus further comprises a second configuring module configured to configure a second parameter for each of the basic blocks.

[0151] The third obtaining module is configured to, after translating any of the basic blocks, obtain a parameter value of the second parameter of another basic block as a second determination value if the basic block and the another basic block have a same function call instruction.

[0152] The second updating module is configured to update the parameter value of the second parameter of the another basic block to the basic block pointer of the basic block if the second determination value is an initial value.

[0153] The first obtaining module comprises:

[0154] The fourth obtaining submodule is configured to obtain a first preceding basic block of the basic block based on the parameter value of the first parameter of the basic block.

[0155] The fifth obtaining submodule is configured to take the first preceding basic block as an initial basic block, and obtain a linking basic block of the initial basic block based on a parameter value of a second parameter of the initial basic block.

[0156] The sixth obtaining submodule is configured to take the linking basic block as a new initial basic block, and execute again the operation of obtaining the linking basic block of the initial basic block based on the parameter value of the second parameter of the initial basic block.

[0157] The basic block determining module is configured to determine the first preceding basic block and the obtained linking basic block as the preceding basic blocks of the basic block.

[0158] Optionally, the apparatus further comprises:

[0159] The second clearing module is configured to clear the stored data in the address record stack in a case that a translation lookaside buffer is refreshed, or stored data of the address record stack reaches a preset storage threshold.

[0160] To sum up, the binary translation device provided by the embodiment of the application adds a first instruction sequence in the first sequence after obtaining the first sequence by translating the to-be-processed block; the first instruction sequence is used for writing the guest virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the to-be-processed block is a basic block to be translated and existing the function call instruction; the jump block is a basic block in which a next guest instruction of the function call instruction is located; the jump block is translated to obtain a host virtual address of the jump block, and a second instruction sequence is added in the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used for writing the host virtual address as a record address corresponding to the guest virtual address of the jump block into the address record stack; if the to-be-translated guest instruction is a return instruction, the return instruction is translated to obtain a second sequence, and a third instruction sequence is added in the second sequence; the third instruction sequence is used for obtaining a record address corresponding to a return address of the return instruction from the address record stack as a target address, and jumping to the target address. In this way, the embodiment of the application stores the guest virtual address and the host virtual address of the jump block in the address record stack, and the first instruction sequence and the second instruction sequence are added in the first sequence, so that the guest virtual address and the host virtual address of the jump block can be written into the address record stack in advance through the first instruction sequence and the second instruction sequence when the to-be-processed block after translation is executed, and the jump address can be pre-extracted. Further, the third instruction sequence for obtaining the target address and jumping is additionally added when the return instruction is translated, so that the host address corresponding to the return address can be directly obtained from the address record stack and jumped to when the host executes the return instruction, the execution efficiency of the translated instruction is improved to a certain extent, and thus the efficiency of the binary translator is improved.

[0161] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts are described in the part of the method embodiment.

[0162] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0163] As for the request processing device in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0164] The embodiment of the application further provides an electronic device, including a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above binary translation method.

[0165] Referring to Figure 8 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. As shown in Figure 8 , the electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing at least one executable instruction, and the executable instruction makes the processor execute the binary translation method of the foregoing embodiment.

[0166] It should be noted that the electronic device in the embodiments of the present application comprises a mobile electronic device and a non-mobile electronic device.

[0167] The processor can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable device, a transistor logic device, a hardware component or any combination thereof. The processor can also be a combination for realizing a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0168] The communication bus can comprise a path for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect, peripheral component interconnect) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 3 only one line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0169] The memory can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0170] The embodiment of the present application further provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), the processor can execute Figure 1 the binary translation method shown.

[0171] The embodiment of the present application further provides a computer program product containing instructions, when the computer program product is run on a computer, the computer can execute Figure 1 the binary translation method shown.

[0172] The embodiment of the present application further provides a chip, the chip includes a processor and a communication interface, the communication interface and the processor are coupled, the processor is used for running a program or instructions, realizes various processes of the binary translation method embodiment and can achieve the same technical effects, to avoid repetition, here will not repeat.

[0173] It should be understood that the chip mentioned in the embodiment of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0174] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0175] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can be realized wholly or partially by software, hardware, firmware, or any combination thereof. When realized by software, the embodiments of the present application can be realized wholly or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer instructions wholly or partially produce the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. that includes one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0176] The embodiments of the present application are described with reference to flowcharts and / or block diagrams of the method, terminal device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices produce the functions described in the flowcharts and / or block diagrams. Figure 1 The functions described in a flow or multiple flows and / or blocks Figure 1 The functions described in a flow or multiple flows and / or blocks

[0177] These computer program instructions can also be stored in a computer-readable memory that can cause the computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction devices that implement the functions described in the flowcharts and / or block diagrams. Figure 1 The functions described in a flow or multiple flows and / or blocks Figure 1 The functions described in a flow or multiple flows and / or blocks

[0178] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate a computer-implemented process, so that the instructions executed on the computer or other programmable terminal devices provide a process for implementing the functions specified in the flowchart Figure 1 one flow or multiple flows and / or blocks Figure 1 Figure 1 one block or multiple blocks.

[0179] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they get the basic inventive concept. Therefore, the appended claims are intended to cover all the preferred embodiments and all the changes and modifications falling within the scope of the embodiments of the present application.

[0180] Each of the embodiments in the specification is described in a relevant manner, and the same or similar parts between each of the embodiments can be referred to each other, and each of the embodiments focuses on the difference from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0181] It should be noted that the acquisition of various data related processes in the embodiments of the present application is performed under the premise of complying with the corresponding data protection regulations and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0182] Finally, it should be noted that in this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or terminal device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or terminal device including the element.

[0183] The binary translation method, device, electronic equipment and readable storage medium provided by the present application are described in detail above, the principles and implementation manners of the present application are described by applying specific examples in this paper, and the above example description is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above description should not be understood as a limitation on the present application.

Claims

1. A binary translation method, characterized by, The method comprises: adding a first instruction sequence in the first sequence after translating the block to be processed to obtain a first sequence; the first instruction sequence is used to write the client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the block to be processed is a basic block to be translated which contains a function call instruction; the jump block is a basic block in which the next client instruction of the function call instruction is located; translating the jump block to obtain the host virtual address of the jump block, and adding a second instruction sequence in the first instruction sequence of the block to be processed corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; if the client instruction to be translated is a return instruction, translating the return instruction to obtain a second sequence, and adding a third instruction sequence in the second sequence; the third instruction sequence is used to obtain the record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address; in the case that any basic block is updated to an invalid state, obtaining a precedent basic block of the basic block; the precedent basic block is a basic block in which the last instruction of the basic block is located; if the precedent basic block contains a function call instruction, replacing the first instruction sequence in the first sequence corresponding to the precedent basic block with a null operation instruction.

2. The method of claim 1, wherein, The first instruction sequence contains at least a to-be-replaced instruction sequence, and the to-be-replaced instruction sequence contains at least a self-jump instruction; the adding of the second instruction sequence in the first instruction sequence of the block to be processed corresponding to the jump block comprises: replacing the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence.

3. The method of claim 2, wherein, After the adding of the first instruction sequence in the first sequence, the method further comprises: adding a to-be-modified mark to the first sequence; After the replacing of the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence, the method further comprises: clearing the to-be-modified mark of the first sequence; Before the execution of any first sequence, the method further comprises: in the case that the first sequence contains the to-be-modified mark, modifying the self-jump instruction in the first sequence into a null operation instruction; or, in the case that the first sequence does not contain the to-be-modified mark, executing the first sequence.

4. The method of claim 1, wherein, After the adding of the second instruction sequence in the first instruction sequence of the block to be processed corresponding to the jump block, the method further comprises: if the jump block contains a function call instruction, taking the jump block as a new block to be processed, taking a basic block in which the next client instruction of the function call instruction of the jump block is located as a jump block corresponding to the new block to be processed, and performing the operation of translating the jump block to obtain the host virtual address of the jump block again until the current jump block does not contain a function call instruction.

5. The method of claim 1, wherein, The method further comprises: configuring a first parameter for each basic block; After translating any of the basic blocks, in a case where there is a function call instruction in a precedent basic block of the basic block, a parameter value of a first parameter of the basic block is obtained as a first determination value; If the first determination value is an initial value, the parameter value of the first parameter is updated as a basic block pointer of the precedent basic block; The obtaining the precedent basic block of the basic block comprises: obtaining the precedent basic block based on the parameter value of the first parameter of the basic block.

6. The method of claim 5, wherein, The method further comprises: configuring a second parameter for each of the basic blocks; After translating any of the basic blocks, in a case where there is a same function call instruction between the basic block and another basic block which has been translated, a parameter value of a second parameter of the another basic block is obtained as a second determination value; If the second determination value is an initial value, the parameter value of the second parameter of the another basic block is updated as a basic block pointer of the basic block; The obtaining the precedent basic block of the basic block based on the parameter value of the first parameter of the basic block comprises: obtaining a first precedent basic block of the basic block based on the parameter value of the first parameter of the basic block; taking the first precedent basic block as an initial basic block, obtaining a linking basic block of the initial basic block based on a parameter value of a second parameter of the initial basic block; taking the linking basic block as a new initial basic block, and performing again the operation of obtaining the linking basic block of the initial basic block based on the parameter value of the second parameter of the initial basic block; determining the first precedent basic block and the obtained linking basic block as the precedent basic blocks of the basic block.

7. The method according to any one of claims 1 to 6, characterized in that, The method further comprises: clearing the stored data in the address record stack in a case where the translation lookaside buffer is refreshed, or the stored data of the address record stack reaches a preset storage threshold.

8. A binary translation apparatus, characterized by, The apparatus comprises: a first adding module, configured to add a first instruction sequence in a first sequence obtained by translating a to-be-processed block; the first instruction sequence is used for writing a client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the to-be-processed block is a basic block to be translated which has the function call instruction; the jump block is a basic block in which a next client instruction of the function call instruction is located; a first translating module, configured to translate the jump block to obtain a host virtual address of the jump block, and add a second instruction sequence in a first instruction sequence of a to-be-processed block corresponding to the jump block; the second instruction sequence is used for writing the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; a second translating module, configured to, if a to-be-translated client instruction is a return instruction, translate the return instruction to obtain a second sequence, and add a third instruction sequence in the second sequence; the third instruction sequence is used for obtaining a record address corresponding to a return address of the return instruction from the address record stack as a target address, and jumping to the target address; The first obtaining module is configured to, in the case that any basic block is updated to an invalid state, obtain a precedent basic block of the basic block; the precedent basic block is a basic block in which a previous instruction of the basic block is located; The second replacing module is configured to, if the precedent basic block has a function call instruction, replace a first instruction sequence in a first sequence corresponding to the precedent basic block with a null operation instruction.

9. An electronic device, comprising: The computer device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is configured to store a computer program. The processor is configured to execute the program stored in the memory, and implement the method in any one of claims 1-7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the method in any one of claims 1-7.

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