Adaptive method and device based on Warp scheduling and cache replacement, and medium

Abstract

The invention relates to the technical field of computers, in particular to an adaptive method and device based on Warp scheduling and cache replacement and a medium. The method comprises the following steps: dynamically monitoring an access behavior of a Warp in an L1 data cache through a locality sensing unit, and identifying locality preference of a workload; according to the locality preference, adaptively selecting a Warp scheduling algorithm; periodically collecting cache access count and cache missing count through a cache state monitor, calculating the memory access missing rate of the current sampling period, and comparing the memory access missing rate with the missing rate of the previous sampling period; if the memory access missing rate of the current sampling period is higher than that of the previous sampling period, switching a cache replacement strategy; if not, the current strategy is kept. According to the method, the Warp scheduling algorithm and the cache replacement strategy are adaptively adjusted, so that the cache utilization rate and the performance of the GPGPU are optimized.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more particularly to an adaptive method, device, and medium based on Warp scheduling and cache replacement. Background Art

[0002] At present, general-purpose graphics processing units (GPGPUs) have become the core accelerators in the field of high-performance computing due to their high cost-effectiveness and large-scale parallel computing capabilities. Compared with traditional CPUs, GPGPUs not only have significant advantages in computing density and energy efficiency, but also have become the key hardware platform supporting exascale computing due to the architectural characteristics of massive computing cores. However, the optimization of its on-chip storage system still faces major challenges, especially the coordinated optimization of Warp scheduling and cache management in dynamic load scenarios, which needs to be broken through.

[0003] The current Warp schedulers (such as GTO and LRR) used by GPGPU generally adopt a static single strategy, which is difficult to adapt to the local characteristics of different programs, resulting in low on-chip cache utilization and limited performance. In GPGPU, the main task of the Warp scheduler is to allocate instructions in a group of threads to available execution units for scheduling and execution according to a specific algorithm to reduce memory access latency and complete tasks in a shorter time. However, the static single scheduling method has some limitations. In GPGPU programs, the uncertainty of memory access patterns and the differences in thread execution add great difficulty to Warp scheduling. Static Warp schedulers are difficult to predict program behavior, and it is difficult to improve program performance by scheduling so that the cache can effectively capture the locality in the program. A single scheduling optimization method usually only optimizes a specific problem in GPGPU. Although it can achieve good results in some programs, not all programs have the same performance bottleneck. Therefore, this single scheduling optimization method is difficult to adapt to the memory access and computing characteristics of different programs on GPGPU at the same time, and it is difficult to obtain good results in programs with different workloads.

[0004] In addition, GPGPU performance optimization does not only depend on program data locality, Warp scheduling and cache strategy, but also on the cache replacement method, which has an important impact on its memory access efficiency. Using different cache management methods will result in different performance of the same program. Static and single cache management also has similar limitations. The core goal of GPGPU cache management is to achieve the lowest cache miss rate within limited capacity through a suitable replacement algorithm, and to retain as much data locality in the cache as possible. However, static cache replacement algorithms (such as LRU and LFU) use a fixed replacement method, which makes it difficult to cope with changes in cache hit rates under different modes. Specifically, the LRU algorithm is based on the principle of least recently used, which may cause some frequently accessed but long interval data to be replaced prematurely. The LFU algorithm is based on access frequency, but when faced with burst access patterns, it may not be able to adjust the replacement strategy in time. This makes it difficult for the cache to effectively capture data locality in the program, and performance improvement is difficult to achieve.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The disclosed embodiments provide an adaptive method, device, and medium based on Warp scheduling and cache replacement, which dynamically perceives the data locality characteristics of a program, combines a locality perception unit and a cache status monitor, and adaptively adjusts the Warp scheduling algorithm and cache replacement strategy to optimize the cache utilization and performance of a GPGPU.

[0008] In some embodiments, the method comprises: Dynamically monitor the access behavior of Warps in the L1 data cache through a locality awareness unit to identify the locality preference of the workload, where the locality preference includes intra-Warp locality and inter-Warp locality. Adaptively select a Warp scheduling algorithm based on the locality preference: if the locality preference is intra-Warp locality, use the GTO algorithm for scheduling; if the locality preference is inter-Warp locality, use the LRR algorithm for scheduling; The cache status monitor periodically collects cache access counts and cache miss counts, calculates the memory miss rate of the current sampling cycle, and compares it with the miss rate of the previous sampling cycle; If the memory miss rate of the current sampling cycle is higher than that of the previous sampling cycle, the cache replacement strategy is switched; if it is lower than or equal to it, the current strategy is maintained and the miss rate of the previous sampling cycle is updated; Repeat the above steps until the program is finished.

[0009] Preferably, the locality sensing unit includes a plurality of entries, each entry corresponding to access information of a sample cache line in the L1 data cache; Each entry includes: a flag bit, a hit counter within a warp, a hit counter between warps, and three history bits. The flag bit indicates the locality type of the cache line. The hit counter within the warp records the number of re-hit times within the same warp. The hit counter between warps records the number of re-hit times between different warps. The history bit stores the warp ID that most recently accessed the cache line. The data cache is composed of a plurality of cache sets, each cache set containing cache lines of the same size; When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when the cache misses, a new entry is added and the current WarpID is recorded.

[0010] Preferably, when a memory access request occurs, the locality perception unit updates the corresponding hit counter according to the matching relationship between the current WarpID and the historical access set; when the cache misses, a new entry is added and the current WarpID is recorded, specifically in the following manner: When a memory access request occurs, the target cache tag and the current WarpID are extracted. If the target cache tag is already included in the cache set, the locality awareness unit will look up the entry corresponding to the target cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set; if the WarpID of the current memory access request is included in the historical access set, the locality awareness unit increases the corresponding Warp internal hit count bit; if the historical access set does not contain the current WarpID, the locality awareness unit will increase the corresponding Warp inter-hit count bit and add the current WarpID to the historical access set; if the current historical access set is full, the locality awareness unit updates the historical access set using a first-in-first-out method; if the cache tag is not in the cache set, the locality awareness unit fills the cache tag and the current WarpID into a new entry and clears the historical access set.

[0011] Preferably, the local preference is determined by: At the end of the sampling period, compare the intra-Warp hit counter of each entry with the inter-Warp hit counter; If the internal hit counter value of a warp is greater than the inter-warp hit counter value, it is determined to be intra-warp locality; otherwise, it is determined to be inter-warp locality.

[0012] Preferably, the switching of the cache replacement strategy includes: When the LRU algorithm is currently used, switch to the LFU algorithm; or when the LFU algorithm is currently used, switch to the LRU algorithm.

[0013] Preferably, the cache status monitor includes: GPGPU memory access counter, used to accumulate the number of cache accesses within the sampling period; GPGPU memory miss counter, used to accumulate the number of cache misses within the sampling period; The previous sampling cycle missing rate register is used to store historical missing rate data.

[0014] Preferably, when the sampling period ends, the locality sensing unit, the GPGPU memory access counter and the GPGPU memory access miss counter are cleared and reset.

[0015] Preferably, the LAU samples only one cache set in the L1 data cache to approximately characterize the overall cache behavior.

[0016] In some embodiments, the device includes a processor and a memory storing program instructions, and the processor is configured to execute the adaptive method based on Warp scheduling and cache replacement when running the program instructions.

[0017] In some embodiments, the storage medium stores a computer program thereon, and when the program is executed by the processor, the adaptive method based on Warp scheduling and cache replacement is implemented.

[0018] The embodiments of the present disclosure provide an adaptive method, device, and medium based on Warp scheduling and cache replacement, which can achieve the following technical effects: The locality awareness unit (LAU) monitors the cache access mode of the Warp in real time, intelligently identifies the data locality characteristics of the program (Intra-Warp / Inter-Warp), and realizes the dynamic switching of the scheduling strategy (GTO / LRR). Combined with the periodic detection of the memory miss rate by the cache status monitor, the cache replacement strategy (LRU / LFU) is dynamically adjusted to form a dual adaptive mechanism. This effectively solves the problem that traditional static strategies cannot adapt to dynamic workloads, and keeps the system performance in the optimal state under different program characteristics.

[0019] Based on the accurate judgment of the Warp locality type, GTO scheduling is used to strengthen the access association within the Warp, or LRR scheduling is used to promote data reuse between Warps. Through the dynamic selection of LFU / LRU replacement strategy, a balance is achieved between burst access and regular access modes to improve cache line reuse efficiency.

[0020] The core value of this invention lies in breaking through the limitations of the split optimization of scheduling and cache management in the traditional GPGPU architecture. By building an intelligent decision-making system with closed-loop feedback, it significantly improves the performance stability and resource utilization efficiency of heterogeneous computing platforms under complex workloads.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein: Figure 1 It is a schematic flow chart of the method of the present invention; Figure 2 It is a logical schematic diagram of the method of the present invention; Figure 3 It is a schematic diagram of the LAU local sensing unit architecture; Figure 4 It is a schematic diagram of the structure of the device of the present invention. DETAILED DESCRIPTION

[0023] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0024] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0025] Unless otherwise stated, the term "plurality" means two or more.

[0026] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0027] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0028] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0029] like Figure 1-Figure 2 ,An adaptive method based on Warp scheduling and cache replacement dynamically perceives the data locality characteristics of the program, combines the locality awareness unit (LAU) and the cache status monitor, and adaptively adjusts the Warp scheduling algorithm (GTO or LRR) and the cache replacement strategy (LRU or LFU) to optimize the cache utilization and performance of GPGPU.

[0030] In some embodiments, the method comprises: S1: Dynamically monitor the access behavior of Warps in the L1 data cache through the locality awareness unit to identify the locality preference of the workload, where the locality preference includes intra-Warp locality and inter-Warp locality.

[0031] The locality-aware unit dynamically monitors the access behavior of Warps, and can identify the intra-Warp / inter-Warp locality characteristics of the workload in real time. Based on this characteristic, the scheduling algorithm (GTO or LRR) is adaptively selected, which can effectively reduce the cache line contention problem caused by the mismatch between the scheduling strategy and the load characteristics.

[0032] As a refinement of the above embodiment, the locality awareness unit includes a plurality of entries, each entry corresponding to access information of a sample cache line in the L1 data cache; Each entry includes: a flag bit, a hit counter within a warp, a hit counter between warps, and three history bits. The flag bit indicates the locality type of the cache line. The hit counter within the warp records the number of re-hit times within the same warp. The hit counter between warps records the number of re-hit times between different warps. The history bit stores the warp ID that most recently accessed the cache line. The data cache is composed of a plurality of cache sets, each cache set containing cache lines of the same size; When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when the cache misses, a new entry is added and the current WarpID is recorded. The specific method is as follows: When a memory access request occurs, the target cache tag and the current WarpID are extracted. If the target cache tag is already included in the cache set, the locality awareness unit will look up the entry corresponding to the target cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set; if the WarpID of the current memory access request is included in the historical access set, the locality awareness unit increases the corresponding Warp internal hit count bit; if the historical access set does not contain the current WarpID, the locality awareness unit will increase the corresponding Warp inter-hit count bit and add the current WarpID to the historical access set; if the current historical access set is full, the locality awareness unit updates the historical access set using a first-in-first-out method; if the cache tag is not in the cache set, the locality awareness unit fills the cache tag and the current WarpID into a new entry and clears the historical access set.

[0033] The locality preference is determined by: At the end of the sampling period, compare the intra-Warp hit counter of each entry with the inter-Warp hit counter; If the internal hit counter value of a warp is greater than the inter-warp hit counter value, it is determined to be intra-warp locality; otherwise, it is determined to be inter-warp locality.

[0034] S2: Adaptively select a Warp scheduling algorithm based on the locality preference: if the locality preference is intra-Warp locality, use the GTO algorithm for scheduling; if it is inter-Warp locality, use the LRR algorithm for scheduling.

[0035] As a refinement of the above embodiment, the switching of the cache replacement strategy includes: When the LRU algorithm is currently used, switch to the LFU algorithm; or when the LFU algorithm is currently used, switch to the LRU algorithm.

[0036] S3: The cache access count and cache miss count are periodically collected through the cache status monitor, the memory access miss rate of the current sampling period is calculated, and the miss rate is compared with the miss rate of the previous sampling period.

[0037] As a refinement of the above embodiment, the cache status monitor includes: GPGPU memory access counter, used to accumulate the number of cache accesses within the sampling period; GPGPU memory miss counter, used to accumulate the number of cache misses within the sampling period; The previous sampling cycle missing rate register is used to store historical missing rate data.

[0038] S4: If the memory miss rate of the current sampling cycle is higher than that of the previous sampling cycle, the cache replacement strategy is switched; if it is lower than or equal to the previous sampling cycle, the current strategy is maintained and the miss rate of the previous sampling cycle is updated.

[0039] By periodically collecting cache access counts and miss rates and comparing them with historical data, dynamic feedback control of the cache replacement strategy is achieved.

[0040] S5: Repeat the above steps until the program runs to the end.

[0041] The sampling period reset mechanism ensures the system's ability to respond quickly to periodic load changes.

[0042] When the sampling period ends, the locality sensing unit, the GPGPU memory access counter and the GPGPU memory access miss counter are cleared and reset.

[0043] As a refinement of the above embodiment, a locality awareness unit (LAU) is used to monitor the behavior of Warp in the L1 data cache to identify the locality preference of the workload. LAU contains multiple entries to store L1 cache access information. When a Warp's load instruction is sent to the load / store (LD / ST) unit, a memory access request is generated, involving one or more memory transactions. The system first checks the L1 data cache, which consists of multiple cache sets, each of which contains cache lines of the same size. Each memory transaction is assigned to the corresponding cache set, and the cache tag is checked to determine whether it hits. If the tag matches, it is a cache hit; otherwise, it is a cache miss.

[0044] To save hardware overhead, this embodiment samples only one cache set to approximate the performance of the entire L1 cache. In the LAU, each entry corresponds to a cache line in the sampled cache set and contains the following information: a flag bit indicating the locality type of the cache line. Two counters, which record the number of re-hit (Intrahit) within the same Warp and the number of re-hit (Interhit) between different Warps. Three history bits constitute the Warp history record, which stores the WarpID of the previous access to the cache line.

[0045] When a memory access request occurs, if the cache tag is already included in the cache set, the LAU will look up the entry corresponding to the cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set. If the WarpID of the current memory access request is included in the historical access set, the LAU will increase the corresponding Warp internal hit count bit. If the historical access set does not contain the current WarpID, the LAU will increase the corresponding Warp inter-Warp hit count bit and add the current WarpID to the historical access set. If the current historical access set is full, the LAU updates the historical access set using a first-in, first-out method. If the cache tag is not in the cache set, the LAU fills the cache tag and the current WarpID into a new entry and clears the historical access set. In this way, the LAU can continue to collect access information for the intra-Warp locality and inter-Warp locality of each data cache line until the end of the predefined sampling period.

[0046] LAU divides the locality type of each entry into Intra-Warp Locality and Inter-Warp Locality. LAU determines the locality type of the cache line by comparing the accumulated hit count statistics of the Warp and the hit count statistics of the Warp corresponding to the cache entry collected through cache cycle sampling. If the counter Intra hit>Inter hit, it means that the workload exhibits strong intra-Warp locality, that is, different threads in the same Warp frequently access the same cache address, which means that multiple threads using the same Warp have a higher cache hit rate. In this case, the Warp scheduler will select the GTO algorithm for scheduling to further enhance the intra-Warp locality of the workload. If the counter Intra hit≤Inter hit, the workload exhibits inter-Warp locality, that is, threads between different Warps frequently access the same cache address, and the Warp scheduler will select the LRR algorithm for Warp scheduling, allowing all Warp launches to have the same priority.

[0047] In addition, we introduce a cache status monitor to detect the data cache status during the sampling period. The monitor consists of two counters: GPGPU memory access counter and GPGPU memory miss counters And the memory miss rate register of the previous sampling cycle The number of cache accesses and cache misses as well as the memory miss rate of the previous sampling cycle are recorded. During the sampling period, if a memory access request occurs on the GPGPU, then Add 1. If a cache request is detected to be missed while the GPGPU is making a cache request, a cache miss occurs and the counter Add 1. Based on the collected GPGPU memory access count information and memory access miss information, calculate the GPGPU memory access miss rate in this sampling period. The calculation formula is as follows: , The GPGPU memory miss rate information can reflect the cache utilization efficiency of the replacement strategy adopted by the GPGPU in the sampling period. Higher than the missing rate information of the previous sampling period , it means that the cache replacement strategy currently used may not be suitable for the current operating state, and a different replacement strategy is needed to increase the cache utilization efficiency of GPGPU and keep the miss rate information of the previous sampling cycle unchanged; if it is less than or equal to the miss rate information of the previous sampling cycle, keep the current strategy unchanged and update the miss rate information of the previous sampling cycle. The formula is as follows: , When entering the next sampling cycle, the local awareness unit LAU and two counters GPGPU memory access counter and GPGPU memory miss counters Perform zero reset and repeat the sampling cycle process until the program ends.

[0048] Combination Figure 4 As shown, the embodiment of the present disclosure provides an adaptive device 300 based on Warp scheduling and cache replacement, including a processor (processor) 304 and a memory (memory) 301. Optionally, the device may also include a communication interface (CommunicationInterface) 302 and a bus 303. Among them, the processor 304, the communication interface 302, and the memory 301 can communicate with each other through the bus 303. The communication interface 302 can be used for information transmission. The processor 304 can call the logic instructions in the memory 301 to execute the adaptive method based on Warp scheduling and cache replacement of the above embodiment.

[0049] In addition, the logic instructions in the memory 301 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0050] The memory 301, as a computer-readable storage medium, can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes the functional application and data processing by running the program instructions / modules stored in the memory 301, that is, the adaptive method based on Warp scheduling and cache replacement in the above embodiment is implemented.

[0051] The memory 301 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 301 may include a high-speed random access memory and may also include a non-volatile memory.

[0052] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned adaptive method based on Warp scheduling and cache replacement.

[0053] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

Claims

1. An adaptive method based on Warp scheduling and cache replacement, characterized in that: The following steps are involved: Dynamically monitor the access behavior of Warps in the L1 data cache through a locality awareness unit to identify the locality preference of the workload, where the locality preference includes intra-Warp locality and inter-Warp locality. Adaptively select a Warp scheduling algorithm based on the locality preference: if the locality preference is intra-Warp locality, use the GTO algorithm for scheduling; if the locality preference is inter-Warp locality, use the LRR algorithm for scheduling; The cache status monitor periodically collects cache access counts and cache miss counts, calculates the memory miss rate of the current sampling cycle, and compares it with the miss rate of the previous sampling cycle; If the memory miss rate in the current sampling cycle is higher than that in the previous sampling cycle, the cache replacement strategy is switched; If it is lower than or equal to, the current strategy is maintained and the missing rate of the previous sampling period is updated; Repeat the above steps until the program is finished.

2. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The locality sensing unit includes a plurality of entries, each entry corresponding to access information of a sample cache line in the L1 data cache; Each entry includes: a flag bit, a hit counter within a warp, a hit counter between warps, and three history bits. The flag bit indicates the locality type of the cache line. The hit counter within the warp records the number of re-hit times within the same warp. The hit counter between warps records the number of re-hit times between different warps. The history bit stores the warp ID that most recently accessed the cache line. The data cache is composed of a plurality of cache sets, each cache set containing cache lines of the same size; When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when the cache misses, a new entry is added and the current WarpID is recorded.

3. The adaptive method based on Warp scheduling and cache replacement according to claim 2, characterized in that: When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when the cache misses, a new entry is added and the current WarpID is recorded. The specific method is as follows: When a memory access request occurs, the target cache tag and the current WarpID are extracted. If the target cache tag is already included in the cache set, the locality awareness unit will look up the entry corresponding to the target cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set; if the WarpID of the current memory access request is included in the historical access set, the locality awareness unit increases the corresponding Warp internal hit count bit; if the historical access set does not contain the current WarpID, the locality awareness unit will increase the corresponding Warp inter-hit count bit and add the current WarpID to the historical access set; if the current historical access set is full, the locality awareness unit updates the historical access set using a first-in-first-out method; if the cache tag is not in the cache set, the locality awareness unit fills the cache tag and the current WarpID into a new entry and clears the historical access set.

4. The adaptive method based on Warp scheduling and cache replacement according to claim 2, characterized in that: The locality preference is determined by: At the end of the sampling period, compare the intra-Warp hit counter of each entry with the inter-Warp hit counter; If the internal hit counter value of a Warp is greater than the inter-Warp hit counter value, it is determined to be intra-Warp locality; Otherwise, it is determined to be inter-Warp locality.

5. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The switching of the cache replacement strategy includes: When the LRU algorithm is currently used, switch to the LFU algorithm; or when the LFU algorithm is currently used, switch to the LRU algorithm.

6. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The cache status monitor includes: GPGPU memory access counter, used to accumulate the number of cache accesses within the sampling period; GPGPU memory miss counter, used to accumulate the number of cache misses within the sampling period; The previous sampling cycle missing rate register is used to store historical missing rate data.

7. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: When the sampling period ends, the locality sensing unit, the GPGPU memory access counter and the GPGPU memory access miss counter are cleared and reset.

8. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The locality awareness unit samples only one cache set in the L1 data cache to approximately characterize the overall cache behavior.

9. An adaptive device based on Warp scheduling and cache replacement, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the adaptive method based on Warp scheduling and cache replacement as described in any one of claims 1-8 when running the program instructions.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the adaptive method based on Warp scheduling and cache replacement as described in any one of claims 1 to 8 above is implemented.

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