Apparatus and method for signal encryption in high bandwidth memory

Abstract

Embodiments of the invention relate to devices, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory HBM may include a hybrid of secure and unsecure circuits coupled to secure and unsecure registers, respectively. Information may be communicated between the secure and unsecure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, encryption circuitry in the HBM may first encrypt the information prior to writing it to the secure register. When information is read from the secure register, it may be first encrypted by encryption circuitry prior to being provided along the interface.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of September 14, 2020, application number 202010959587.4, and invention name “Device and method for signal encryption in high bandwidth memory”. Technical Field

[0003] The present invention relates generally to semiconductor devices, and more particularly, to semiconductor memory devices. Background Art

[0004] A memory device may include a variety of circuits that may be used to implement various functions of the memory. Some memory devices may be installed on a second device, such as a host device (e.g., a graphics card, a CPU, a computing system, etc.). Access to the circuits of the memory may typically be performed by the host device. For example, instructions for the operation of the circuits and data from those circuits may be passed along an interface bus that couples the memory device to the host device. Summary of the invention

[0005] In one aspect, the present application relates to an apparatus comprising: a high bandwidth memory (HBM) comprising a first register and a second register; a host device; an interface bus configured to couple information between the HBM and the host device, wherein a portion of the information is encrypted, and wherein the encrypted portion of the information is received from or provided to at least one of the first registers.

[0006] In another aspect, the present application relates to an apparatus comprising: a secure circuit including an input terminal coupled to an input bus; an unsecure circuit having an input terminal coupled to the input bus; a decryption circuit coupled to the input terminal of the secure circuit and the input bus, the decryption circuit being configured to decrypt input data provided along the input bus and to provide the decrypted input data to the secure circuit.

[0007] In another aspect, the present application relates to a device comprising: a secure circuit having an output terminal coupled to an output bus; an unsecure circuit having an output terminal coupled to the output bus; an encryption circuit positioned between the output terminal of the secure circuit and the output bus, the encryption circuit being configured to encrypt output information provided at the output terminal of the secure circuit and to provide the encrypted output information along the output bus.

[0008] In another aspect, the present application relates to an apparatus comprising: an interface bus; and a host device configured to provide encrypted information to the interface bus together with a selection signal in a first state, and further configured to provide unencrypted information to the interface bus together with the selection signal in a second state.

[0009] In another aspect, the present application relates to a method comprising: receiving information from a host device at a memory device; decrypting the information and storing the decrypted information in a first register of the memory device when a select signal is in a first state; and storing the information in a second register of the memory device when the select signal is in a second state. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a memory system according to an embodiment of the present invention.

[0011] Figure 2 is a cross-sectional view of a high bandwidth memory according to an embodiment of the present invention.

[0012] Figure 3 is a block diagram of a high bandwidth memory according to an embodiment of the present invention.

[0013] Figure 4 is a schematic diagram of a wrapper data register circuit according to an embodiment of the present invention.

[0014] Figure 5 is a timing diagram of the operation of a wrapper data register circuit according to an embodiment of the present invention.

[0015] Figure 6 is a schematic diagram of a wrapper data register circuit according to an embodiment of the present invention.

[0016] Figure 7 is a timing diagram of a write operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following description of specific embodiments is merely exemplary in nature and is by no means intended to limit the scope of the invention or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings that form a part of the detailed description and show by way of illustration specific embodiments of the described system and method in which they can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present invention. In addition, for the purpose of clarity, the detailed description will not be discussed when it is obvious to those skilled in the art so as not to obscure the description of embodiments of the present invention. Therefore, the following detailed description should not be viewed in a limiting sense, and the scope of the present invention is defined solely by the appended claims.

[0018] A memory device, such as a high bandwidth memory (HBM) device, may include a variety of internal circuits for performing functions. For example, a memory device may include a built-in self-test (BIST) circuit for testing the performance of the memory device (and / or measuring other properties). The memory device may be packaged onto a host device, and an interface bus may couple the memory device to the host device. Information, such as test instructions, may be provided by the host device to the memory device along the interface bus, and information, such as test results, may be received by the host device from the memory device along the interface bus. The memory device may include a secure circuit that may receive or provide information that is desired to be kept secure (e.g., details of the operation of the memory device, performance of specific components of the memory device, etc.). The memory device may also contain an unsecure circuit that may receive or provide information that may not need to be kept secure (e.g., because the information is based on publicly available specifications). The interface bus may thus carry a mix of secure information and unsecure information. However, since the information is coupled in and out of the memory device by the host device, it may be possible for the host device to monitor the information. Therefore, it may be desirable to protect the secure portion of the information along the interface bus.

[0019] The present invention relates to an apparatus, system and method for signal encryption in a high bandwidth memory. A portion of information along an interface bus between a host device and a memory device may be encrypted. The encrypted portion may be a portion of information associated with a secure circuit of the memory device. The memory device may include a register coupled to the interface bus, such as a wrapper data register (WDR). The WDR may include a secure WDR storing information associated with a secure circuit and an unsecure WDR storing information associated with an unsecure circuit. For example, the WDR may store instructions and / or data to be provided to and / or received from the circuit. The memory device may also include a cryptographic circuit. In some embodiments, the cryptographic circuit may include a decryption circuit, and as part of a write operation to the WDR, the decryption circuit may receive an encrypted portion of information along the interface bus, and then, decrypt the encrypted portion before it is stored in the secure WDR. In some embodiments, the cryptographic circuit may include an encryption circuit, and as part of a read operation from the WDR, the encryption circuit may receive information from the secure WDR, and then, encrypt the information before providing it along the interface bus. In some embodiments, the cryptographic circuit may include a decryption circuit and an encryption circuit.

[0020] Figure 1 1 is a block diagram of a memory system according to an embodiment of the present invention. The memory system includes a system in package (SiP) 101, which includes a memory device 100 and a host device 102. The memory device 100 is coupled to the host device 102 along an interface bus 116. The memory device 100 includes a wrapper data register (WDR) circuit 104. The WDR circuit 104 includes a secure WDR 110 coupled to a cryptographic circuit 108, an unsecure WDR 112, and a wrapper instruction register (WIR) 114. The secure WDR 110 and the unsecure WDR 112 receive and send information along the interface bus 116. The interface bus 116 includes an input bus WSI and an output bus WSO. One or more control signals may also be provided to the WIR 114 along the interface bus 116 to control whether the information along the interface is routed to the secure WDR 110 or the unsecure WDR 112 / from the secure WDR 110 or from the unsecure WDR 112.

[0021] Memory device 100 may provide memory storage for host device 102. For example, SiP 101 may be a computing device such as a motherboard or graphics card, the host device may be a processor (e.g., a CPU or GPU), and HBM may provide on-board memory used by SiP 101. Memory device 100 may be designed and / or manufactured by a first entity (e.g., a first company, a first organization, etc.), which may generally be referred to as a memory entity. Host device 102 may be designed and / or manufactured by a second entity (e.g., a second company), which may generally be referred to as a host entity. Information provided to and / or received from security circuit 106 may be encrypted outside of memory device 100, such that the encrypted information is not sensitive to the host organization but may be decrypted and understood by the memory organization.

[0022] For example, the memory entity may be the company that designed the memory device 100, while the host entity may be the company that packaged the memory device 100 and the host device 102 together into the SiP 101. In general, the term memory entity is used to refer to the entity that is allowed to access the unencrypted meaning of the information sent to / received from the secure circuit 106, while the host entity refers to the entity that is not allowed to have such access. For example, the secure circuit may refer to a test circuit, and the designer of the memory device 100 may want the details of the test circuit to be kept confidential from the host entity that is the customer of the memory device and that packages the memory device 100 onto the SiP 101. Therefore, the memory entity may want to keep the information sent to the test circuit (or the information provided by the test circuit) encrypted when the information is passed along the interface bus 116 in order to prevent the host entity from being able to decipher the content of the information.

[0023] It should be noted that for ease of reference, the terms memory entity and host entity are used, and that there may be many different relationships between the memory entity and the host entity. For example, in some embodiments, the memory entity may be a supplier that sells memory devices to the host entity (thus, it is a customer). In some embodiments, the memory and host entities may represent different parts of an organization (e.g., different departments, different facilities, etc.). In some embodiments, the memory entity and the host entity may each represent multiple different entities. For example, the host entity may include an entity that designs the host device 102, an entity that manufactures the host device 102, an entity that packages the host device 102 and the memory device 100 into the SiP 101, etc.

[0024] The WDR circuit 104 may include several registers, such as a secure WDR 110, an unsecure WDR 112, and a WIR 114. The registers may store information (e.g., in one or more latch circuits). The control signals may be used, in part, to control to which register the information along the interface bus 116 is sent or from which register the information is received. In some embodiments, the control signals may cause the information along the input bus WSI to be written to the WIR 114, and the state of the information stored in the WIR 114 may determine whether subsequent information along the interface bus 116 is stored in the secure WDR 110 or in the unsecure WDR 112 as part of a write operation. The state of the information stored in the WIR 114 may also determine whether the information is read from the secure WDR 110 or from the unsecure WDR 112 as part of a read operation.

[0025] The two WDR circuits 110 and 112 may store information associated with the secure circuit 106 and the unsecure circuit 107, respectively. The secure circuit 106 and the unsecure circuit 107 may be able to access the information in their respective WDRs 110 and 112. For example, the circuits 106 and 107 may be able to read the information in their respective WDRs 112 or 114, and may be able to write new information to their respective WDRs 112 or 114.

[0026] The cryptographic circuit 108 may include a decryption circuit and / or an encryption circuit. The decryption circuit may receive encrypted information along the input bus WSI and then decrypt the information before it is stored in the secure WDR 110. Therefore, the encrypted information sent to the secure WDR 110 may be stored in the secure WDR 110 as unencrypted information. The encryption circuit may receive unencrypted information stored in the secure WDR 110 and encrypt it before providing the information along the output bus WSO. Therefore, if the cryptographic circuit 108 includes both encryption and decryption circuits, the information provided to and received from the secure WDR 110 may be encrypted outside the WDR circuit 104.

[0027] In an example operation where the secure circuit 106 is a test circuit for the memory device 100, instructions for the operation of the test may be received along the input bus WSI, decoded by the decryption circuit of the cryptographic circuit 108, and then written to the secure WDR 110. The secure circuit 106 may then read the information from the secure WDR 110 and use the information to perform a test on the memory device 100. After the test is performed, the secure circuit 106 may write the information (e.g., the results of the test) back to the secure WDR 110. The information may then be read from the secure WDR 110, encrypted by the encryption circuit of the cryptographic circuit 108, and then provided along the output bus WSO. Information may also be written to the unsecure WDR 112, used by the unsecure circuit 107, and then read from the unsecure WDR 112 in a similar manner, but without being decrypted / encrypted. In this manner, information along the interface bus 116 may be used to operate the secure circuit 106 and the unsecure circuit 107 , and information from the secure circuit 106 and the unsecure circuit 107 may be read out along the interface bus 116 .

[0028] The interface controller 118 of the host device 102 may control the flow of information along the interface bus 116. In some embodiments, the interface bus 116 may be an IEEE 1500 interface, and the interface controller 118 may be an IEEE 1500 controller. The interface controller 118 may provide input information (e.g., a value to be written to the WDR circuit 104) along the input bus WSI, receive information from the WDR circuit 108 along the output bus WSO, and provide one or more control signals. The control signal may include a clock signal that controls the timing of writing information to the WDR circuit 104 or reading information from the WDR circuit 104. The control signal may include a selection signal that determines whether to write information to (or read information from) the secure WDR 110, the unsecure WDR 112, and / or the WIR 114. In some embodiments, there may be a separate selection signal for each of the secure WDR 110, the unsecure WDR 112, and the WIR 114. In some embodiments, there may be a single select signal provided along the interface bus 116 for the WIR 114 , and the select signals for the secure WDR 110 and the unsecure WDR 112 may be generated internally to the WDR circuit 104 based on the state of the WIR 114 .

[0029] In some embodiments where the cryptographic circuit 108 includes a decryption circuit, when the interface controller 118 writes information to the secure WDR 110, one or more of the control signals may activate the cryptographic circuit 108. The activated cryptographic circuit 108 may receive information along the input bus WSI, and may decrypt the received information, and then provide the decrypted information to the secure WDR 110. For example, the write information may be a test instruction. When the interface controller 118 writes information to the unsecure 112, the cryptographic circuit 108 may remain inactive, and the information along the input bus WSI may be written to the unsecure WDR 112 as is.

[0030] The information stored in the secure WDR 110 can be read by the secure circuit 106, which can perform one or more functions based on the state of the information in the secure WDR. For example, in some embodiments, the secure WDR can store information that can be interpreted by the secure circuit 106. Then, the secure circuit 106 can write the information to the secure WDR 110. For example, the result can be written to the secure WDR 110. In some embodiments, the result can overwrite the instruction previously stored in the secure WDR 110. In some embodiments, there can be separate input and output areas for the secure WDR 110. The unsecure WDR 112 can be read by the unsecure circuit 107 in a manner generally similar to the secure WDR 110 (and written to the unsecure circuit 107 in the manner described).

[0031] In some embodiments where the cryptographic circuit 108 includes encryption circuitry, when the interface controller 118 indicates that information should be read from the secure WDR 110 (e.g., by providing an appropriate signal to the WIR 114), the cryptographic circuit 108 may be activated and may receive information from the secure WDR 110 and then encrypt the information before providing it along the output bus WSO. When the interface controller 118 indicates that information should be read from the unsecure WDR 112, the cryptographic circuit 108 may remain inactive and the information may be read directly from the unsecure WDR 112 to the output bus WSO.

[0032] In some embodiments, the host device 102 may be coupled to the external device 120 along the second interface bus 121. In some embodiments, the second interface bus 121 may be a JTAG interface. In some embodiments, information written to or read from the WDR circuit 104 may be received / sent from the external device 120 to the external device 120. The external device 120 may operate the secure circuit 106 and / or the unsecure circuit 107 in the memory device 100 along the second interface bus 121 and the interface bus 116 through the host device 102. For example, if the SiP 101 is a graphics card or a motherboard, the external device 120 may be a computer coupled to the SiP 101, such as a personal computer. In some embodiments, the external device 120 may be a tester unit for performing one or more tests on the memory device 100. In this embodiment, one or more of the secure circuits 106 may be a built-in self-test (BIST) circuit that may be operated by the external device 120. In some embodiments, the external device 120 may be a separate device coupled to the host device 102. In some embodiments, external device 120 is integral with SiP 101. In some embodiments, external device 120 (and second interface 121) may be omitted, and host device 102 may directly perform the functions attributed to external device 120. For example, in some embodiments, host device 102 may operate the BIST circuit itself.

[0033] The external device 120 may store information 122 provided to and / or received from the secure circuit 106 and the unsecure circuit 107 in the memory device 100. The information 122 may include a mix of decrypted information 124 and unencrypted information 126. The encrypted information 124 may include information for operating the secure circuit 106 in the memory device 100 (e.g., control information for operating a test circuit, test data to be written to one or more memory cells, etc.). The encrypted information 124 may also include information received from the secure circuit 106 (e.g., a result file of result data from the test circuit, test data read from one or more memory cells, etc.). The unencrypted information 126 may include information sent to and / or received from the unsecure circuit 107 of the memory device 100. The encrypted information 124 may be encrypted so that the meaning of the encrypted information 124 cannot be extracted without knowing how the encrypted information was encrypted. If encrypted information is being written to the secure WDR 110, the information may be pre-encrypted (e.g., pre-encrypted by the memory organization) before being provided to the external device 120, and then decrypted by the cryptographic circuit 108 when it is written to the secure WDR 110. If encrypted information is received from the secure WDR 110, the information may be encrypted by the cryptographic circuit 108.

[0034] Figure 2is a cross-sectional view of a high bandwidth memory according to an embodiment of the present invention. In some embodiments, Figure 2 The high bandwidth memory (HBM) 200 may be included in Figure 1 In the memory device 100. Figure 2 The HBM 200 is an HBM having a structure in which eight memory core chips 220 to 227 are stacked one above the other on the interface chip 210. However, the embodiments of the present invention are not limited to HBM, and memories (or other semiconductor devices) of other structures may be used in other embodiments. The memory core chips 220 to 227 are semiconductor chips, each of which integrates a memory core including a memory cell array. The interface chip 210 is a semiconductor chip that controls the memory core chips 220 to 227.

[0035] The interface chip 210 may be coupled to a host device (e.g., host device 102) along an interposer that contains one or more channels used as a bus between the host device and the memory device (e.g., interface bus 116). The interface chip 210 may receive information from the interface bus at one or more external terminals 233, and then the interface chip 210 may distribute the received information to one or more of the memory core chips 220 to 227. Similarly, the interface chip 210 may receive information from the memory core chips 220 to 227, and then provide the information at an external terminal (e.g., along an interface such as interface bus 116). Figure 1 The WDR circuit (and secure and unsecure circuits) may be located in the interface chip 210 .

[0036] Each of the interface chip 210 and the memory core chips 220 to 227 includes a plurality of TSVs 230 penetrating the corresponding semiconductor substrate. The interface chip 210 and the memory core chips 220 to 227 are all stacked by a face-down method, that is, in this way, the main surface on which the transistors and wiring patterns (all not shown) are formed faces downward. Therefore, the memory core chip 227 positioned in the topmost layer does not need TSVs 230. However, in some embodiments of the present invention, the memory core chip 227 positioned in the topmost layer may include TSVs 230. Most of the TSVs 230 provided on the memory core chips 220 to 227 are respectively connected to the front TSV pads 231A positioned at the same plane position. In contrast, most of the TSVs 230 provided on the interface chip 210 and the front TSV pads 231A provided on the interface chip 210 are positioned at different plane positions. TSVs 230 located at the same plane position among TSVs 230 provided on the interface chip 210 and the memory core chips 220 to 227 are cascade-connected via front TSV pads 231A, TSV bumps 231B, and back TSV pads 231C, respectively, so that a plurality of signal paths 232 are formed. Commands and write information output from the interface chip 210 are supplied to the memory core chips 220 to 227 via the signal paths 232. Read information output from the memory core chips 220 to 227 is supplied to the interface chip 210 via the signal paths 232. External terminals 233 are provided on the interface chip 210, and signal transmission / reception to / from an external circuit is performed via the external terminals 233.

[0037] Figure 3 is a block diagram of a high bandwidth memory according to an embodiment of the present invention. In some embodiments, Figure 3 The high bandwidth memory 300 may be included in Figure 1 High bandwidth memory 100 and / or Figure 2 in the high bandwidth memory 200. Figure 3 An example is shown of how standard memory operations may be performed between the interface chip 310 and one or more core chips 320 to 327. For clarity of illustration, Figure 3 WDR circuits are not shown (e.g., Figure 1 WDR circuit 104). The WDR circuit and its operation are Figures 4 to 7 Discussed in more detail in .

[0038] like Figure 3, the interface chip 310 includes a row decoder 311 and a delay counter 312. The row decoder 311 receives the command address signal RCA and the clock signal CLK and generates the address signal ADD and the internal command. One type of internal command is an effective command ACT. The effective command ACT is supplied to the memory core chips 320 to 327 via TSV 330, and is also supplied to the delay counter 312. The address signal ADD is also supplied to the memory core chips 320 to 327 via TSV 330. The delay counter 312 receives the effective command ACT and the clock signal CLK. The delay counter 312 generates the internal command ACTIMP after a predetermined cycle of the clock signal CLK from the activation of the effective command ACT. The internal command ACTIMP is supplied to the memory core chips 320 to 327 via different TSVs 330.

[0039] Each of the memory core chips 320 to 327 includes an action control circuit 340, an address latch circuit 341, an address decoder 342, and a memory cell array 343. The action control circuit 340 receives an active command ACT and an internal command ACTIMP and generates a state signal RActBk. The state signal RActBk is a signal indicating the state of the memory cell array 343. For example, the state signal RActBk is at a high level when the memory cell array 343 is in an action state, and is at a low level when the memory cell array 343 is in an inactive state (precharge state). The state signal RActBk is supplied to the address decoder 342 together with the address signal ADD latched by the address latch circuit 341. The address decoder 342 decodes the address signal ADD and performs row access to the memory cell array 343. The memory cell array 343 can be divided into a plurality of memory banks. In this case, the action control circuit 340 is allocated to each of the memory banks.

[0040] In the example operation, Figure 1The WDR circuit 104 of the HBM device 300 together with the security circuit 106 and the unsafe circuit 107 can be located in the interface die 310 of the HBM device 300. The security circuit 106 can be a built-in self-test (BIST) circuit and can be used to test one or more memory cells in the memory cell array 343. The interface bus that couples the host device (e.g., a processor) to the HBM device 300 can be an IEEE 1500 interface bus. The host device can provide test instructions (e.g., address information ADD of the memory cell to be tested) and test data, a data sequence to be written to the specified memory cell. The provided test instructions and test data can be encrypted. The host device can provide a selection signal indicating that the test instructions and data are encrypted and should be written to the secure WDR. The cryptographic circuit located in the interface die 310 can receive the encrypted information, decrypt it, and store it in the secure WDR. The BIST circuit can access the test instructions and provide the test data to the memory cells of the memory array 343 in one or more of the core chips 320 to 327 based on the test instructions. The BIST circuit may then read the test data from the memory cells and compare the read test data to the write test data. The BIST circuit may then write the result information to the secure WDR. The host device may retrieve the result information by sending a select signal to the interface die 310. The cryptographic circuit may encrypt the result information and then provide the result information to the host device along the interface bus.

[0041] Figure 4 4 is a schematic diagram of a WDR circuit according to an embodiment of the present invention. In some embodiments, the WDR circuit 400 may be included in Figure 1 The WDR circuit 400 includes a secure WDR 410 (labeled as Sec_WDR herein) and an unsecure WDR 412 (labeled as NonSec_WDR herein). In some embodiments, these WDRs may be included in Figure 1 In some embodiments, the WDR circuit 400 includes a secure WDR 110 and an unsecure WDR 112. Figure 1 of WIR 114 in WIR 414.

[0042] exist Figure 4 In a particular embodiment of the invention, the WDR circuit 400 includes a cryptographic circuit 408. In particular, the cryptographic circuit 408 is a decryption circuit including a random number generator 450 and an exclusive OR (EOR) gate 451. The random number generator 450 and the EOR gate 451 are used to receive encrypted information along the input bus WSI and decrypt the encrypted information before writing it to the secure WDR 410 as a signal received by a host device (e.g., Figure 1 102) performs a portion of a write operation to the secure WDR 410.

[0043] The WDR circuit 400 is along (eg, Figure 1 The interface bus 116 of the WDR circuit 400 is coupled to the host device, and the bus includes an input bus WSI, an output bus WSO, and a number of control signals, such as SelectWIR, ShiftWR, and WRCLK. The signal SelectWIR can be used to activate WIR 414 so that information along the input bus WSI can be written to WIR 414 and / or so that information in WIR 414 is written to the output bus WSO. The signal ShiftWR controls the loading and / or unloading of information bits into registers (such as secure WDR 410, unsecure WDR 412, and WIR 414). The signal WRCLK can be a clock signal that controls the timing of handling information in the WDR circuit 400.

[0044] In an example embodiment of the WDR circuit 400, signals (e.g., SelectWIR and ShiftWR) are generally considered to be 'valid' when they are at a high logic level, and are generally considered to be ineffective when they are at a low logic level. Signals or buses (e.g., WSI, WSO) carrying binary data can generally use a high logic level to represent a binary signal 1 and a low logic level to represent a binary signal 0. The clock signal WRCLK may have a rising edge (where a low logic level transitions to a high logic level) or a falling edge (where a high logic level falls to a low logic level). In some embodiments, one type of edge (e.g., a rising edge) can be used to control the timing of a write operation, while another type of edge (e.g., a falling edge) can be used to control the timing of a read operation. In general, the WDR circuit 400 can use a first voltage (e.g., a ground voltage) to represent a low logic level, and a second voltage (e.g., a system voltage higher than the ground voltage) to represent a high logic level. It should be understood that in other embodiments, other waveforms can be used to mark the activation of a signal, and other systems can be used to distinguish the logic levels of a signal.

[0045] In some embodiments of the present invention, WIR 414, secure WDR 410, and unsecure WDR 412 may all be shift registers. Each may include several latch circuits coupled in series with each other. Each of the latch circuits is capable of storing a logic state representing a stored bit. In some embodiments, the shift register may operate in a first-in, first-out (FIFO) manner. For example, during a write operation to the shift register, the shift register may be activated (e.g., by a signal from WIR 414, as discussed herein). Whenever a rising edge of a clock signal WRCLK is received, the activated shift register may shift the value in each latch circuit to the next latch circuit in series, and the current logic level on the input bus WSI may be stored in the first latch circuit. When reading the shift register, in response to each falling edge of the clock signal WRCLK, the value stored in the last latch circuit may be used to set the state of the output bus WSO, and may be removed from the latch circuit. Each value may then be shifted to the next latch circuit so that the value in the second to last circuit is loaded into the last latch circuit, and so on.

[0046] WIR 414 can be used to store information that can be used to control whether the unsecure WDR 412 or the secure WDR 410 (and the random number generator 450) is active. WIR 414 has a clock terminal coupled to the output terminal of AND gate 455. AND gate 455 has input terminals coupled to signals SelectWIR, ShiftWR, and WRCLK. WIR 414 has an input terminal coupled to the input bus WSI. Therefore, when both SelectWIR and ShiftWR are valid, AND gate 455 can pass clock signal WRCLK to the clock terminal of WIR 414, which in turn can cause WIR to load the current state of input bus WSI. The state of the bit stored in WIR 414 can be used to generate a signal to activate secure WDR 410 and unsecure WDR 412.

[0047] WIR 414 may be coupled to WIR decoder circuit 415. WIR decoder circuit 415 reads the state of the bit stored in WIR 414 and provides selector signals SEC_WDRSel and NonSec_WDRSel. Signal SEC_WDRSel may be used to activate secure WDR 410 and random number generator 450. Signal NonSec_WDRSel may be used to activate unsecure WDR 412. WIR 414 may also provide signal WDRSel, which is partially used to select whether secure WDR 410 or unsecure WDR 412 provides information to output bus WSO. In some embodiments, signal WDRSel may be provided directly by WIR 414. In some embodiments, signal WDRSel may be provided by WIR decoder circuit 415.

[0048] The unsecure WDR 412 has an input terminal coupled to the input bus WSI and a clock terminal coupled to the output of the AND gate 454. The AND gate 454 has input terminals that provide the signals NonSec_WDRSel, ShiftWR, and the clock signal WRCLK. Thus, when the signals NonSec_WDRSel and ShiftWR are valid, the AND gate 454 may provide the clock signal WRCLK to the clock terminal of the unsecure WDR 412. When activation (e.g., a rising edge) of the clock signal WRCLK is received at the clock terminal of the unsecure WDR 412, the unsecure WDR 412 may shift the information in the register and store the current state of the input bus WSI in the first register.

[0049] The secure WDR 410 is generally similar to the unsecure WDR 412, and similar features will not be repeated for the sake of brevity. The secure WDR 410 has a clock terminal coupled to the output terminal of the AND gate 453. The input terminal of the AND gate 453 provides the signals ShiftWR, SEC_WDRSel, and WRCLK. Therefore, when the signals SEC_WDRSel and ShiftWR are valid, the clock signal WRCLK can be passed from the AND gate 452 to the clock terminal of the secure WDR 410 and the clock terminal of the random number generator 450.

[0050] An input terminal of the secure WDR 410 is coupled to the output of the cryptographic circuit 408. The random number generator 450 has a clock terminal coupled to the output terminal of the AND gate 452. The AND gate 452 has input terminals coupled to the signals ShiftWR, SEC_WDRSel, and WRCLK. Similar to the secure WDR 410, when the signals ShiftWR and SEC_WDRSel are valid, the clock signal WRCLK is passed to the clock terminal of the random number generator 450.

[0051] The random number generator 450 may provide a value of the signal randomgen_out whenever an activation is received at a clock terminal of the random number generator 450. The signal randomgen_out may be a binary signal at a high logic level or a low logic level (e.g., 1 or 0). The random number generator 450 may provide the signal randomgen_out with a behavior that is known to the supplier organization but unknown to the customer organization. In some embodiments, the random number generator 450 may provide the value of the signal randomgen_out with a behavior over time that is difficult to predict without knowing the details of the operation of the random number generator 450. For example, the pattern of the signal randomgen_out over time may appear to have random characteristics.

[0052] The signal randomgen_out is provided to an input terminal of the EOR gate 451, and the input bus WSI is coupled to the other input terminal of the EOR gate 451. The output terminal of the EOR gate 451 is coupled to the input terminal of the safety WDR 410. If the value on the input bus WSA matches the value of randomgen_out, then a low logic level is provided to the input of the safety WDR 410, and if WSI does not match the value of randomgen_out, then a high value is provided to the input of the safety WDR 410. Therefore, when the signals SEC_WDRSel and SelectWIR are valid with each activation of the clock signal WRCLK, a new value of randomgen_out is generated, combined with the input value WSI, and then stored in the safety WDR 410.

[0053] When information is written to secure WDR 410, the values ​​input along input bus WSI may have been previously encrypted based on knowledge of the behavior of random number generator 450. Therefore, random number generator 450 and EOR gate 451 may work together to store decrypted data in secure WDR 410 after decrypting the information along input bus WSI.

[0054] During a read operation of the WDR circuit 400, information can be read out from the shift registers (e.g., secure WDR 410, unsecure WDR 412, and / or WIR 414) to the output bus WSO. During a read organization, when one of the shift registers is activated and receives a signal at the clock terminal, data is read out from the register to the output terminal. The selection of the shift registers using the signals SEC_WDRSel, NonSec_WDRSel, and SelectWIR can be substantially similar to the selection made during a write operation.

[0055] Latch circuit 458 has an input terminal coupled to the output of multiplexer 457 and a clock terminal coupled to clock signal WRCLK. The value stored in latch circuit 458 can be provided along output bus WSO. Multiplexer 457 has an input terminal coupled to the output terminal of WIR 414 and an input terminal coupled to signal WDROut. The selector terminal of multiplexer 457 is coupled to signal SelectWIR. Thus, when signal SelectWIR is at a high level, multiplexer 457 provides the output signal from WIR 414 to latch 458, and when signal SelectWIR is at a low level, signal WDROut is provided to latch 458.

[0056] Signal WDROut represents the output of one of the two WDRs 410 or 412, and one of them is determined by signal WDRSel. Signal WDROut is provided by the output terminal of multiplexer 456, which has input terminals coupled to the output terminals of secure WDR 410 and unsecure WDR 412. Signal WDRSel is coupled to the select terminal of multiplexer 456.

[0057] In response to activation of clock signal WRCLK, latch circuit 458 may latch the current value provided to its input terminal (e.g., the value provided by multiplexer 457). The latched value may be provided as the value along output bus WSO until the next activation of the clock signal causes latch circuit 458 to latch a new value.

[0058] Figure 5 5 is a timing diagram of the operation of a WDR circuit according to an embodiment of the present invention. In some embodiments, the timing diagram 500 may represent the operation of a WDR circuit, such as Figure 4 The WDR circuit 400 (and / or Figure 1 104). The timing diagram 500 shows several different signals (and states of shift registers such as WIR, secure WDR, and unsecure WDR) along a common time axis extending along the horizontal axis.

[0059] Timing diagram 500 includes a clock signal WRCLK. Clock signal WRCLK is a periodic signal that may be connected to one or more other clock signals of a device (eg, a clock signal of HBM 100 and / or host device 102). Figure 5 In the example embodiment of FIG. 5 , the clock signal WRCLK alternates between a high logic level and a low logic level with regular timing.

[0060] Timing diagram 500 further includes a timing diagram for activating WIR (eg, Figure 4When the signal SelectWIR is valid (eg, at a high logic level), the state of the bit on the input bus WSI can be written to WIR. Figure 5 In an embodiment of the present invention, WIR, secure WDR and unsecure WDR may be shift registers including, for example, 4 individual registers. Therefore, the signal SelectWIR may be valid for 4 rising edges of the clock signal WRCLK.

[0061] Timing diagram 500 further includes a register signal ShiftWR. When signal ShiftWR is at a high level, one of the shift registers may be activated. Similar to signal SelectWIR, signal ShiftWR may be at a high level for 4 rising clock edges to allow 4 bits to be written to the shift register. Signal ShiftWR may be at a high logic level for 4 rising edges of signal WRCLK, and then, for one rising edge of WRCLK, may be at a low logic level.

[0062] The timing diagram 500 further includes values ​​along the input bus WSI. The signal line WSI is labeled with LSB (for least significant bit) at the left side of each activation of ShiftWR and with MSB (for most significant bit) at the right side of each activation of ShiftWR. For illustrative purposes only, these are meant to show how data is loaded into the shift register.

[0063] Timing diagram 500 further includes the values ​​of the bits stored in the WIR. Each box represents the state of 4 bits from the most significant bit to the least significant bit stored in the register of the WIR.

[0064] The timing diagram 500 further includes a random number randomgen_out. The seventh signal of the timing diagram 500 is the non-secure selection signal NonSec_WDRSel. The eighth signal is the value of the bit stored in the non-secure WDR. The ninth signal is the secure selection signal Sec_WDRSel, and the tenth signal is the value of the bit stored in the secure WDR.

[0065] At an initial time t0, information may be written into WIR. Therefore, the SelectWIR signal may be at a high level (along with ShiftWR). At the first rising edge of the clock signal WRCLK, the current value on WSI may be written to WIR. Because the signal on WSI is at a high logic level, a logic high may be written to WIR, marking an overall value of 1000. At the next rising edge of the clock signal, the previously stored 1 may be shifted away, and the current value of WSI (low logic level) may be written to produce 0100. The next rising edge also loads a low logic level on WSI to produce 0010, and the fourth clock signal adds another 0 to produce 0001.

[0066] At time t1, data to be written to one of the WDRs may be provided along the input bus WSI. The value 0001 may indicate that the unsafe WDR should be active. Therefore, when the value 0001 is stored in WIR, the signal NonSec_WDRSel may rise to a high logic level. At time t1, the signal ShiftWR may be valid again. Because the signal NonSec_WDRSel is at a high level (and because SelectWIR is low), the value on the input bus WSI may be written to the unsafe WDR. From the first clock pulse to the last clock pulse, the value of WSI may be 1, 1, 0, and 0. Therefore, the state of the unsafe WDR may change from 0000 to 1000 to 1100 to 0110 to 0011.

[0067] At time t2, the WIR may be activated again and may be loaded with new information. At each of the 4 rising clock edges, the value of the input bus is 0, 1, 0, and then 0. Therefore, the state of the WIR may become 0000 (because the previously stored 1 in the least significant bit is 'pushed out' by the first 0), then to 1000, then to 0100, then to 0010. The value 0010 stored in the WIR may indicate that the security WDR and random number generator should be activated. Therefore, once 0010 is loaded in the WIR, the signal Sec_WDR may rise to a high logic level.

[0068] At time t3, both signals ShiftWR and SEC_WDR are active. At the first rising clock edge (shown by the vertical arrow), the value along WSI is 0, and the value of randomgen_out is also 0. Therefore, 0 is written to SEC_WDR (e.g., the EOR of 0 and 0 is 0), maintaining the overall value of 0000. Next, the value of WSI is 0 and randomgen_out is 1, and therefore 1 is written to Sec_WDR to change the overall value to 1000. Next, the value of WSI is 1 and the value of randomgen_out is 0, causing 1 to be written to Sec_WDR to change the overall value to 1100. Finally, the value of WSI and the value of randomgen_out are 1, and therefore 0 is written to Sec_WDR to yield a final value of 0110.

[0069] As can be seen, to write the value 0011 to the unsecure WDR, the plaintext values ​​1, 1, 0, and 0 are provided along the input bus WSI (in backward order from LSB to MSB due to the operation of the shift register). To write the value 0110 to the secure WDR, then the encrypted values ​​0, 0, 1, and 1 are written to WSI. Therefore, without knowing the sequence of values ​​of randomgen_out, it is impossible to determine the decrypted value 0110 from the sequence of encrypted values ​​0, 0, 1, and 1 along WSI.

[0070] The encrypted information may be stored in a data file (e.g. Figure 1 The data may have been previously encrypted based on knowledge of the operation of the cryptographic circuit 408 (e.g., knowledge of the sequence of bits provided by the random number generator circuit). In some embodiments, the supplier organization may determine the plain text value (e.g., 0110) to be written to the secure WDR, and then, may generate encrypted input data that is provided to the customer organization to be loaded into the HBM device. In this way, the customer organization may only know the encrypted information and cannot determine the value actually written to the secure WDR.

[0071] Figure 6 6 is a schematic diagram of a WDR circuit according to an embodiment of the present invention. In some embodiments, the WDR circuit 600 may be included in Figure 1 The WDR circuit 600 may be substantially similar to Figure 44. The WDR circuit 400 of FIG. 4 is a WDR circuit 600 of FIG. 4, and for the sake of brevity, the operations, features, and components previously described with respect to the WDR circuit 400 will not be repeated. Unlike the WDR circuit 400, the WDR circuit 600 includes a cryptographic circuit 608, which includes an encryption circuit used as part of a read operation. In the WDR circuit 600, during a read operation, information is read from the secure WDR 610, and the encrypted information is provided to the output bus WSO after being encrypted by the cryptographic circuit 608.

[0072] During a read operation from secure WDR 610, both signals ShiftWR and Sec_WDRSel (which are based on the state of WIR 614) are asserted. This may result in pulses of clock signal WRCLK being provided to the clock terminal of random number generator 650 (via AND gate 652) and secure WDR 610 (via AND gate 653). Figure 6 In the embodiment of , each circuit may respond to the falling edge of the clock signal WRCLK. In response to each falling edge, the random number generator 650 may generate a new value of the random number randomgen_out, and the secure WDR 610 may provide one of the stored values, and then transfer the stored value to a register.

[0073] exist Figure 6 In the embodiment of FIG. 5 , the EOR gate 651 has a first input terminal coupled to the random number generator randomgen_out and a second input terminal coupled to the output terminal of the secure WDR 610. The output terminal of the EOR gate 651 is coupled to one of the input terminals of the multiplexer 656. In this way, the EOR gate 651 can encrypt the output of the secure WDR 610 based on the random number randomgen_out to provide the encrypted output to the output bus WSO.

[0074] Figure 7 700 is a timing diagram of a write operation according to an embodiment of the present invention. In some embodiments, the timing diagram 700 may depict Figure 6 The operation of the WDR circuit 600 is shown in FIG. 7. Because the timing diagram 700 may be substantially similar to Figure 5 Therefore, for the sake of brevity, the features and operations similar to those of the timing diagram 500 will not be repeated for the timing diagram 700.

[0075] Because timing diagram 700 depicts a read operation rather than a write operation, the various operations of timing diagram 700 are synchronized to the falling edge of clock signal WRCLK (rather than the falling edge of clock signal WRCLK). Figure 5). In the initial time period, WIR (e.g., WIR 614) is activated and the value 0001 is written to WIR by writing the values ​​1, 0, 0, and then 0 to the shift register. This value in WIR causes the select signal of the unsafe WDR NonSec_WDRSel to become valid. Starting at time t1, the value in the unsafe WDR0011 is written out to the output bus WSO as the value 1, 1, 0, and then as the value 0. At time t2, WIR is activated again and the value 0010 is written to WIR by providing the values ​​0, 1, 0, and then the value 0 along the input bus WSI. This can cause the secure select signal Sec_WDRSel to become valid.

[0076] Starting at time t3, information can be read from the secure WDR, encrypted, and then the encrypted data can be written to the output bus WSO. Prior to time t3, the secure WDR stores the value 0110. At the first falling edge of t3, the value 0 is read from the secure WDR (leaving the value of the secure WDR as 0011). The read value 0 is provided to the EOR gate along with the value 0 of randomgen_out. The EOR of 0 and 0 is 0, so a low logic level is provided to WSO. At the next falling edge of the clock signal WRCLK, a value 1 is read from the secure WDR and EORed with randomgen_out 1 to yield an output 0 along WSO. At the third falling edge of the clock signal WRCLK, a value 1 is read from the secure WDR and EORed with randomgen_out 0 to yield an encrypted value 1 along WSO. At the fourth falling edge of the clock signal WRCLK, a value 0 is read from the secure WDR and EORed with randomgen_out1 to yield a value 1 along the output bus WSO.

[0077] Thus, the value 0110 stored in the secure WDR is encrypted by the value of the random number randomgen_out to provide an output sequence of 0, 0, 1, and 1. Without knowing the value of the random number randomgen_out over time, it may be difficult or impossible to extract the value 0110 from the output sequence of 0, 0, 1, and 1. The value 0011 may be provided along the output bus and may be stored in a data file (e.g., Figure 1 The data file can be retrieved later by the supplier organization, which can use the knowledge of the random number over time to decrypt the information in order to recover the original sequence 0110.

[0078] It should be noted that although Figure 4 An embodiment of the invention shows a circuit for decrypting incoming information as part of a read operation, and Figure 6Circuitry is shown for encrypting outgoing information as part of a write operation, but in some embodiments, Figure 4 and 6 The features of may be combined for a WDR circuit that performs both encryption and decryption. This circuit may include an EOR gate (e.g., EOR gate 451) positioned between the input bus WSI and the input terminal of the secure WDR and an EOR gate (e.g., EOR gate 651) positioned between the output terminal of the secure WDR and the output bus WSO. In some embodiments, the two EOR gates may share a random number generator (e.g., commonly coupled to randomgen_out). In some embodiments, they may have separate random number generators. The circuit that performs both functions may have a random number generator in the same random number generator. Figure 5 and 7 The timing diagrams of both show the operations.

[0079] Of course, based on the present systems, devices and methods, it should be understood that any of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and / or processes, or may be separated and / or executed in separate devices or device portions.

[0080] Finally, the above discussion is intended to be illustrative only of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described with reference to exemplary embodiments in particular detail, it should also be appreciated that a person of ordinary skill in the art may envision numerous modifications or alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a safety circuit comprising an input terminal coupled to an input bus; an unsafe circuit having an input terminal coupled to the input bus; A decryption circuit is coupled to the input terminal of the security circuit and the input bus, the decryption circuit being configured to decrypt input data provided along the input bus and provide the decrypted input data to the security circuit.

2. The apparatus according to claim 1, further comprising: a wrapper instruction register configured to, when active, store information received along the input bus; A decoder circuit is configured to provide a select signal based on the information stored in the wrapper instruction register, wherein the information is stored in the secure circuit when the select signal is provided.

3. The apparatus of claim 1, wherein the secure circuit is a secure wrapper data register coupled to at least one secure circuit of a memory, and wherein the unsecure circuit is an unsecure wrapper data register coupled to at least one unsecure circuit of a memory.

4. The apparatus of claim 3, wherein the memory is a high bandwidth memory, and wherein the interface bus couples an interface die of the high bandwidth memory to a host device.

5. The apparatus of claim 1, wherein the decryption circuit comprises a random number generator configured to provide a random number sequence, and wherein the input data is decrypted based on the random number sequence.

6. The apparatus of claim 1, further comprising: an output bus, wherein the secure circuit further comprises an output terminal coupled to the output bus, and the unsecure circuit further comprises an output terminal coupled to the output bus; as well as An encryption circuit is positioned between the output terminal of the security circuit and the output bus, the encryption circuit being configured to encrypt output information provided at the output terminal of the security circuit and to provide the encrypted output information along the output bus.

7. The apparatus of claim 6, wherein the first WDR is coupled to at least one security specific circuit of a memory, and wherein the second WDR is coupled to at least one specific unsecure circuit of the memory.

8. The apparatus of claim 7, wherein the memory device is a high bandwidth memory and the output bus couples the high bandwidth memory to a host device.

9. The apparatus of claim 7, wherein the at least one safety specific circuit comprises a built-in self-test (BIST) circuit.

10. The apparatus of claim 9, wherein the memory device is a high bandwidth memory device comprising at least one core die and an interface die comprising the BIST circuit, and wherein the BIST circuit is configured to test one or more memory cells of the at least one core die based on information stored in the first WDR.

11. The apparatus of claim 6, wherein the interface bus is an IEEE 1500 bus.

12. The apparatus of claim 6, wherein the encryption circuit comprises a random number generator configured to provide a random number when activated by the selection signal, wherein the encryption circuit is configured to receive the output data and combine it with the random number to generate encrypted output data.

13. The apparatus of claim 1, further comprising: A host device is configured to provide encrypted information and a select signal in a first state and further configured to provide unencrypted information and the select signal in a second state.

14. The apparatus of claim 13, wherein the host device is configured to provide a wrapper instruction register (WIR) select signal at an active level and the select signal in the first state, and then provide the WIR select signal at an inactive level and the encrypted information.

15. The apparatus of claim 13, wherein the host device is configured to provide a wrapper instruction register (WIR) select signal at an active level and the select signal in the second state, and then provide the WIR select signal at an inactive level and the unencrypted information.

16. The apparatus of claim 13, wherein the encrypted information includes information for a built-in self-test (BIST) circuit.

17. The apparatus of claim 13, wherein the host device is further configured to provide the selection signal in the first state and receive encrypted information, and wherein the host device is further configured to provide the selection signal in the second state and receive unencrypted information.

18. The apparatus of claim 13, further comprising an interface coupled to the host device, wherein the interface bus comprises the input bus and an output bus.

19. The apparatus of claim 5, wherein the random number generator is activated based on a signal from a register.

20. The apparatus of claim 1, further comprising a multiplexer configured to provide information for the secure circuit or the unsecure circuit based on a signal from a register.

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