Chip verification method and device, electronic equipment and computer program product

Abstract

The invention belongs to the technical field of chip design, and mainly provides a chip verification method and device, electronic equipment and a computer program product, and the method comprises the steps: carrying out the function verification of a joint test action group in an electronic design automation simulation stage, and obtaining a verification result of a chip in the electronic design automation simulation stage, the function verification time of the joint test action group of the chip is advanced from a field programmable gate array verification stage (i.e., a prototype test and verification stage) to an electronic design automation simulation stage (i.e., a register transfer stage verification stage), and the function verification of the joint test action group of the chip can be realized in the electronic design automation simulation stage. According to the method, problems possibly existing in chip design are found in advance, some problems possibly existing in the chip design are prevented from being left in a field programmable gate array verification stage, and when the problems exist in the chip design, register transmission level codes with the problems can be directly positioned, so that the problems are more explicit, and the problem solving efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a chip verification method, device, electronic equipment and computer program product. Background Art

[0002] In chip development, in order to avoid uncorrectable hardware failures after chip tape-out and reduce the risk of later problems, the chip needs to be verified during the chip design phase to ensure that its design fully meets the required specifications, resolve potential risks, and correct existing defects.

[0003] However, as the scale and complexity of chips increase, the difficulty of verification also increases, and high coverage becomes an increasingly difficult goal. How to improve the coverage of chip verification, solve the problems found in chip verification more efficiently, and shorten the chip development cycle and development costs are the key issues in current chip development. Summary of the invention

[0004] The present invention provides a chip verification method, device, electronic device and computer program product, which can solve the technical problems in existing solutions that chip verification cannot achieve high coverage and problems found in chip verification cannot be efficiently solved.

[0005] A first aspect of an embodiment of the present invention provides a chip verification method, the chip verification method comprising:

[0006] Use electronic design automation simulation tools to simulate the chip and obtain a chip circuit that includes a debugging interface for the joint test action team;

[0007] The chip circuit is subjected to a joint test action team functional verification to obtain the verification result of the chip in the electronic design automation simulation stage.

[0008] A second aspect of an embodiment of the present invention further provides a chip verification device, the chip verification device comprising:

[0009] A simulation unit, used to simulate the chip using an electronic design automation simulation tool to obtain a chip circuit including a debugging interface of the joint test action team;

[0010] The verification unit is used to perform joint test action team functional verification on the chip circuit to obtain the verification result of the chip in the electronic design automation simulation stage.

[0011] A third aspect of an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the chip verification method described in the first aspect when executed by the processor.

[0012] A fourth aspect of an embodiment of the present invention provides a computer program product, which stores a computer program. When the computer program is executed by a processor, the steps of the chip verification method described in the first aspect are implemented.

[0013] In an embodiment of the present invention, an electronic design automation simulation tool is used to simulate and design a chip to obtain a chip circuit that supports a joint test action group debugging interface, and the chip circuit is subjected to joint test action group functional verification to obtain a verification result of the chip in the electronic design automation simulation stage, so that the chip can be verified using the joint test action group debugging interface in the electronic design automation simulation stage, rather than using the joint test action group debugging interface to verify the chip in the field programmable gate array (FPGA) verification stage. This enables the time for the joint test action group functional verification of the chip to be advanced from the field programmable gate array verification stage (i.e., the prototype testing and verification stage) to the electronic design automation simulation stage. Therefore, it is possible to discover possible problems in chip design in advance in the electronic design automation simulation stage, thereby avoiding leaving some possible problems in chip design in the field programmable gate array verification stage, which is conducive to early resolution of the problems.

[0014] In addition, the present invention performs joint test action group functional verification in the electronic design automation simulation stage, so that when there is a problem in the chip design, the problematic register transfer level (RTL) code can be directly located and the problem can be reproduced, making the problem in the chip design more obvious, which is conducive to improving the efficiency of problem solving and shortening the chip development cycle and development cost. Moreover, since the function of the joint test action group debugging interface is very powerful and can access a lot of content, it can also achieve a more comprehensive verification of the chip in the electronic design automation simulation stage, improve the chip verification coverage in the electronic design automation simulation stage, and then improve the verification quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the implementation flow of a chip verification method provided by an embodiment of the present invention.

[0016] Figure 2 A schematic diagram of a chip structure provided in an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of the implementation flow of step 102 of the chip verification method provided in an embodiment of the present invention.

[0018] Figure 4This is a schematic diagram of a specific implementation flow of step 1023 of the chip verification method provided in an embodiment of the present invention.

[0019] Figure 5 A schematic diagram of the structure of a chip verification device provided by an embodiment of the present invention.

[0020] Figure 6 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] It should be understood that in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0023] In addition, in the description of the present specification and the appended claims, the terms "first", "second", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include a particular feature, structure or characteristic described in conjunction with the embodiment. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0025] The English abbreviations and their corresponding Chinese translations included in the present invention are as follows:

[0026] EDA (Electronic design automation); JTAG (Joint Test Action Group); SOC (System on Chip); RTL (register transfer level); CPU (Central Processing Unit); DDR (Double Data Rate), SRAM (Static Random Access Memory).

[0027] In chip development, in order to avoid uncorrectable hardware failures after chip tape-out and reduce the risk of later problems, the chip needs to be verified during the chip design phase to ensure that its design fully meets the required specifications, resolve potential risks, and correct existing defects.

[0028] However, as the scale and complexity of chips increase, the difficulty of verification also increases, and high coverage becomes an increasingly difficult goal. How to improve the coverage of chip verification and solve the problems found in chip verification more efficiently, shorten the chip development cycle and development costs, is an important issue that needs to be solved in current chip development.

[0029] Based on this, the embodiments of the present invention provide a chip verification method, device, electronic device and computer program product, which can solve the technical problems in existing solutions that chip verification cannot achieve high coverage and problems found in chip verification cannot be efficiently solved.

[0030] like Figure 1 , which is a schematic diagram of a first implementation flow of a chip verification method provided by an embodiment of the present invention. The chip verification method can be implemented by using the following steps 101 to 102.

[0031] Step 101, use electronic design automation simulation tools to simulate and design the chip to obtain a chip circuit including a debugging interface of the joint test action team.

[0032] Step 102, perform joint test action team functional verification on the chip circuit to obtain the verification result of the chip in the electronic design automation simulation stage.

[0033] In the embodiment of the present invention, the electronic design automation simulation tool refers to an electronic design automation (EDA) tool used for circuit design and verification. Electronic design automation simulation can help engineers discover and solve potential design problems during the chip design stage.

[0034] The Joint Test Action Group (JTAG) is an international standard test protocol, mainly used for internal chip testing and system simulation and debugging. The Joint Test Action Group technology is an embedded debugging technology that encapsulates a special test circuit TAP (Test Access Port) inside the chip and tests the internal nodes through a dedicated Joint Test Action Group test tool.

[0035] As a powerful hardware debugging tool, the JTAG debug interface plays an important role in debugging field programmable gate arrays. Through the JTAG debug interface, engineers can configure, debug, monitor and troubleshoot field programmable gate arrays, accelerate the development cycle and improve product quality. At the same time, the non-intrusive nature of the JTAG debug interface makes it an efficient and safe debugging tool that can be widely used in the field of digital system design and debugging.

[0036] That is, in current practice, the JTA debug interface is used in field programmable gate array debugging as a backdoor for chip verification to observe and control the internal state of the chip.

[0037] Different from this, the present invention obtains a chip circuit that supports the joint test action group debugging interface in the electronic design automation simulation stage of chip design, so that the chip can use the joint test action group debugging interface to verify the chip in the electronic design automation simulation stage, rather than using the joint test action group debugging interface to verify the chip in the field programmable gate array verification stage. The time of the joint test action group function verification of the chip is advanced from the field programmable gate array verification stage (i.e., the prototype testing and verification stage) to the electronic design automation simulation stage (i.e., the register transfer level verification stage). Therefore, it is possible to discover possible problems in chip design in advance in the electronic design automation simulation stage, avoid leaving some possible problems in chip design in the field programmable gate array verification stage, and facilitate early resolution of problems.

[0038] Specifically, the chip verification of most chip design manufacturers currently includes electronic design automation simulation verification and field programmable gate array function verification. In the electronic design automation simulation stage, the specific simulation object is the register transfer level code obtained in the chip design stage. Register transfer level (RTL) code refers to the description of the data flow of digital circuits using the register transfer level description method. In the register transfer level verification stage, the data is in an ideal state during the transmission process, that is, there is no delay in the signal during the transmission process, and the transition process of the digital signal from 0 to 1 or 1 to 0 is completed instantly. Field programmable gate array function verification belongs to prototype verification, and its purpose is to test and verify the circuit design through prototype hardware close to the final chip in the early stage, and to ensure the design of the correct chip by running at a speed close to the final chip. Prototype verification maps the design to the field programmable gate array, verifies the overall function of the chip by simulating the function and application environment of the chip, and provides an on-chip software development environment.

[0039] Compared with the register transfer level verification stage, the field programmable gate array function verification belongs to a later verification, and the register transfer level verification stage belongs to an earlier chip verification. The present invention obtains a chip circuit that supports the debugging interface of the joint test action group in the electronic design automation simulation stage of the chip design, so that the time of the joint test action group function verification of the chip is advanced from the field programmable gate array verification stage (i.e., the prototype test and verification stage) to the electronic design automation simulation stage (i.e., the register transfer level verification stage), and realizes that in the electronic design automation simulation stage, the problems that may exist in the chip design are discovered in advance, and some problems that may exist in the chip design are avoided from being left in the field programmable gate array verification stage, which is conducive to solving the problems in advance. It also makes it possible to directly locate the register transfer level (RTL) code with problems when there are problems in the chip design, and reproduce the problems, so that the problems in the chip design are more obvious, which is conducive to improving the efficiency of problem solving and shortening the development cycle and development cost of the chip. In addition, since the debugging interface of the Joint Test Action Team is very powerful and can access a lot of content, it can also achieve more comprehensive verification of the chip during the electronic design automation simulation stage, thereby improving the chip verification coverage during the electronic design automation simulation stage and thus improving the verification quality.

[0040] like Figure 2 As shown, the chip mentioned in the embodiment of the present invention may include a central processing unit (CPU) and a joint test action team debugging interface located outside the central processing unit. Figure 3As shown, in one embodiment of the present invention, the above-mentioned step 102 of performing joint test action group functional verification on the chip circuit includes step 1021: verifying the startup of the central processor based on the joint test action group debugging interface to obtain the verification result of the joint test action group startup function.

[0041] In actual applications, the CPU startup mode includes a normal startup mode and a startup mode based on a debugging tool. Among them, the normal startup mode refers to the startup mode corresponding to the normal startup of the CPU. When the CPU cannot start normally, it needs to be started based on a debugging tool. The CPU is started based on the debugging interface of the Joint Test Action Group (i.e., started based on the Joint Test Action Group) is one of the startup modes based on the debugging tool.

[0042] When the CPU is normally started, it is started through BootROM (BootROM is the first program executed when the chip is powered on or restarted). When there is an abnormality in BootROM, the CPU can be started from other locations through the debugging tool. As an implementation of the present invention, the startup process of the CPU based on the debugging interface of the Joint Test Action Group can include the following steps A01 to A03.

[0043] Step A01, pull the central processing unit through soft reset to make the joint test action team debugging interface work normally.

[0044] Step A02, configure the ROM (read-only memory) clock and release the ROM reset.

[0045] Step A03, configure the CPU soft reset and start the CPU normally.

[0046] In practical applications, the startup mode of the central processing unit can be set by hardware design. Specifically, the chip can be provided with a mode input / output port. When the mode input / output port is at a high level 1, it indicates that the central processing unit is started by the joint test action team. When the mode input / output port is at a low level 0, it indicates that the central processing unit is started by the normal startup method. The present invention pulls the central processing unit by soft reset, which means that the mode input / output port is at a high level so that the central processing unit is started by the joint test action team, that is, the debugging interface of the joint test action team works normally. When the debugging interface of the joint test action team can work normally, the ROM (read-only memory) clock can be configured, the ROM reset is released, and the instructions in the ROM are read to realize the startup of the central processing unit.

[0047] It should be noted that the present invention only describes the startup process of the CPU based on the debug interface of the joint test action group, and does not limit the protection scope of the present invention. In different chip designs, the debug interface of the joint test action group can be used to control the startup of the CPU in different ways. For example, in some chip designs, the CPU is usually started under a reset signal. The debug interface of the joint test action group can send a reset signal to the CPU, unlock or lock the access to the internal register or state machine, and program or debug the code executed by the CPU through the debug interface of the joint test action group to start the CPU. The present invention does not limit this.

[0048] In an embodiment of the present invention, when the central processing unit can be started based on the joint test action group debugging interface, it indicates that there is no abnormality in the joint test action group startup function. When the central processing unit cannot be started based on the joint test action group debugging interface, it indicates that there is an abnormality in the joint test action group startup function and the joint test action group debugging interface or other parts of the chip need to be modified or optimized.

[0049] In addition to the above verification of the CPU based on the JTA debug interface startup, such as Figure 3 As shown, in one embodiment of the present invention, the above step 102 performs joint test action group functional verification on the chip circuit, and also includes step 1022: accessing the internal registers of the central processing unit based on the joint test action group debugging interface to obtain the accuracy of the internal registers of the central processing unit.

[0050] When there is no problem with the design of the internal registers of the central processing unit, the joint test action team debugging interface can read the data of the internal registers of the central processing unit normally. When there is a problem with the address mapping of the internal registers of the central processing unit or there are other problems that affect data reading, the joint test action team debugging interface may not be able to access certain addresses of the internal registers of the central processing unit. Based on this, the present invention accesses the internal registers of the central processing unit based on the joint test action team debugging interface, and can obtain the accuracy of the internal registers of the central processing unit, that is, whether there are problems with the internal registers of the central processing unit.

[0051] In one embodiment of the present invention, when there is a problem with the internal register of the central processing unit, the address with the problem can be directly output to optimize it.

[0052] In the embodiment of the present invention, when the joint test action team debugging interface can normally read the data of the internal registers of the central processing unit, it not only indicates that there is no problem with the address management of the internal registers of the central processing unit, but also indicates that there is no problem with the connection of the joint test action team debugging interface.

[0053] Specifically, in the process of accessing the internal registers of the central processing unit based on the joint test action team debugging interface to obtain the accuracy of the internal registers of the central processing unit, the data in the internal registers of the central processing unit can be read through the joint test action team debugging interface and compared with the default data. When the comparison is successful, it means that the joint test action team debugging interface can read the data of the internal registers of the central processing unit normally.

[0054] In one embodiment of the present invention, the chip in the present invention is a system-on-chip chip, including an internal storage space of the system-on-chip; the above-mentioned step 102 performs joint test action team functional verification on the chip circuit, and also includes step 1023: accessing the internal storage space of the system-on-chip based on the joint test action team debugging interface to obtain the accuracy of the internal storage space of the system-on-chip.

[0055] In the embodiments of the present invention, the system on chip (System on Chip, SOC) refers to a system-level chip, which is an integrated circuit with a dedicated purpose, including a complete system and all the contents of the embedded software. The system on chip usually integrates a central processing unit (CPU), a graphics processing unit (GPU), communication and other modules, and is widely used in the fields of mobile phone main chips. The internal storage space of the system on chip can include double data rate synchronous dynamic random access memory (Double Data Rate, DDR), static random access memory (Static Random Access Memory, SRAM), non-volatile memory and other types of internal storage space. The present invention does not limit the type of internal storage space of the system on chip.

[0056] In one embodiment of the present invention, in order to improve the access efficiency of the debugging interface of the joint test action team, as Figure 4 As shown, the above step 1023 accesses the internal storage space of the system on chip based on the debugging interface of the joint test action team to obtain the accuracy of the internal storage space of the system on chip, which can be implemented by the following steps 401 to 403.

[0057] Step 401 , select some storage addresses in the internal storage space of the system on chip as addresses to be accessed.

[0058] Generally speaking, the accuracy verification of the internal storage space of the system on chip by the debugging interface of the joint test action team must be guaranteed, and all accessible storage spaces must be traversed. However, since the internal storage space of the system on chip is too large, traversing all accessible storage spaces results in low access efficiency. Based on this, for each different storage space, such as Double Data Rate (DDR), Static Random Access Memory (SRAM), and non-volatile memory, part of the storage addresses of each different storage space can be selected for access to obtain the accuracy of the entire internal storage space of the system on chip.

[0059] In one embodiment of the present invention, a head address, a tail address, and a plurality of middle addresses in the internal storage space of the system on chip may be used as addresses to be accessed.

[0060] That is, for each different storage space, a head address, a tail address and a plurality of middle addresses are respectively selected as addresses to be accessed.

[0061] For example, for one of the DDR internal storage spaces, select its corresponding head address (i.e., the address corresponding to the starting position of the storage space), tail address (i.e., the ending address) and several intermediate addresses as the addresses to be accessed, for example, a total of 20 addresses, respectively address 1 to address 20, and address 1 to address 20 (add1-add20) are used as the addresses to be accessed.

[0062] Step 402: Generate an address access file based on the address to be accessed.

[0063] The address access file records the operation attributes, operation address and corresponding operation data.

[0064] In an embodiment of the present invention, when accessing the internal storage space of the on-chip system based on the joint test action team debugging interface, the driver function jtag_driver of the joint test action team can be defined first, and the address to be accessed is recorded in the address access file, which includes the following information: operation attributes, operation addresses and corresponding operation data, wherein the operation attributes include read operations (read) and write operations (write), the operation addresses include the addresses corresponding to the read operations and the addresses corresponding to the write operations, that is, the read addresses and the write addresses (that is, add1-add20), and the operation data include the read data corresponding to the read operations and the write data corresponding to the write operations (that is, data1-data20).

[0065] Continuing with the above example, when the addresses to be accessed include address 1 to address 20 (add1-add20), a total of 20 addresses, the text information contained in the address access file is shown in Table 1 below.

[0066] Table 1:

[0067]

[0068] Step 403 , access the addresses to be accessed one by one based on the address access file, and obtain the accuracy of the internal storage space of the system on chip according to the access result.

[0069] When accessing the addresses to be accessed one by one based on the joint test action team debugging interface, the verification environment can first extract the file information in the address access file, and for write operations, write the write data into the write address; for read operations, read the data at the read address and compare it with the write data for verification. For the same address, if the read data is consistent with the written data, it can be determined that the function of the joint test action team debugging interface to access the address is normal; otherwise, it is determined that the function of the joint test action team debugging interface to access the address is abnormal.

[0070] In one embodiment of the present invention, for a single internal storage space, for example, one of the DDR internal storage spaces, if the functions of the head address, the tail address, and multiple intermediate addresses are normal, then the internal storage space can be considered to be functioning normally; if there are addresses with abnormal functions among the head address, the tail address, and multiple intermediate addresses, then all addresses contained in the internal storage space can be accessed one by one, and the addresses with abnormal functions can be optimized.

[0071] In the embodiment of the present invention, when the functions of each different storage space in the internal storage space of the system on chip are normal, it is confirmed that the functions of the internal storage space of the system on chip are normal.

[0072] In the implementation of the present invention, for addresses with address function anomalies accessed by the debugging interface of the joint test action team, the verification environment can print out address anomaly prompt information to remind the verification personnel to pay attention.

[0073] In one embodiment of the present invention, Figure 3 As shown, the above step 102 performs joint test action team functional verification on the chip circuit, and also includes step 1024: accessing the readable and writable control registers of the system on chip based on the joint test action team debugging interface to obtain the accuracy of the readable and writable control registers of the system on chip.

[0074] In an embodiment of the present invention, the readable and writable control register of the system on chip and the internal storage space of the system on chip are storage spaces with different functions and different attributes. However, access to the readable and writable control register of the system on chip can still be implemented by referring to the aforementioned steps 401 to 403 to improve the access efficiency of the debugging interface of the joint test action team, which will not be repeated here.

[0075] In addition, the specific implementation process of step 1022 for accessing the internal registers of the central processing unit based on the joint test action team debug interface can also refer to the aforementioned steps 401 to 403 to improve the access efficiency of the joint test action team debug interface, which will not be repeated here.

[0076] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, and in some embodiments of the present invention, certain steps can be performed in other sequences. For example, in step 1021 to step 1024, the implementation of each step is not limited by the described action sequence.

[0077] The chip verification method provided in the embodiment of the present invention uses an electronic design automation simulation tool to simulate and design the chip, and obtains a chip circuit that supports the joint test action group debugging interface, so that the chip can use the joint test action group debugging interface to verify the chip in the electronic design automation simulation stage, rather than using the joint test action group debugging interface to verify the chip in the field programmable gate array verification stage. The time of the joint test action group function verification of the chip is advanced from the field programmable gate array verification stage (that is, the prototype test and verification stage) to the electronic design automation simulation stage (that is, the register transfer level verification stage). Therefore, it is possible to discover possible problems in the chip design in advance in the electronic design automation simulation stage, avoid leaving some possible problems in the chip design in the field programmable gate array verification stage, and facilitate early resolution of the problems.

[0078] In addition, the present invention performs joint test action group functional verification in the electronic design automation simulation stage, so that when there is a problem in the chip design, the register transfer level code with the problem can be directly located, and the problem can be reproduced, making the problem in the chip design more obvious, which is conducive to improving the efficiency of problem solving and shortening the chip development cycle and development cost. Moreover, since the function of the joint test action group debugging interface is very powerful and can access a lot of content, it can also achieve a more comprehensive verification of the chip in the electronic design automation simulation stage, improve the chip verification coverage in the electronic design automation simulation stage, and then improve the verification quality.

[0079] The embodiment of the present invention also provides a chip verification device, such as Figure 5 As shown, the chip verification device 500 can be configured on an intelligent electronic device such as a computer, and the chip verification device may include:

[0080] The simulation unit 501 is used to simulate the chip using an electronic design automation simulation tool to obtain a chip circuit including a debugging interface of the joint test action team;

[0081] The verification unit 502 is used to perform joint test action team functional verification on the chip circuit to obtain the verification result of the chip in the electronic design automation simulation stage.

[0082] In one embodiment of the present invention, the chip is provided with a central processing unit; the verification unit 502 is used to verify the startup of the central processing unit based on the debugging interface of the joint test action team to obtain the verification result of the startup function of the joint test action team.

[0083] In one embodiment of the present invention, the verification unit 502 is used to access the internal registers of the central processing unit based on the debugging interface of the joint test action team to obtain the accuracy of the internal registers of the central processing unit.

[0084] In one embodiment of the present invention, the chip is a system-on-chip chip, which is provided with an internal storage space of the system-on-chip; the verification unit 502 is used to access the internal storage space of the system-on-chip based on the debugging interface of the joint test action team to obtain the accuracy of the internal storage space of the system-on-chip.

[0085] In one embodiment of the present invention, the verification unit 502 is specifically used to: select some storage addresses in the internal storage space of the system on chip as addresses to be accessed; generate an address access file based on the addresses to be accessed; the address access file records operation attributes, operation addresses and corresponding operation data; access the addresses to be accessed one by one based on the address access file, and obtain the accuracy of the internal storage space of the system on chip based on the access results.

[0086] In one embodiment of the present invention, the verification unit 502 is specifically configured to use a head address, a tail address, and a plurality of intermediate addresses in the internal storage space of the system on chip as the address to be accessed.

[0087] In one embodiment of the present invention, the verification unit 502 is used to access the readable and writable control registers of the system on chip based on the debugging interface of the joint test action team to obtain the accuracy of the readable and writable control registers of the system on chip.

[0088] It should be noted that, for the convenience and simplicity of description, the specific working process of the chip verification device 500 described above can refer to the above Figures 1 to 4 The corresponding process of the method described in will not be repeated here.

[0089] like Figure 6 As shown, an embodiment of the present invention further provides an electronic device. The electronic device 6 may include: a processor 60, a memory 61, and a computer program 62 stored in the memory 61 and executable on the processor 60. When the processor 60 executes the computer program 62, the steps in the above-mentioned various chip verification method embodiments are implemented, for example, Figure 1 Steps 101 to 102 are shown.

[0090] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or any conventional processor, etc.

[0091] The memory 61 may be an internal storage unit of the electronic device 6, such as a hard disk or a memory. The memory 61 may also be an external storage device for the electronic device 6, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 6. Further, the memory 61 may also include both an internal storage unit of the electronic device 6 and an external storage device. The memory 61 is used to store the above-mentioned computer program and other programs and data required by the electronic device.

[0092] The computer program may be divided into one or more units, which are stored in the memory 61 and executed by the processor 60 to implement the present invention. The one or more units may be a series of computer program instruction segments capable of implementing specific functions, which are used to describe the process of the computer program executing the chip verification method in the electronic device.

[0093] For example, the above computer program can be divided into: a simulation unit and a verification unit, and the specific functions are as follows:

[0094] A simulation unit, used to simulate the chip using an electronic design automation simulation tool to obtain a chip circuit including a debugging interface of the joint test action team;

[0095] The verification unit is used to perform joint test action team functional verification on the chip circuit to obtain the verification result of the chip in the electronic design automation simulation stage.

[0096] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional units as needed, that is, the internal structure of the device can be divided into different functional units to complete all or part of the functions described above. The functional units in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0097] An embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a central processing module, the steps of the chip verification method described in any of the above embodiments are implemented.

[0098] An embodiment of the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the steps of the chip verification method described in any of the above embodiments.

[0099] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0100] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0101] In the embodiments provided by the present invention, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, systems or units, which can be electrical, mechanical or other forms.

[0102] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0103] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0104] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer program product, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or recording medium that can carry computer program code, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electric carrier signals and telecommunication signals.

[0105] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A chip verification method, characterized in that: Chip verification methods include: Use electronic design automation simulation tools to simulate the chip and obtain a chip circuit that includes a debugging interface for the joint test action team; The chip circuit is subjected to a joint test action team functional verification to obtain the verification result of the chip in the electronic design automation simulation stage.

2. The chip verification method according to claim 1, characterized in that: The chip is provided with a central processing unit; the joint test action team functional verification of the chip circuit is performed to obtain the verification result of the chip in the electronic design automation simulation stage, including: The central processing unit is verified based on the startup of the joint test action team debugging interface to obtain a verification result of the joint test action team startup function.

3. The chip verification method according to claim 2, characterized in that: The joint test action team functional verification of the chip circuit is performed to obtain the verification result of the chip in the electronic design automation simulation stage, including: The internal registers of the central processing unit are accessed based on the debugging interface of the joint test action team to obtain the accuracy of the internal registers of the central processing unit.

4. The chip verification method according to any one of claims 1 to 3, characterized in that: The chip is a system-on-chip chip, and is provided with an internal storage space of the system-on-chip; the joint test action team functional verification of the chip circuit is performed to obtain the verification result of the chip in the electronic design automation simulation stage, including: The internal storage space of the system on chip is accessed based on the debugging interface of the joint test action team to obtain the accuracy of the internal storage space of the system on chip.

5. The chip verification method according to claim 4, characterized in that: The step of accessing the internal storage space of the system on chip based on the debugging interface of the joint test action team to obtain the accuracy of the internal storage space of the system on chip includes: Selecting some storage addresses in the internal storage space of the system on chip as addresses to be accessed; Generate an address access file based on the address to be accessed; the address access file records operation attributes, operation addresses and corresponding operation data; The addresses to be accessed are accessed one by one based on the address access file, and the accuracy of the internal storage space of the system on chip is obtained according to the access result.

6. The chip verification method according to claim 5, characterized in that: The selecting part of storage addresses in the internal storage space of the system on chip as addresses to be accessed includes: The head address, the tail address and a plurality of middle addresses in the internal storage space of the system on chip are used as the addresses to be accessed.

7. The chip verification method according to claim 4, characterized in that: The joint test action team functional verification of the chip circuit is performed to obtain the verification result of the chip in the electronic design automation simulation stage, including: The accuracy of the readable and writable control registers of the system on chip is obtained by accessing the readable and writable control registers of the system on chip based on the debugging interface of the joint test action team.

8. A chip verification device, characterized in that: The chip verification device comprises: A simulation unit, used to simulate the chip using an electronic design automation simulation tool to obtain a chip circuit including a debugging interface of the joint test action team; The verification unit is used to perform joint test action team functional verification on the chip circuit to obtain the verification result of the chip in the electronic design automation simulation stage.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is executed by a processor, the steps of the chip verification method according to any one of claims 1 to 7 are implemented.

10. A computer program product, characterized in that It comprises a computer program, and when the computer program is executed, the steps of the chip verification method according to any one of claims 1 to 7 are implemented.

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