Gate driver

Abstract

A gate driver is provided. The gate driver includes a plurality of stages, each stage including: a first transistor including a first electrode and a second electrode connected to a first control node; a third transistor including a first electrode connected to the first control node and a second electrode connected to the second control node; a fifth transistor including a gate electrode connected to the inverting control node and a second electrode connected to the gate output node; a sixth transistor including a gate electrode connected to the second control node and a second electrode connected to the gate output node; a seventh transistor including a first electrode and a second electrode connected to the first control node; and an eighth transistor including a gate electrode receiving an aging signal, a first electrode receiving an aging voltage, and a second electrode connected to the first electrode of the first transistor.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure relate to a gate driver. More particularly, aspects of embodiments of the present disclosure relate to a gate driver for preventing or substantially preventing leakage current of a transistor to improve reliability. Background Art

[0002] Generally, a display device may include a display panel and a display panel driver. The display panel may include a gate line, a data line, and a pixel circuit. The display panel driver may include a gate driver for providing a gate signal to the gate line, a data driver for providing a data voltage to the data line, and a drive controller for controlling the gate driver and the data driver.

[0003] According to the level of the voltage applied to the transistor of the gate driver, the leakage current may flow through some of the plurality of transistors. When the leakage current flows in the gate driver, the reliability of the gate driver may be reduced.

[0004] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0005] Embodiments of the present disclosure may relate to a gate driver having improved reliability.

[0006] According to one or more embodiments of the present disclosure, a gate driver includes a plurality of stages, each of which includes: a first transistor, the first transistor including: a gate electrode configured to receive a clock signal; a first electrode configured to receive an input signal; and a second electrode connected to a first control node; a third transistor, the third transistor including: a gate electrode configured to receive a low gate voltage; a first electrode connected to the first control node; and a second electrode connected to the second control node; a fifth transistor, the fifth transistor including: a gate electrode connected to an inverting control node; a first electrode configured to receive a high gate voltage; and a second electrode connected to a gate output node configured to output a gate signal; a sixth transistor, the sixth transistor including: a gate electrode connected to the second control node; a first electrode configured to receive a low gate voltage; and a second electrode connected to the gate output node; a seventh transistor, the seventh transistor including: a gate electrode configured to receive a global control signal; a first electrode configured to receive a high gate voltage; and a second electrode connected to the first control node; and an eighth transistor, the eighth transistor including: a gate electrode configured to receive an aging signal; a first electrode configured to receive an aging voltage; and a second electrode connected to the first electrode of the first transistor.

[0007] In an embodiment, each of the plurality of stages may further include: a first capacitor comprising a first electrode connected to a second control node and a second electrode connected to a gate output node; and a second capacitor comprising a first electrode configured to receive a high gate voltage and a second electrode connected to an inverting control node.

[0008] In an embodiment, each of the plurality of stages may further include a second transistor including: a gate electrode connected to the first control node; a first electrode configured to receive a high gate voltage; and a second electrode connected to the inverting control node.

[0009] In an embodiment, each of the plurality of stages may further include a fourth transistor including: a gate electrode connected to the second control node; a first electrode configured to receive a low gate voltage; and a second electrode connected to the inverting control node.

[0010] In an implementation, the fourth transistor may be an N-type transistor, and the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be P-type transistors.

[0011] In an implementation, the aging voltage may be greater than a low voltage level of the clock signal and a low voltage level of the low gate voltage.

[0012] In an embodiment, in the first reset period, the global control signal may have a high voltage level, the clock signal may have a low voltage level, the low gate voltage may have a low voltage level, and the aging signal may have a low voltage level.

[0013] In an embodiment, in a first reset period, the eighth transistor may be configured to provide an aging voltage to a first electrode of the first transistor, the first transistor may be configured to provide a voltage of the first electrode of the first transistor to a first control node, and the third transistor may be configured to provide a voltage of the first control node to a second control node.

[0014] In an embodiment, in a first aging period after the first reset period, the global control signal may have a low voltage level, the clock signal may have a high voltage level, the low gate voltage may have a low voltage level, and the aging signal may have a low voltage level.

[0015] According to some embodiments of the present disclosure, in a gate driver, an aging operation may be performed on the first transistor and the third transistor to prevent or substantially prevent leakage current, thereby improving the reliability of the gate driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure;

[0018] Figure 2 The diagram is included in Figure 1 A block diagram of a gate driver in a display device;

[0019] Figure 3 The diagram is included in Figure 2 A circuit diagram of an example of a stage in a gate driver;

[0020] Figure 4 It is a graphic Figure 3 A timing diagram of an example of an aging operation of a stage;

[0021] Figure 5 It is shown in Figure 4 The first reset period of operation Figure 3 A timing diagram of an example of a level;

[0022] Figure 6 It is shown in Figure 4 The first reset period of operation Figure 3 A circuit diagram of an example of a stage;

[0023] Figure 7 It is shown in Figure 4 The first aging period of operation Figure 3 A timing diagram of an example of a level;

[0024] Figure 8 It is shown in Figure 4 The first aging period of operation Figure 3 A circuit diagram of an example of a stage;

[0025] Fig. 9 It is shown in Figure 4 The second reset period of operation Figure 3 A timing diagram of an example of a level;

[0026] Fig.10 It is shown in Figure 4 The second reset period of operation Figure 3 A circuit diagram of an example of a stage;

[0027] Fig.11 It is shown in Figure 4 The second aging period of Figure 3 A timing diagram of an example of a level;

[0028] Fig.12 It is shown in Figure 4 The second aging period of Figure 3 A circuit diagram of an example of a stage;

[0029] Fig.13 It is a graphic Figure 3 A timing diagram of an example of an aging operation of a stage;

[0030] Fig.14 The diagram is included in Figure 2 A circuit diagram of an example of a stage in a gate driver;

[0031] Fig.15 It is a graphic Fig.14 A timing diagram of an example of an aging operation of a stage;

[0032] Fig.16 It is shown in Fig.15 The reset period of the Fig.14 A timing diagram of an example of a level;

[0033] Fig.17 It is shown in Fig.15 The reset period of the Fig.14 A circuit diagram of an example of a stage;

[0034] Fig.18 It is shown in Fig.15 The aging period of the Fig.14 A timing diagram of an example of a level;

[0035] Fig.19 It is shown in Fig.15 The aging period of the Fig.14 A circuit diagram of an example of a stage;

[0036] Fig. 20 is a block diagram illustrating an electronic device; and

[0037] Fig.21 The diagram is implemented as a smart phone Fig. 20 An example view of an electronic device. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, wherein similar reference numerals refer to similar elements throughout. However, the present disclosure may be embodied in various different forms and should not be understood as being limited to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be comprehensive and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, in order to fully understand the aspects and features of the present disclosure, processes, elements and techniques that are not necessary for those of ordinary skill in the art may not be described. Unless otherwise stated, similar reference numerals represent similar elements throughout the drawings and written descriptions, and therefore, their redundant descriptions may not be repeated.

[0039] When a specific embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0040] In addition, as will be appreciated by those of ordinary skill in the art, considering the present disclosure as a whole, multiple suitable features of the various embodiments of the present disclosure may be partially or completely combined or combined with each other, and may be technically interlocked and operated in various suitable ways, and the various embodiments may be implemented independently of each other or in combination with each other in any suitable manner, unless otherwise stated or implied.

[0041] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and zones can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "beneath", "below", "lower", "under", "above", "upper" etc. can be used in this article to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It will be understood that spatial relative terms are intended to include different orientations of the device in use or in operation except the orientation depicted in the figure. For example, if the device in the figure is turned over, the element described as "below" or "below" or "below" of other elements or features will be oriented to "above" of other elements or features. Therefore, the example terms "below" and "below" can include two orientations above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0042] In the figure, the x-axis, y-axis and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0043] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the first element, component, region, layer or section described below can be referred to as a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0044] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, the layer, region, or element can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements therebetween. In addition, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0045] The terms used herein are used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "includes", "including", "has", "have" and "having" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" means A, B or A and B. When a statement such as "at least one of..." follows a column of elements, it modifies the entire column of elements and does not modify the individual elements in the list. For example, the expressions "at least one of a, b or c", "at least one of a, b and c", and "at least one selected from the group consisting of a, b and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0046] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations of measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined in this article.

[0048] Figure 1 is a block diagram illustrating a display device 10 according to one or more embodiments of the present disclosure.

[0049] refer to Figure 1 The display device 10 may include a display panel 110 and a display panel driver. The display panel driver may include a driving controller 120, a gate driver 130, a gamma reference voltage generator 140, and a data driver 150.

[0050] The display panel 110 may include a display area for displaying an image and a peripheral area adjacent to the display area.

[0051] The display panel 110 may include gate lines GL, data lines DL, and pixels P electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction, and the data lines DL may extend in a second direction crossing the first direction.

[0052] The driving controller 120 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0053] The driving controller 120 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0054] The driving controller 120 may generate a first control signal CONT1 for controlling the operation of the gate driver 130 based on the input control signal CONT, and may output the first control signal CONT1 to the gate driver 130. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0055] The driving controller 120 may generate a second control signal CONT2 for controlling the operation of the data driver 150 based on the input control signal CONT, and may output the second control signal CONT2 to the data driver 150. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0056] The driving controller 120 may generate a data signal DATA based on the input image data IMG. The driving controller 120 may output the data signal DATA to the data driver 150.

[0057] The driving controller 120 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 140 based on the input control signal CONT, and may output the third control signal CONT3 to the gamma reference voltage generator 140 .

[0058] The gate driver 130 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 120. The gate driver 130 may output the gate signal to the gate line GL.

[0059] The gamma reference voltage generator 140 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 120. The gamma reference voltage generator 140 may provide the gamma reference voltage VGREF to the data driver 150. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0060] In an implementation, the gamma reference voltage generator 140 may be disposed in the driving controller 120 , or may be disposed in the data driver 150 .

[0061] The data driver 150 may receive the second control signal CONT2 and the data signal DATA from the driving controller 120, and may receive the gamma reference voltage VGREF from the gamma reference voltage generator 140. The data driver 150 may convert the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 150 may output the data voltage to the data line DL.

[0062] Figure 2 The diagram is included in Figure 1 1 is a block diagram of a gate driver 130 in a display device 10.

[0063] refer to Figure 1 and Figure 2 , the gate driver 130 may include a first stage STAGE1, a second stage STAGE2, a third stage STAGE3, a fourth stage STAGE4, ​​etc., which receive a gate start signal FLM and a clock signal CLK, and may output a first gate signal GS1, a second gate signal GS2, a third gate signal GS3, a fourth gate signal GS4, etc. The first stage STAGE1 may receive the gate start signal FLM as an input signal. Each of the subsequent second stage STAGE2, the third stage STAGE3, the fourth stage STAGE4, ​​etc. may receive the first gate signal GS1, the second gate signal GS2, the third gate signal GS3, the fourth gate signal GS4, etc., of at least one corresponding previous stage as an input signal.

[0064] For example, Figure 2As shown in, the first stage STAGE1, the second stage STAGE2, the third stage STAGE3 and the fourth stage STAGE4 can sequentially output the first gate signal GS1, the second gate signal GS2, the third gate signal GS3 and the fourth gate signal GS4 in one frame period. The first stage STAGE1 can output the first gate signal GS1 based on the gate start signal FLM. The second stage STAGE2 can output the second gate signal GS2 based on the first gate signal GS1. The third stage STAGE3 can output the third gate signal GS3 based on the second gate signal GS2. The fourth stage STAGE4 can output the fourth gate signal GS4 based on the third gate signal GS3.

[0065] Figure 3 The diagram is included in Figure 2 FIG. 1 is a circuit diagram of an example of the gate driver 130 in the stage 200 .

[0066] refer to Figures 1 to 3 , the gate driver 130 may include a plurality of stages 200. Each stage 200 may include a first transistor T1, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0067] The first transistor T1 may include a gate electrode for receiving a clock signal CLK, a first electrode for receiving an input signal, and a second electrode connected to the first control node NQ1. The input signal may be a gate start signal FLM or a previous gate signal PGS. The gate start signal FLM may be a signal for starting the operation of the first stage STAGE1 among the plurality of stages 200. The previous gate signal PGS may be a gate signal GS output from any one of the plurality of previous stages. The first transistor T1 may provide the input signal to the first control node NQ1 in response to the clock signal CLK.

[0068] The third transistor T3 may include a gate electrode for receiving the low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. The third transistor T3 may provide the voltage of the first control node NQ1 to the second control node NQ2.

[0069] The fifth transistor T5 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the gate output node NGS at which the gate signal GS is output. The fifth transistor T5 may provide the high gate voltage VGH to the gate output node NGS in response to the voltage of the inverting control node NQB.

[0070] The sixth transistor T6 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the gate output node NGS. The sixth transistor T6 may provide the low gate voltage VGL to the gate output node NGS in response to the voltage of the second control node NQ2.

[0071] The seventh transistor T7 may include a gate electrode for receiving the global control signal ESR, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the first control node NQ1. The seventh transistor T7 may provide the high gate voltage VGH to the first control node NQ1 in response to the global control signal ESR.

[0072] The eighth transistor T8 may include a gate electrode for receiving the aging signal AS, a first electrode for receiving the aging voltage VA, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may provide the aging voltage VA to the first electrode of the first transistor T1 in response to the aging signal AS.

[0073] In an embodiment, each stage 200 may further include a first capacitor C1 and a second capacitor C2 .

[0074] The first capacitor C1 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the gate output node NGS. The first capacitor C1 may stabilize a voltage of the second control node NQ2.

[0075] The second capacitor C2 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the inversion control node NQB. The second capacitor C2 may reduce distortion of a waveform of the gate signal GS.

[0076] In an implementation, each stage 200 may further include a second transistor T2 .

[0077] The second transistor T2 may include a gate electrode connected to the first control node NQ1, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the inversion control node NQB. The second transistor T2 may provide the high gate voltage VGH to the inversion control node NQB in response to the voltage of the first control node NQ1.

[0078] In an implementation, each stage 200 may further include a fourth transistor T4 .

[0079] The fourth transistor T4 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the inversion control node NQB. The fourth transistor T4 may provide the low gate voltage VGL to the inversion control node NQB in response to the voltage of the second control node NQ2.

[0080] In an embodiment, the fourth transistor T4 may be an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be PMOS transistors, and the fourth transistor T4 may be an NMOS transistor.

[0081] In order to make the sixth transistor T6 including the first electrode for receiving the low gate voltage VGL provide the low gate voltage VGL to the gate output node NGS in response to the voltage of the second control node NQ2, the voltage of the second control node NQ2 may be at least less than VGL-|VTH|, where VGL is the low gate voltage and |VTH| is the absolute value of the threshold voltage of the sixth transistor T6. However, a leakage path may be formed by the first transistor T1 and the third transistor T3, a leakage current may flow through the leakage path, and the voltage of the second control node NQ2 may increase. When the voltage of the second control node NQ2 increases, the waveform of the gate signal GS may be distorted. In each stage 200, an aging operation may be performed on the first transistor T1 and the third transistor T3 to prevent or substantially prevent leakage current. The aging operation refers to an operation of applying stress to a transistor that is turned off in advance. When the aging operation is performed on the transistor, even if the transistor is used, a change in the characteristics of the transistor may be prevented or substantially prevented, and leakage current may be prevented or substantially prevented. The aging operation will be described in more detail below.

[0082] Figure 4 It is a graphic Figure 3 A timing diagram of an example of an aging operation of stage 200.

[0083] refer to Figures 1 to 4 , when the aging signal AS has a low voltage level, the aging operation may be performed.

[0084] In the first reset period RP1 , the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0085] In the first aging period AP1 after the first reset period RP1 , the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0086] In the second reset period RP2 after the first aging period AP1 , the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0087] In the second aging period AP2 after the second reset period RP2 , the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a high voltage level, and the aging signal AS may have a low voltage level.

[0088] Figure 5 It is shown in Figure 4 The first reset period RP1 of the operation Figure 3 An example timing diagram of stage 200 is shown. Figure 6 It is shown in Figure 4 The first reset period RP1 of the operation Figure 3 200 is an example circuit diagram of the stage.

[0089] refer to Figures 1 to 6 , in the first reset period RP1 , the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0090] The eighth transistor T8 may be turned on in response to the aging signal AS having a low voltage level. The eighth transistor T8 may provide the aging voltage VA to the first electrode of the first transistor T1, and the first electrode of the first transistor T1 may have the aging voltage VA.

[0091] The first transistor T1 may be turned on in response to the clock signal CLK having a low voltage level. The first transistor T1 may provide a voltage of a first electrode of the first transistor T1 to a first control node NQ1, and the first control node NQ1 may provide an aging voltage VA.

[0092] The third transistor T3 may be turned on in response to the low gate voltage VGL having a low voltage level. The third transistor T3 may provide the voltage of the first control node NQ1 to the second control node NQ2, and the second control node NQ2 may have the aging voltage VA.

[0093] Therefore, in the first reset period RP1 , the first electrode of the first transistor T1 , the first control node NQ1 , and the second control node NQ2 may be reset to the aging voltage VA.

[0094] In an embodiment, the aging voltage VA may be greater than the low voltage level of the clock signal CLK and the low voltage level of the low gate voltage VGL. Therefore, the threshold voltages of the first transistor T1 and the third transistor T3 may be prevented or substantially prevented from decreasing.

[0095] Figure 7 It is shown in Figure 4 The first aging period of AP1 is Figure 3 An example timing diagram of stage 200 is shown. Figure 8 It is shown in Figure 4 The first aging period of AP1 is Figure 3 200 is an example circuit diagram of the stage.

[0096] refer to Figures 1 to 8 , in the first aging period AP1, the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0097] The first transistor T1 may be turned off in response to the clock signal CLK having a high voltage level.

[0098] The eighth transistor T8 may be turned on in response to the aging signal AS having a low voltage level. The eighth transistor T8 may provide the aging voltage VA to the first electrode of the first transistor T1, and the first electrode of the first transistor T1 may have the aging voltage VA.

[0099] The seventh transistor T7 may be turned on in response to the global control signal ESR having a low voltage level. The seventh transistor T7 may provide a high gate voltage VGH to the first control node NQ1, and the first control node NQ1 may have the high gate voltage VGH.

[0100] Therefore, the first transistor T1 may be turned off, the gate-source voltage of the first transistor T1 may have a positive value, and the drain-source voltage of the first transistor T1 may have a positive value, so that an aging operation may be performed on the first transistor T1.

[0101] Fig. 9 It is shown in Figure 4 The second reset period RP2 is operated Figure 3 An example timing diagram of stage 200 is shown. Fig.10 It is shown in Figure 4 The second reset period RP2 is operated Figure 3 200 is an example circuit diagram of the stage.

[0102] The operation of the stage 200 in the second reset period RP2 may be the same or substantially the same as the operation of the stage 200 in the first reset period RP1.

[0103] refer to Figures 1 to 10 , in the second reset period RP2 , the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0104] The eighth transistor T8 may be turned on in response to the aging signal AS having a low voltage level. The eighth transistor T8 may provide the aging voltage VA to the first electrode of the first transistor T1, and the first electrode of the first transistor T1 may have the aging voltage VA.

[0105] The first transistor T1 may be turned on in response to the clock signal CLK having a low voltage level. The first transistor T1 may provide a voltage of a first electrode of the first transistor T1 to the first control node NQ1, and the first control node NQ1 may have an aging voltage VA.

[0106] The third transistor T3 may be turned on in response to the low gate voltage VGL having a low voltage level. The third transistor T3 may provide the voltage of the first control node NQ1 to the second control node NQ2, and the second control node NQ2 may have the aging voltage VA.

[0107] Therefore, in the second reset period RP2 , the first electrode of the first transistor T1 , the first control node NQ1 , and the second control node NQ2 may be reset to the aging voltage VA.

[0108] Fig.11 It is shown in Figure 4 The second aging period AP2 is operated Figure 3 An example timing diagram of stage 200 is shown. Fig.12 It is shown in Figure 4 The second aging period AP2 is operated Figure 3 200 is an example circuit diagram of the stage.

[0109] refer to Figures 1 to 12 , in the second aging period AP2, the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a high voltage level, and the aging signal AS may have a low voltage level.

[0110] The third transistor T3 may be turned off in response to the low gate voltage VGL having a high voltage level.

[0111] The seventh transistor T7 may be turned on in response to the global control signal ESR having a low voltage level. The seventh transistor T7 may provide a high gate voltage VGH to the first control node NQ1, and the first control node NQ1 may have the high gate voltage VGH.

[0112] Therefore, the third transistor T3 may be turned off, the gate-source voltage of the third transistor T3 may have a positive value, and the drain-source voltage of the third transistor T3 may have a positive value, so that an aging operation may be performed on the third transistor T3.

[0113] An aging operation may be performed on the first transistor T1 and the third transistor T3 so that a leakage current may be prevented or substantially prevented, and reliability of the gate driver 130 may be improved.

[0114] The aging operation for the first transistor T1 and the third transistor T3 may be performed during the process. However, when the display device 10 is driven, the leakage current may increase again. Therefore, even during the driving process of the display device 10, the aging operation for the first transistor T1 and the third transistor T3 may be performed.

[0115] Fig.13 It is a graphic Figure 3 A timing diagram of an example of an aging operation of stage 200.

[0116] refer to Figures 1 to 13 , as referenced above Figures 4 to 12 As described above, after performing an aging operation on the first transistor T1, an aging operation may be performed on the third transistor T3. As another example, Fig.13 As shown in , after performing the aging operation on the third transistor T3 , the aging operation may be performed on the first transistor T1 .

[0117] like Fig.13 As shown in , in the first reset period RP1 , the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0118] In an embodiment, in the first aging period AP1 after the first reset period RP1 , the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a high voltage level, and the aging signal AS may have a low voltage level.

[0119] In an embodiment, in the second reset period RP2 after the first aging period AP1 , the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0120] In an embodiment, in the second aging period AP2 after the second reset period RP2 , the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0121] Therefore, the aging operation may be performed on the third transistor T3 in the first aging period AP1 , and the aging operation may be performed on the first transistor T1 in the second aging period AP2 .

[0122] Fig.14 The diagram is included in Figure 2 FIG. 1 is a circuit diagram of an example of a gate driver 130 in stage 300 .

[0123] refer to Figure 1 , Figure 2 and Fig.14 , the gate driver 130 may include a plurality of stages 300. Each stage 300 may include a first transistor T1, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0124] The first transistor T1 may include a gate electrode for receiving a clock signal CLK, a first electrode for receiving an input signal, and a second electrode connected to the first control node NQ1. The input signal may be a gate start signal FLM or a previous gate signal PGS. The gate start signal FLM may be a signal for starting the operation of the first stage STAGE1 among the plurality of stages 300. The previous gate signal PGS may be a gate signal GS output from any one of the plurality of previous stages. The first transistor T1 may provide the input signal to the first control node NQ1 in response to the clock signal CLK.

[0125] The third transistor T3 may include a gate electrode for receiving the low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2. The third transistor T3 may provide the voltage of the first control node NQ1 to the second control node NQ2.

[0126] The fifth transistor T5 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the gate output node NGS at which the gate signal GS is output. The fifth transistor T5 may provide the high gate voltage VGH to the gate output node NGS in response to the voltage of the inverting control node NQB.

[0127] The sixth transistor T6 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the gate output node NGS. The sixth transistor T6 may provide the low gate voltage VGL to the gate output node NGS in response to the voltage of the second control node NQ2.

[0128] The seventh transistor T7 may include a gate electrode for receiving the global control signal ESR, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the first control node NQ1. The seventh transistor T7 may provide the high gate voltage VGH to the first control node NQ1 in response to the global control signal ESR.

[0129] The eighth transistor T8 may have a gate electrode for receiving the aging signal AS, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may provide the low gate voltage VGL to the first electrode of the first transistor T1 in response to the aging signal AS.

[0130] In an embodiment, each stage 300 may further include a first capacitor C1 and a second capacitor C2 .

[0131] The first capacitor C1 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the gate output node NGS. The first capacitor C1 may stabilize a voltage of the second control node NQ2.

[0132] The second capacitor C2 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the inversion control node NQB. The second capacitor C2 may reduce distortion of a waveform of the gate signal GS.

[0133] In an implementation, each stage 300 may further include a second transistor T2 .

[0134] The second transistor T2 may include a gate electrode connected to the first control node NQ1, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the inversion control node NQB. The second transistor T2 may provide the high gate voltage VGH to the inversion control node NQB in response to the voltage of the first control node NQ1.

[0135] In an implementation, each stage 300 may further include a fourth transistor T4 .

[0136] The fourth transistor T4 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the inversion control node NQB. The fourth transistor T4 may provide the low gate voltage VGL to the inversion control node NQB in response to the voltage of the second control node NQ2.

[0137] In an embodiment, the fourth transistor T4 may be an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be PMOS transistors, and the fourth transistor T4 may be an NMOS transistor.

[0138] Fig.15 It is a graphic Fig.14 A timing diagram of an example of an aging operation of stage 300 is shown.

[0139] refer to Figure 1 , Figure 2 , Fig.14 and Fig.15 , when the aging signal AS has a low voltage level, the aging operation may be performed.

[0140] In the reset period RP, the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0141] In the aging period AP after the reset period RP, the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a high voltage level, and the aging signal AS may have a low voltage level.

[0142] Fig.16 It is shown in Fig.15 The reset period RP is operated Fig.14 An example timing diagram of stage 300 is shown. Fig.17 It is shown in Fig.15 The reset period RP is operated Fig.14 1 is a circuit diagram of an example of stage 300.

[0143] refer to Figure 1 , Figure 2 as well as Figures 14 to 17, in the reset period RP, the global control signal ESR may have a high voltage level, the clock signal CLK may have a low voltage level, the low gate voltage VGL may have a low voltage level, and the aging signal AS may have a low voltage level.

[0144] The eighth transistor T8 may be turned on in response to the aging signal AS having a low voltage level. The eighth transistor T8 may provide a low voltage level of a low gate voltage VGL to the first electrode of the first transistor T1, and the first electrode of the first transistor T1 may have a low voltage level of the low gate voltage VGL.

[0145] The first transistor T1 may be turned on in response to the clock signal CLK having a low voltage level. The first transistor T1 may provide a voltage of a first electrode of the first transistor T1 to the first control node NQ1, and the first control node NQ1 may have a low voltage level of a low gate voltage VGL.

[0146] The third transistor T3 may be turned on in response to the low gate voltage VGL having a low voltage level. The third transistor T3 may provide the voltage of the first control node NQ1 to the second control node NQ2, and the second control node NQ2 may have a low voltage level of the low gate voltage VGL.

[0147] Therefore, in the reset period RP, the first electrode of the first transistor T1 , the first control node NQ1 , and the second control node NQ2 may be reset to a low voltage level of the low gate voltage VGL.

[0148] Fig.18 It is shown in Fig.15 The aging period of the AP is Fig.14 An example timing diagram of stage 300 is shown. Fig.19 It is shown in Fig.15 The aging period of the AP is Fig.14 1 is a circuit diagram of an example of stage 300.

[0149] refer to Figure 1 , Figure 2 as well as Figures 14 to 19 , in the aging period AP, the global control signal ESR may have a low voltage level, the clock signal CLK may have a high voltage level, the low gate voltage VGL may have a high voltage level, and the aging signal AS may have a low voltage level.

[0150] The first transistor T1 may be turned off in response to the clock signal CLK having a high voltage level, and the third transistor T3 may be turned off in response to the high voltage level of the low gate voltage VGL.

[0151] The eighth transistor T8 may be turned on in response to the aging signal AS having a low voltage level. The eighth transistor T8 may provide a high voltage level of the low gate voltage VGL to the first electrode of the first transistor T1, and the first electrode of the first transistor T1 may have a high voltage level of the low gate voltage VGL.

[0152] The seventh transistor T7 may be turned on in response to the global control signal ESR having a low voltage level. The seventh transistor T7 may provide a high gate voltage VGH to the first control node NQ1, and the first control node NQ1 may have the high gate voltage VGH.

[0153] Therefore, the first transistor T1 can be turned off, the gate-source voltage of the first transistor T1 can have a positive value, and the drain-source voltage of the first transistor T1 can have a positive value, so that the aging operation can be performed on the first transistor T1. Additionally, the third transistor T3 can be turned off, the gate-source voltage of the third transistor T3 can have a positive value, and the drain-source voltage of the third transistor T3 can have a positive value, so that the aging operation can be performed on the third transistor T3.

[0154] An aging operation may be performed on the first transistor T1 and the third transistor T3 so that a leakage current may be prevented or substantially prevented, and reliability of the gate driver 130 may be improved.

[0155] Fig. 20 is a block diagram illustrating an electronic device 1000 . Fig.21 The diagram is implemented as a smart phone Fig. 20 FIG. 1 is a diagram of an example of an electronic device 1000 .

[0156] refer to Fig. 20 and Fig.21 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be the above reference Figure 1 The display device 10 described herein. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0157] In an embodiment, if Fig.21 As shown in the figure, the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.

[0158] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be connected to (e.g., coupled to) other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be connected to (e.g., coupled to) an expansion bus such as a peripheral component interconnect (PCI) bus.

[0159] The memory device 1020 may store data for operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0160] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like.

[0161] I / O devices 1040 may include input devices such as keyboards, keys, mouse devices, touch pads, touch screens, etc. and output devices such as printers, speakers, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0162] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0163] Display device 1060 may be connected to other components via a bus or other communication links.

[0164] The embodiments of the present disclosure described above can be applied to any suitable display device and any suitable electronic device including a touch panel. For example, the embodiments of the present disclosure can be applied to mobile phones, smart phones, digital televisions (TVs), 3D TVs, personal computers (PCs, such as tablet computers, laptop computers), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0165] The above are examples of some embodiments of the present disclosure and are not to be construed as limitations thereto. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications to the embodiments are possible without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects in each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, it is to be understood that the above are examples of various example embodiments and are not to be construed as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined by the accompanying claims and their equivalents.

Claims

1. A gate driver, the gate driver comprising a plurality of stages, each of the plurality of stages comprising: A first transistor, the first transistor comprising: a gate electrode configured to receive a clock signal, a first electrode configured to receive an input signal, and a second electrode connected to the first control node; A third transistor, the third transistor comprising: a gate electrode configured to receive a low gate voltage, a first electrode connected to the first control node, and a second electrode connected to a second control node; A fifth transistor, the fifth transistor comprising: The gate electrode connected to the inverting control node, a first electrode configured to receive a high gate voltage, and a second electrode connected to a gate output node configured to output a gate signal; A sixth transistor, the sixth transistor comprising: a gate electrode connected to the second control node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the gate output node; A seventh transistor, the seventh transistor comprising: a gate electrode configured to receive a global control signal, a first electrode configured to receive the high gate voltage, and a second electrode connected to the first control node; and An eighth transistor, the eighth transistor comprising: a gate electrode configured to receive an aging signal, a first electrode configured to receive an aging voltage, and A second electrode connected to the first electrode of the first transistor.

2. The gate driver according to claim 1, wherein: Each of the plurality of stages further comprises: A first capacitor, the first capacitor comprising: a first electrode connected to the second control node, and a second electrode connected to the gate output node; and A second capacitor, the second capacitor comprising: a first electrode configured to receive the high gate voltage, and A second electrode connected to the inverting control node.

3. The gate driver according to claim 2, wherein: Each of the plurality of stages further comprises: A second transistor, the second transistor comprising: a gate electrode connected to the first control node; a first electrode configured to receive the high gate voltage; and A second electrode connected to the inverting control node.

4. The gate driver according to claim 3, wherein: Each of the plurality of stages further comprises: A fourth transistor, the fourth transistor comprising: a gate electrode connected to the second control node; a first electrode configured to receive the low gate voltage; and A second electrode connected to the inverting control node.

5. The gate driver according to claim 4, wherein: The fourth transistor is an N-type transistor, and the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors.

6. The gate driver according to claim 1, wherein: The aging voltage is greater than a low voltage level of the clock signal and a low voltage level of the low gate voltage.

7. The gate driver according to claim 1, wherein: In a first reset period, the global control signal has a high voltage level, the clock signal has a low voltage level, the low gate voltage has a low voltage level, and the aging signal has a low voltage level.

8. The gate driver according to claim 7, wherein: In the first reset period, the eighth transistor is configured to provide the aging voltage to the first electrode of the first transistor, the first transistor is configured to provide the voltage of the first electrode of the first transistor to the first control node, and the third transistor is configured to provide the voltage of the first control node to the second control node.

9. The gate driver according to claim 7, wherein: In a first aging period after the first reset period, the global control signal has a low voltage level, the clock signal has a high voltage level, the low gate voltage has the low voltage level, and the aging signal has the low voltage level.

10. The gate driver according to claim 9, wherein: During the first aging period, the seventh transistor is configured to provide the high gate voltage to the first control node, and the eighth transistor is configured to provide the aging voltage to the first electrode of the first transistor.

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