Semiconductor device and writing method

Abstract

The invention relates to a semiconductor device and a writing method. It is possible to reduce access time from a CPU to a register while preventing software from becoming complicated. A semiconductor device includes: a decoder circuit that determines a write source processor; a write enable setting storage circuit storing a write enable setting indicating that the processor is capable of performing a write to each bit of the write destination register; a masking / merging circuit generating a value to be written back into the write destination register based on the write enable setting and the write source processor; and a write-back circuit that writes back the value to be written back into the write destination register.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Japanese Provisional Application No. 2023-184433, filed on October 27, 2023, the disclosure of which is incorporated herein by reference. Background Art

[0003] The present invention relates to a semiconductor device that performs data writing, and to a writing method.

[0004] In recent years, it has been required to install multiple CPUs (central processing units) on semiconductor devices such as vehicle-mounted microcomputers to continuously execute safety-related functions even if any failure occurs. Safety-related functions include functions to avoid a series of failures when accessing shared resource registers from multiple CPUs. In the shared resource registers installed on the vehicle-mounted microcomputer, one register may include bit parts that can be accessed from multiple CPUs.

[0005] The disclosed techniques are listed below.

[0006] [Patent Document 1] International Patent Publication No. 2010 / 029682

[0007] In the related art, only the enable bit portion can be rewritten by the read-modify-write method. For example, Patent Document 1 discloses a technology related to an information processor that performs the read-modify-write method.

[0008] However, the execution of the read-modify-write method requires an arbitration process for stopping access from a CPU different from the CPU accessing the register and multiple access processes and arithmetic processes based on the read-modify-write method. Therefore, this method has the problem of software complication and increased access time from the CPU to the register.

[0009] The complication of software and the increase in access time from the CPU have become causes of increased software development man-hours and reduced performance of in-vehicle microcomputers. Therefore, the need for functions and systems that avoid a series of failures based on hardware has increased. Such functions and systems are called FFI (Freedom Interface) and are required by ISO26262. Summary of the invention

[0010] As described above, it is desirable to reduce the access time from the CPU to the register while preventing the software from being complicated.

[0011] Other objects and novel features will be apparent from the description of this specification and the accompanying drawings.

[0012] According to one embodiment, a semiconductor device includes: a decoder circuit that determines a write source processor; a write enable setting storage circuit that stores a write enable setting indicating that the processor is able to perform a write to each bit of a write destination register; a masking / merging circuit that generates a value to be written back to the write destination register based on the write enable setting and the write source processor; and a write-back circuit that writes the value to be written back to the write destination register.

[0013] According to one embodiment, a write method includes: a step of determining a write source processor; a step of generating a value to be written back to a write destination register based on the write source processor and a write enable setting indicating that the processor is able to perform a write to each bit of the write destination register; and a step of writing the value to be written back to the write destination register.

[0014] According to the embodiment, it is possible to reduce the access time from the CPU to the register while preventing the complication of software. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic circuit diagram showing the configuration of a semiconductor device according to a first embodiment.

[0016] Figure 2 is a schematic circuit diagram showing the configuration of a decoder circuit according to the first embodiment.

[0017] Figure 3 is a schematic circuit diagram showing a write enable setting circuit according to the first embodiment.

[0018] Figure 4 is a schematic circuit diagram showing the configuration of a masking / combining circuit according to the first embodiment.

[0019] Figure 5 is a timing chart showing the operation of the decoder circuit according to the first embodiment.

[0020] Figure 6 is a timing chart showing the operation of the masking / combining circuit according to the first embodiment.

[0021] Figure 7 is a timing chart showing the operation of the write-back circuit according to the first embodiment.

[0022] Figure 8 is a diagram for explaining the configuration of a semiconductor device according to the second embodiment.

[0023] Fig. 9 is a schematic circuit diagram showing a configuration of a write-back circuit according to a second embodiment.

[0024] Fig.10is a timing chart for explaining the operation of the write-back circuit according to the second embodiment. DETAILED DESCRIPTION

[0025] For the sake of clarity of explanation, the following description and drawings are appropriately omitted and simplified. Each of the elements of the functional blocks that are respectively illustrated in the drawings as performing various types of processing can be configured by a CPU, a memory or another circuit in hardware, or by executing a program loaded in a memory in software, etc. to achieve. Therefore, it will be understood by those skilled in the art that the functional blocks can be implemented in various forms by hardware, software operating on hardware, or a combination thereof, and are not limited to any one form. In each of the drawings, the same elements are represented by the same reference symbols, respectively, and their descriptions are not repeated as needed.

[0026] The program includes a command group (or software code) for causing the computer to perform one or more functions explained in the embodiment when loaded into the computer. The program can be stored in a non-transient computer-readable medium or a tangible storage medium. Computer-readable media or tangible storage media may include, for example, random access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD), other memory technologies, CD-ROM, digital versatile disk (DVD), Blu-ray (registered trademark) optical disk, other optical disk storage devices, cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, but are not limited thereto. The program can be sent on a transient computer-readable medium or a communication medium. Transient computer-readable media or communication media include, for example, electrical, optical, acoustic and other forms of propagation signals, but are not limited thereto.

[0027] First embodiment

[0028] Figure 1 is a schematic circuit diagram showing the configuration of the semiconductor device 100 according to the first embodiment. PWDATA[31:0], bus slave selection signals PSEL0 to PSEL7, and PADDR[31:0] are input from the write source processor 200 to the semiconductor device 100 through the APB (Advanced Peripheral Bus) bus interface IF. PWDATA[31:0] is also referred to as write data. PADDR[31:0] is also referred to as a bus address. The bus slave selection signals PSEL0 to PSEL7 correspond to ID0 to ID7 of the write source processor. Note that the number of IDs can be two or more and 6 or less, or 8 or more. Then, the semiconductor device 100 performs a write to the write destination register 310 of the write destination module 300 through the APB bus interface IF.

[0029] The semiconductor device 100 includes a decoder circuit 110 , a write enable setting storage circuit 120 , a masking / merging circuit 130 , and a write-back circuit 140 .

[0030] As input, the decoder circuit 110 receives bus slave select signals PSEL0 to PSEL7 and PADDR[31:0]. The bus slave select signal PSEL indicates the write source processor 200. The decoder circuit 110 identifies the write source processor 200.

[0031] The decoder circuit 110 stores information (also referred to as MASK_CON) regarding whether a masking process is to be performed on each bit written to the destination register 310. For example, if a masking process is not performed on a bit, all processors may be able to write data to the bit.

[0032] The decoder circuit 110 generates a decoded ID (also referred to as a decoded signal) based on MASK_CON and bus slave selection signals PSEL0 to PSEL7 , and outputs the decoded ID to the masking / merging circuit 130 .

[0033] Furthermore, the decoder circuit 110 outputs PSEL_OUT based on PSEL0 to PSEL7 to the write-back circuit 140. Note that a more detailed configuration of the decoder circuit 110 will be described later.

[0034] The write enable setting storage circuit 120 stores a write enable setting indicating that the processor can perform writing to each bit of the write destination register 310. The write enable setting storage circuit 120 may include, for example, three flip-flops corresponding to each bit. Therefore, ID0 to ID7 of the processor 200 may be expressed. The write enable setting of each bit is also referred to as SFR_ID[2:0]. Note that the detailed configuration of the write enable setting storage circuit 120 will be described later.

[0035] The masking / merging circuit 130 generates a value to be written back to the write destination register 310 based on the write enable setting and the write source processor 200. Specifically, the masking / merging circuit 130 can generate a value to be written back to the write destination register 310 for each bit based on the write enable setting and the decode ID. The masking / merging circuit 130 includes, for example, a masking circuit 131, a masking circuit 132, an OR circuit 133, and a comparator circuit 134. Each of the masking circuits 131 and 132 is made of, for example, an AND circuit or the like. The masking circuit 131 outputs the data to be written (such as PWDATA

[31] ) to the OR circuit 133 based on the instruction of the comparator circuit 134. The masking circuit 132 outputs the data of the bit (such as bit31) that has been written to the write destination register 310 based on the instruction of the comparator circuit 134. The comparator circuit 134 operates the masking circuits 131 and 132 based on the decode ID and the SFR_ID. Note that the detailed configuration of the masking / merging circuit 130 will be described later.

[0036] The write-back circuit 140 writes back the value to be written back for each bit input from the masking / merging circuit 130 to the write destination register 310. Note that the write-back circuit 140 may include a selector for selecting PWDATA[31:0] and the value to be written back based on PSEL_OUT. The write-back circuit 140 also outputs PWDATA[31:0], PSEL, and PADDR[31:0] to the write destination module 300.

[0037] Reference Figure 2 , a detailed configuration of the decoder circuit 110 will be described. The decoder circuit 110 includes a comparator circuit 111, a selector 112, a signal generator 113, and a selector 114.

[0038] The comparator circuit 111 compares PADDR[18:16] included in the address bus PADDR[19:0] with the binary data PSEL_ID[2:0] of the bus slave selection signals PSEL0 to PSEL7. PADDR[18:16] is a bit indicating the write source processor 200. The comparator circuit 111 outputs the comparison result to the selectors 112 and 114.

[0039] As input, for each PADDR[15:0], selector 112 receives MASK_CON[31:0] indicating whether a masking process is to be performed on each bit. Note that "H" may be added to the end of hexadecimal, while "B" may be added to the end of the following binary.

[0040] If PADDR[15:0] is "0000 H ", MASK_CON[31:0] is expressed as, for example, "01...01 B ”. The value “1” indicates that the masking process is valid, and the value “0” indicates the always writable state. If PADDR[15:0] is “0001 H ””, MASK_CON[31:0] is expressed as “00…11 B If PADDR[15:0] is "1FFF H ", MASK_CON[31:0] is expressed as "00...000 B ”. If the signals compared by the comparator circuit 111 are equal, the selector 112 outputs MASK_CON[31:0] corresponding to PADDR[15:0] to the signal generator 113.

[0041] The signal generator 113 generates a decoding ID [3:0] [31:0] while using MASK_CON [31:0] and PSEL_ID [2:0]. If each bit of MASK_CON [31:0] is 0, the signal generator 113 sets "the decoding ID [3:0] [] corresponding to the bit = 8 H If each bit of MASK_CON[31:0] is 1, the signal generator 113 sets the decoded ID[3:0][] corresponding to the bit to be decoded = {0 B +PSEL_ID[2:0]}". For example, if PADDR is "0001 H ", MASK_CON[31:0] is "00…11 B ", and PSEL_ID[2:0] is "1 H In this case, decoded ID[3:0][31:0] is "88…11 H ”.

[0042] If each bit of MASK_CON[31:0] is 0, it can also be said that the signal generator 113 replaces the bit with a predetermined bit such as 8. If each bit of MASK_CON[31:0] is 1, it can also be said that the signal generator 113 replaces the bit with PSEL_ID.

[0043] As input, selector 114 receives PSEL0 to PSEL7 and outputs a signal fixed to 1. If the signals compared by comparator circuit 111 are not equal, selector 114 outputs 1 as PSEL_OUT. If the signals compared by comparator circuit 111 are equal, selector 114 outputs PSEL_OUT corresponding to PSEL0 to PSEL7. For example, if PSEL_ID[2][1][0] is "001", selector 114 outputs PSEL0. If PSEL_ID[2][1][0] is "010", selector 114 outputs PSEL1. If PSEL_ID[2][1][0] is "111", selector 114 outputs PSEL7.

[0044] The decoder circuit 110 has a function to output {0000} based on PADDR[15:0]. H +PADDR[15:0]}.

[0045] The decoder circuit 110 may reduce the probability of occurrence of erroneous writing by comparing PSEL_ID[2:0] and PADDR[18:16] using the comparator circuit 111 .

[0046] Reference Figure 3, the detailed configuration of the write enable setting storage circuit 120 will be explained. The write enable setting storage circuit 120 includes an APB bus decoder 121 and a storage device 122.

[0047] As input, the APB bus decoder 121 receives PSEL, PADDR[31:0], PWDATA[31:0], and PWRITE through the APB bus interface IF. PWRITE is a signal indicating whether to perform writing. PRDATA[31:0] is output from the APB bus decoder 121 through the APB bus interface IF.

[0048] The storage device 122 includes three flip-flops FF for each bit. The three flip-flops FF store a write enable setting (also referred to as SRF_ID[2:0]), indicating the ID of the processor that can perform writing to the bit. The storage device 122 outputs SRF_ID[2:0] for each of bit0 to bit31. The write enable setting can be set by the APB bus decoder 121.

[0049] Reference Figure 4 , the detailed configuration of the masking / merging circuit 130 will be explained. The masking / merging circuit 130 includes a masking / merging circuit 130_0 for bit0, ..., a masking / merging circuit 130_30 for bit30, and a masking / merging circuit 130_31 for bit31. The masking / merging circuit 130_31 will be specifically explained, and the detailed explanation of the masking / merging circuits 130_0 to 130_30 will be omitted.

[0050] The masking / merging circuit 130_31 includes an AND circuit 131, an AND circuit 132, an OR circuit 133, and a comparator circuit 134. The AND circuit 131 receives as inputs PWDATA

[31] and AB_OUT, which is the output of the comparator circuit 134. The AND circuit 132 receives as inputs the register value

[31] written to the destination register 310 and the negation of AB_OUT, which is the output of the comparator circuit 134. The OR circuit 133 generates a write-back register value

[31] written to the destination register 310 by performing an OR operation between the output of the AND circuit 131 and the output of the AND circuit 132.

[0051] As inputs, the comparator circuit 134 receives “A=Decoded ID[3:0]

[31] ” and “B={0 B + SFR_ID[2:0]}", then, if "A=B" or "A=8 H " If the condition is not met, then the comparator circuit 134 outputs "AB_OUT=1". If the condition is not met, in particular, if "A≠B" holds, then the comparator circuit 134 outputs "AB_OUT=0".

[0052] For example, in the case of "MASK_CON

[31] = 0", since the masking process is not performed, "Decoding ID[3:0]

[31] = 8 H " holds, so "AB_OUT=1" holds, and PWDATA

[31] is written back. Alternatively, even in the case of "MASK_CON

[31] =1", if PSEL_ID[2:0]

[31] and SFR_ID[2:0]

[31] are equal to each other, "AB_OUT=1" holds, and PWDATA

[31] is written back. If the above conditions are not met, "AB_OUT=0" holds, and therefore, the register value

[31] written to the destination register 310 is written back.

[0053] The same processing is also performed in the masking / merging circuits 130_0, ..., and 130_30. Therefore, the write-back register value [0], ..., the write-back register value

[30] , and the write-back register value

[31] are output.

[0054] Next, refer to Figures 5 to 7 , the operation of the semiconductor device 100 will be explained.

[0055] Figure 5 1 is a timing diagram showing the operation of the decoder circuit 110. The decoder circuit 110 determines whether PADDR[19:16] extracted from the address PADDR[19:0] accessed by the user is equal to PSEL_ID[2:0] indicating PSEL0 to PSEL7. For example, if PADDR[19:16] is "0001 B ", and PSEL_ID[2:0] is 1 H , it can be determined that PADDR[19:16] is equal to PSEL_ID[2:0]. Based on this, the decoder circuit 110 determines whether the access is the user's intended access.

[0056] The decoder circuit 110 selects information about whether to perform a masking process on each bit of the write destination register 310 based on PADDR[15:0] indicating the address of the write destination register 310, and outputs the information as MASK_CON[31:0]. As illustrated by the dotted arrow 21, the decoder circuit 110 replaces the "1" included in MASK_CON[31:0] with PSEL_ID[2:0], and replaces the "0" included in MASK_CON[31:0] with "8", and outputs the resulting data as decoding ID[3:0][31:0]. As illustrated by the dotted arrow 22, the decoder circuit 110 outputs PSERL_OUT corresponding to PSEL0 to PSEL7. Further, as illustrated by the dotted arrow 23, the decoder circuit 110 outputs "0000 B +PADDR[15:0]” as PADDR_OUT[19:0].

[0057] Figure 6 is a timing diagram showing the operation of the masking / merging circuit 130. The masking / merging circuit 130 determines for each bit whether the condition that the decoded ID [3:0] is 8 or the decoded ID [3:0] is equal to SFR_ID [2:0] is satisfied. The masking / merging circuit 130 writes the PWDATA of the bit to the write-back register value of the bit that satisfies the condition.

[0058] For example, the first to fourth bits from the left side of the decoded ID [3:0] [31:0] are "8888 H ”, and PWDATA and the write-back register values ​​are equal to each other, as illustrated by arrow 31. For the same reason, PWDATA “0011 B " is equal to the write-back register value "0011 B ”, as illustrated by arrow 32.

[0059] Furthermore, the ninth to twelfth bits on the left side of the decoded ID [3:0] [31:0] are "1111 H ", and the corresponding bits of SFR_ID[2:0][31:0] are also "1111 H Therefore, as shown by the dashed arrow 33, PWDATA "0110 B " is equal to the write-back register value "0110 B ”. Similarly, the second to fourth bits on the right side of the decoded ID [3:0] [31:0] are “111 H ", and the second to fourth bits on the right side of SFR_ID[2:0][31:0] are also "111 H ””. Therefore, as illustrated by the dashed arrow 34, PWDATA “110B " is equal to the write-back register value "100 B ”.

[0060] The masking / merging circuit 130 writes the write destination register value of the bit into the write back register value of the bit that does not meet the condition. Moreover, the fifth to eighth bits on the left side of the decoded ID [3:0] [31:0] are "1111 H ", and the corresponding bits of SFR_ID[2:0][31:0] are "2222 H Therefore, as shown by the dashed arrow 35, the destination register value "0000" is written. B ” and write back the register value “0000 B ” are equal to each other. Similarly, the first bit on the right side of the decoded ID [3:0] [31:0] is “0 H ", and the first bit on the right side of SFR_ID[2:0][31:0] is "1 H ”, so they are not equal to each other. Therefore, as illustrated by the dotted arrow 36, the write destination register value “0” and the write back register value “0” are equal to each other.

[0061] Figure 7 is a timing diagram showing the operation of the write-back circuit 140. The decoder circuit 110 has generated PADDR_OUT[15:0], in which the bits related to the write source processor 200 have been removed. As illustrated by the dotted arrow 41, the write-back circuit 140 generates PADDR[31:0] based on PADDR_OUT[15:0] and PADDR[31:20], that is, the combination of PADDR_OUT[19:0], and outputs PADDR[31:0] to the write destination module 300. Moreover, as illustrated by the dotted arrow 42, the write-back circuit 140 outputs the write-back register value [31:0] as PWDATA[31:0] to the write destination module 300. Moreover, as illustrated by the dotted arrow 43, the write-back circuit 140 generates PSEL based on PSEL_OUT, and outputs PSEL to the write destination module 300.

[0062] The semiconductor device 100 according to the first embodiment can control writing from a plurality of processors to a write destination module 300 by identifying a write source processor 200 and using a write enable setting. This does not require dedicated control using software and register reading for write back.

[0063] In the semiconductor device 100, the access time from the CPU can be reduced while preventing the complication of the software. Moreover, even if the software is modified, the function of avoiding a series of failures can be maintained.

[0064] Second embodiment

[0065] The second embodiment is a modified example of the first embodiment. Figure 8 , the configuration of the semiconductor device 100a according to the second embodiment will be explained. Figure 1 and 8 In the comparison between them, PSEL (privilege) indicating that the write source processor 200 is privileged is output to the write back circuit 140. If the write source processor 200 is privileged, the semiconductor device 100a outputs PADDR[31:0] and PWDATA[31:0] to the write destination module 300 without passing through the masking / merging circuit 130.

[0066] Reference Fig. 9 , a detailed configuration of the write-back circuit 140 according to the second embodiment will be explained. The write-back circuit 140 includes selectors 141 to 143.

[0067] If PSEL (privilege) is active, the selector 141 selects PSEL (privilege) and outputs the privilege to the write destination module 300. If PSEL (privilege) is active, the selector 142 selects PWDATA [31: 0] and outputs PWDATA [31: 0] to the write destination module 300. If PSEL (privilege) is active, the selector 143 selects PADDR [31: 0] and outputs PADDR [31: 0] to the write destination module 300.

[0068] Fig.10 is a timing diagram showing the operation of the write-back circuit 140 according to the second embodiment. If PSEL (privilege) is active, as illustrated by a dotted arrow 51, not the write-back register value [31:0] but PWDATA [31:0] is output to the write destination module 300. Moreover, as illustrated by a dotted arrow 52, ​​PADDR [31:0] is output to the write destination module 300. Further, as illustrated by a dotted arrow 53, PSEL (privilege) is output to the write destination module 300.

[0069] The semiconductor device 100 a according to the second embodiment can give a privileged mode in which a masking process is not performed to the write source CPU, and thus can systematically control access rights to registers.

[0070] In the foregoing, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor device comprising: A decoder circuit determines a write source processor; a write enable setting storage circuit storing a write enable setting indicating that the processor is enabled to perform writing to each bit of a write destination register; a masking / merging circuit that generates a value to be written back into the write destination register based on the write enable setting and the write source processor; as well as The write-back circuit writes the value to be written back into the write destination register.

2. The semiconductor device according to claim 1, wherein the decoder circuit receives as input a bus address and a bus slave select signal corresponding to the write source processor, The bus address includes a bit indicating the write source processor, and The decoder circuit determines whether a bit included in the bus address and the bus slave select signal are equal to each other.

3. The semiconductor device according to claim 1, in, If the masking process for each bit of the write destination register is invalid, the decoder circuit replaces the bit with a predetermined bit to generate a decoded signal, or If the masking process for the bit is effective, the decoder circuit replaces the bit with a bit indicative of the write source processor to generate the decoded signal.

4. The semiconductor device according to claim 3, in, If the bit is equal to the predetermined bit, or a condition indicating that the bit of the write source processor is equal to the write enable setting is satisfied, the masking / merging circuit generates the value to be written back based on the write data supplied from the write source processor, or If the condition is not satisfied, the masking / merging circuit generates the value to be written back based on the data written in the write destination register.

5. The semiconductor device according to claim 1, in, If the write source processor is privileged, the bus address and write data are not output through the masking / merging circuit.

6. A writing method, comprising the following steps: Determine the write source processor; generating a value to be written back into the write destination register based on the write source processor and a write enable setting indicating that a processor is enabled to perform a write to each bit of the write destination register; as well as The value to be written back is written back to the write destination register.

7. The writing method according to claim 6, in, If the write source processor is privileged, the bus address and write data are not output through the step of generating the value to be written back.

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