Line detection method, device and equipment

Abstract

The invention provides a line detection method, device and equipment, and is applied to the technical field of chips, and the method comprises the steps: transmitting a preset input signal to a storage chip according to a preset frequency; and extracting a test signal determined by the storage chip according to the preset input signal from the cache region of the storage chip. And comparing the test signal with a preset input signal input in line detection to obtain a defect position of the memory chip. And determining the defect type corresponding to the defect position based on the defect position according to the state of the test signal in the preset time period, and generating a line detection report of the storage chip, so that the problems of insufficient detection time, relatively low detection efficiency and relatively high cost existing in a line detection scheme at present can be solved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a circuit detection method, device and equipment. Background Art

[0002] With the rapid development of memory chip technology, its packaging technology is becoming increasingly complex. However, during the packaging process, the integrity of the circuit is affected by many factors (such as material defects, processing errors, process instability, etc.), which may lead to short circuits, open circuits, signal attenuation and other problems. These problems are more easily magnified in mass production, which in turn leads to a decrease in product yield and reliability. In related technologies, circuit detection is mainly concentrated before or during packaging, and is performed through optical microscopes, scanning electron microscopes (SEMs) and other equipment. However, these methods have defects such as insufficient detection time, low detection efficiency and high cost. Summary of the invention

[0003] The purpose of the present application is to provide a line detection method, device and equipment to solve the problems of insufficient detection time, low detection efficiency and high cost in current line detection solutions.

[0004] In the first aspect, an embodiment of the present application provides a line detection method, which is applied to a line detection device, the line detection device is used to detect a packaged memory chip, the line detection device is connected to the memory chip through a communication line, and the method includes: sending a preset input signal to the memory chip at a preset frequency. Extracting a test signal determined by the memory chip according to the preset input signal from a buffer area of ​​the memory chip. Comparing the test signal with the preset input signal input in the line detection, the defect position of the memory chip is obtained. Based on the defect position, according to the state of the test signal within a preset time period, the defect type corresponding to the defect position is determined, and a line detection report of the memory chip is generated.

[0005] The circuit detection method provided in the embodiment of the present application uses digital signal analysis and defect recognition algorithms to quickly discover potential circuit problems, avoid the expansion of large-scale packaging defects, improve production yield and chip reliability, and reduce overall production costs.

[0006] In a possible implementation, the memory chip includes at least one data line, and the test signal is compared with a preset input signal input in the line detection to obtain the defect position of the memory chip, including: comparing the test signal with the preset signal input in the line detection to determine the defect signal in the test signal. According to the defect signal, the defect position of the data line generating the defect signal is determined from the memory chip.

[0007] A possible implementation method is to determine the defect type corresponding to the defect location based on the defect location and according to the state of the test signal within a preset time period, including: based on the defect location, using a trained neural network model to perform defect identification on the state of the test signal in a preset time period to obtain the defect type corresponding to the defect location.

[0008] A possible implementation method is to use a trained neural network model to identify the state of the test signal in a preset time period based on the defect location to obtain the defect type corresponding to the defect location, including: determining the state of the test signal at each time node in the preset time period according to the defect location. Determine the defect type corresponding to the defect location according to the change trend of the state of the test signal in the preset time period.

[0009] In a possible implementation, the line detection method provided in the embodiment of the present application further includes: obtaining key performance indicators of the storage chip under actual working conditions within a preset time period through the communication line, and predicting defect data of the storage chip according to the change trend of the key performance indicators.

[0010] In a possible implementation, the communication line includes a physical read / write line, and the method further includes: sending a read / write instruction to a storage chip, and receiving read / write information determined by the storage chip based on the read / write instruction. According to the read / write information, determining the state of the physical read / write line. Adding the state of the physical read / write line to a line detection report.

[0011] In a possible implementation, the line detection device is connected to the main control chip in communication, and the main control chip is connected to the storage chip in communication. The method also includes: sending an information acquisition instruction to the main control chip, and receiving a unique identifier of the main control chip sent by the main control chip. Sending an information acquisition instruction to the storage chip, and receiving a unique identifier of the storage chip sent by the storage chip. According to the unique identifier of the main control chip and the unique identifier of the storage chip, determining the model of the main control chip, the number of storage chips connected to the main control chip, and the model of the storage chip, and adding the model of the main control chip, the number of storage chips connected to the main control chip, and the model of the storage chip to the line detection report.

[0012] In a second aspect, the present application provides a circuit detection device, which is applied to a circuit detection device, the circuit detection device is used to detect a packaged memory chip, and the circuit detection device is connected to the memory chip via a communication line. The device includes: a sending module, an extraction module, a comparison module, and a generation module.

[0013] The sending module is used to send a preset input signal to the storage chip at a preset frequency.

[0014] The extraction module is used to extract the test signal determined by the storage chip according to the preset input signal from the buffer area of ​​the storage chip.

[0015] The comparison module is used to compare the test signal with the preset input signal input in the line detection to obtain the defect position of the storage chip.

[0016] The generation module is used to determine the defect type corresponding to the defect position based on the defect position and the state of the test signal within a preset time period, and generate a circuit detection report for the storage chip.

[0017] In a third aspect, an embodiment of the present application provides a line detection device, which has the function of implementing the line detection method of the first aspect or any possible implementation method. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, the computer can execute the line detection method of the first aspect or any possible implementation method mentioned above.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the line detection method of the first aspect or any possible implementation method described above.

[0020] Among them, the technical effects brought about by any design method in the second to fifth aspects can refer to the technical effects brought about by different possible implementation methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the structure of a line detection device provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the structure of a line detection system provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of a flow chart of a line detection method provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the structure of a line detection device provided in an embodiment of the present application;

[0026] Figure 5 Another structural schematic diagram of a line detection system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0029] At present, the detection of circuits in memory chips is mainly concentrated before or during packaging, and is carried out through optical microscopes, scanning electron microscopes (SEMs) and other equipment. However, these methods have the following problems: insufficient detection time, low detection efficiency and high detection cost. For example, the relevant technology mainly detects before the packaging is completed, and the hidden circuit problems that may arise after packaging (such as circuit breaks caused by thermal stress) cannot be discovered in time. Traditional methods rely on manual inspection or large-scale equipment inspection, which is difficult to meet the needs of mass production. High-precision equipment and manual operation lead to high detection costs, especially when one by one needs to be inspected.

[0030] Based on this, an embodiment of the present application provides a line detection method, which is applied to a line detection device, the line detection device is used to detect the packaged memory chip, the line detection device is connected to the memory chip through a communication line, and the method includes: sending a preset input signal to the memory chip at a preset frequency. Extracting a test signal determined by the memory chip according to the preset input signal from the buffer area of ​​the memory chip. Comparing the test signal with the preset input signal input in the line detection, the defect position of the memory chip is obtained. Based on the defect position, according to the state of the test signal within a preset time period, the defect type corresponding to the defect position is determined, and a line detection report of the memory chip is generated.

[0031] The circuit detection method provided in the embodiment of the present application uses digital signal analysis and defect recognition algorithms to quickly discover potential circuit problems, avoid the expansion of large-scale packaging defects, improve production yield and chip reliability, and reduce overall production costs.

[0032] On the one hand, the embodiment of the present application provides a line detection device, such as Figure 1 As shown, the line detection device 100 may include a processor 101 and a memory 102 .

[0033] The processor 101 may include one or more processing units, for example, the processor 101 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0034] The memory 102 is used to store instructions and data. In some embodiments, the memory 102 may be a cache memory. The memory 102 may store instructions or data that have just been used or cyclically used by the processor 101. If the processor needs to use the instructions or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 101, and improves the efficiency of the line detection device.

[0035] It should be noted that the above Figure 1 The illustrated line detection device 100 is only an example of an application scenario of the solution of the present application, and is not intended to limit the application scenario of the solution of the present application.

[0036] On the one hand, an embodiment of the present application provides a line detection system, and the line detection system 200 may include: a line detection device 100, at least one storage chip 201 and a main control chip 202.

[0037] The storage chip 201 and the main control chip 202 may be connected via a communication line.

[0038] The circuit detection device 100 is specifically used to detect the defect position and defect type of at least one packaged memory chip 201 through the circuit detection method provided in the embodiment of the present application.

[0039] The memory chip 201 is a packaged memory chip.

[0040] It should be noted that the above Figure 2 The illustrated line detection system 200 is only an example of the application scenario of the solution of the present application, and is not intended to limit the application scenario of the solution of the present application.

[0041] On the one hand, the embodiment of the present application provides a line detection method, which can be deployed as follows Figure 1 The line detection device 100 shown in FIG. Figure 2 The line detection system 200 shown performs.

[0042] like Figure 3 As shown, the method includes:

[0043] S301, sending a preset input signal to a storage chip at a preset frequency.

[0044] Exemplarily, a preset input signal is sent to the memory chip at a preset frequency. The input signal may be, for example, an 8-byte signal of 11110000.

[0045] It should be noted that the present application does not limit the signal strength and frequency range of the preset input signal, and the preset input signal may include a square wave, a sine wave, random noise, etc.

[0046] The present application moves the timing of testing the memory chip to the finished product stage after packaging, thus making up for the deficiency of the traditional testing method in lacking effective means after packaging.

[0047] S302, extracting a test signal determined by the memory chip according to a preset input signal from a buffer area of ​​the memory chip.

[0048] Exemplarily, after receiving the preset input signal, the memory chip stores the preset input signal in the cache area of ​​the memory chip to obtain the test signal. The line detection device extracts the test signal from the cache area of ​​the memory chip, for example, the test signal is 11100000.

[0049] S303, comparing the test signal with a preset input signal input in line detection to obtain a defect position of the memory chip.

[0050] In a possible implementation, the memory chip includes at least one data line, and the test signal is compared with a preset signal input in the line detection to determine a defect signal in the test signal. According to the defect signal, the defect position of the data line generating the defect signal is determined from the memory chip.

[0051] For example, by comparing the test signal 11100000 with the preset input signal 11110000, it can be determined that the fourth bit of the signal in the test signal is different from the fourth bit of the signal in the preset input signal, and it can be determined that there is a problem with the data line corresponding to the fourth bit of the signal in the memory chip. This process can shorten the detection time of a single chip to milliseconds, greatly improving the detection efficiency of the chip.

[0052] S304, based on the defect location and according to the state of the test signal within a preset time period, determine the defect type corresponding to the defect location, and generate a circuit detection report of the memory chip.

[0053] A possible implementation method is to use a trained neural network model to identify the state of the test signal in a preset time period based on the defect location to obtain the defect type corresponding to the defect location.

[0054] Specifically, the state of the test signal at each time node in a preset time period is determined according to the defect position, and the defect type corresponding to the defect position is determined according to the change trend of the state of the test signal in the preset time period.

[0055] Exemplarily, the signal state of the test signal at each time node within a preset time period is recorded. According to the change trend of the signal state, the state change trend of the test signal within the preset time period is analyzed using a trained defect type detection model to automatically identify the defect type of the memory chip, such as short circuit, open circuit or signal attenuation.

[0056] A possible implementation method is to obtain key performance indicators of the memory chip under actual working conditions within a preset time period through a communication line, and predict the defect data of the memory chip according to the change trend of the key performance indicators.

[0057] Exemplarily, key performance indicators in the memory chip are monitored, such as the read and write speed, error rate or temperature of the memory chip, etc. The change trend of the key performance indicator in a preset time period is determined, and based on the change trend, the defect data of the memory chip is predicted to extract and warn of possible problems of the memory chip.

[0058] In a possible implementation, the communication line may include a physical read / write line. A read / write instruction is sent to a storage chip, and read / write information determined by the storage chip based on the read / write instruction is received. The state of the physical read / write line is determined according to the read / write information. The state of the physical read / write line is added to a line detection report.

[0059] Exemplarily, a read / write instruction is sent to the storage chip, and the storage chip receives read / write information determined based on the read / write instruction, compares the read / write information with the read / write instruction, determines the state of the physical read / write line in the communication line, and adds the state of the physical read / write line to the line detection report.

[0060] In a possible implementation, the line detection device is connected to the main control chip in communication, and the main control chip is connected to the storage chip in communication. An information acquisition instruction is sent to the main control chip, and a unique identifier of the main control chip sent by the main control chip is received. An information acquisition instruction is sent to the storage chip, and a unique identifier of the storage chip sent by the storage chip is received. According to the unique identifier of the main control chip and the unique identifier of the storage chip, the model of the main control chip, the number of storage chips connected to the main control chip, and the model of the storage chip are determined, and the model of the main control chip, the number of storage chips connected to the main control chip, and the model of the storage chip are added to the line detection report.

[0061] Exemplarily, the FlahID of the memory chip is read through a specific command, and the number of current memory chips is determined based on the read FlashID. If the currently packaged memory chip is single-chip selected, and the number of memory chips read shows that the current memory chip is dual-chip selected, it is determined that the number of current memory chips does not meet the packaging requirements, and the number of memory chips is written into the line detection report.

[0062] At the same time, the matching of the model of the packaged main control chip and the model of the storage chip is checked. If the matching of the current model of the main control chip and the model of the storage chip is 2982+V7, the model of the main control chip is detected as 2982 through the unique identifier of the main control chip, and the model of the main control chip is detected as V8 through the unique identifier of the storage chip, then the matching of the main control chip and the storage chip does not meet the packaging standard at this time, and the model of the main control chip and the model of the storage chip are added to the line detection report, and it is marked that the model of the main control chip and the model of the storage chip do not match directly at this time.

[0063] The circuit detection method provided in the embodiment of the present application only detects the storage chip and the main control chip through the circuit detection device, and can be dynamically adjusted according to different processes, materials and packaging forms, thereby improving the scope of application of the circuit detection method.

[0064] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the working principle of the line detection device. It can be understood that in order to realize the above functions, the line detection device includes a hardware structure and / or software module corresponding to each function. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiment disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0065] The embodiment of the present application can divide the functional modules of the line detection device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processor. The above integrated module can be implemented in the form of hardware or software functional module.

[0066] It should be noted that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. Figure 4 FIG. 2 shows a possible schematic diagram of the circuit detection device involved in the above-mentioned embodiments. Figure 4 As shown, the line detection device 400 may include: a sending module 401 , an extracting module 402 , a comparing module 403 and a generating module 404 .

[0067] The sending module 401 is used to support the line detection device 400 provided in the embodiment of the present application to perform the following Figure 3 S301 in the line detection method shown.

[0068] The extraction module 402 is used to support the line detection device 400 provided in the embodiment of the present application to perform the following Figure 3 S302 in the line detection method shown.

[0069] The comparison module 403 is used to support the line detection device 400 provided in the embodiment of the present application to perform the following Figure 3 S303 in the line detection method shown.

[0070] The generating module 404 is used to support the line detection device 400 provided in the embodiment of the present application to perform the following Figure 3 S304 in the line detection method shown.

[0071] In a possible implementation, the device is specifically used to compare the test signal with a preset signal input in line detection to determine a defect signal in the test signal and to determine the defect position of the data line generating the defect signal from the memory chip according to the defect signal.

[0072] In a possible implementation, the device is specifically used to identify defects based on the defect location by using a trained neural network model to identify the state of the test signal in a preset time period, and obtain the defect type corresponding to the defect location.

[0073] In a possible implementation, the device is specifically used to determine the state of the test signal at each time node within a preset time period according to the defect position. According to the change trend of the state of the test signal within the preset time period, the defect type corresponding to the defect position is determined. In a possible implementation, the device is specifically used to obtain the key performance indicators of the storage chip under actual working conditions within the preset time period through a communication line. According to the change trend of the key performance indicators, the defect data of the storage chip is predicted.

[0074] In a possible implementation, the device is specifically used to send a read / write instruction to a storage chip, and receive read / write information determined by the storage chip based on the read / write instruction, determine a physical read / write line state according to the read / write information, and add the physical read / write line state to a line detection report.

[0075] In a possible implementation, the device is specifically used to send an information acquisition instruction to a main control chip, and receive a unique identifier of the main control chip sent by the main control chip. Send an information acquisition instruction to a storage chip, and receive a unique identifier of the storage chip sent by the storage chip. According to the unique identifier of the main control chip and the unique identifier of the storage chip, determine the model of the main control chip, the number of storage chips connected to the main control chip, and the model of the storage chip, and add the model of the main control chip, the number of storage chips connected to the main control chip, and the model of the storage chip to a line detection report.

[0076] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0077] The line detection device 500 provided in the embodiment of the present application is used to perform the above Figure 3 The line detection method shown can therefore achieve the same effect as the above-mentioned line detection method.

[0078] The present application also provides a line detection device, which can be the line detection device described in the above embodiment. Figure 1 The line detection device 100 shown can execute the line detection method and related steps in the above method embodiment.

[0079] An embodiment of the present application also provides a computer-readable storage medium on which instructions are stored. When the instructions are executed, the line detection method and related steps in the above method embodiment are executed.

[0080] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer executes the line detection method and related steps in the above method embodiment.

[0081] In some embodiments, the methods described herein may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or encoded on other non-transitory media or articles of manufacture.

[0082] The present application also provides a line detection system 200, such as Figure 5 As shown, the line detection system 200 includes at least one processor 501 and at least one interface circuit 502 .

[0083] As an example, when the line detection system 200 includes a processor and an interface circuit, the processor may be Figure 5 The processor 501 shown in the solid line frame (or the processor 501 shown in the dotted line frame) may be Figure 5 The interface circuit 502 shown in the solid line frame (or the interface circuit 502 shown in the dotted line frame) is shown in the solid line frame. When the line detection system 200 includes two processors and two interface circuits, the two processors include Figure 5 The processor 501 shown in the solid line frame and the processor 501 shown in the dotted line frame, the two interface circuits include Figure 5 The interface circuit 502 shown in the solid line frame and the interface circuit 502 shown in the dotted line frame are not limited to this.

[0084] The processor 501 and the interface circuit 502 may be interconnected via a line. For example, the interface circuit 502 may be used to receive a signal. In another example, the interface circuit 502 may be used to send a signal to another device (e.g., the processor 501). For example, the interface circuit 502 may read a computer instruction stored in a memory and send the computer instruction to the processor 501. The processor 501 executes the instruction and implements the various steps in the above embodiments in combination with the input and output devices, such as implementing Figure 3 The various steps performed in the method embodiment shown. Of course, the line detection system 200 may also include other discrete components, which are not specifically limited in the embodiment of the present application.

[0085] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0086] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0087] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0088] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0089] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a line detection device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0090] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A line detection method, characterized in that: Applied to a circuit detection device, the circuit detection device is used to detect a packaged memory chip, the circuit detection device is connected to the memory chip via a communication line, and the method comprises: Sending a preset input signal to the storage chip at a preset frequency; extracting, from a buffer area of ​​the memory chip, a test signal determined by the memory chip according to the preset input signal; Comparing the test signal with a preset input signal input in the line detection to obtain a defect position of the memory chip; Based on the defect position and according to the state of the test signal within a preset time period, the defect type corresponding to the defect position is determined, and a circuit detection report of the memory chip is generated.

2. The method according to claim 1, characterized in that The memory chip includes at least one data line, and the test signal is compared with a preset input signal input in the line detection to obtain a defect position of the memory chip, including: Comparing the test signal with a preset signal input in the line detection to determine a defect signal in the test signal; According to the defect signal, a defect position of a data line generating the defect signal is determined from the memory chip.

3. The method according to claim 1, characterized in that The determining, based on the defect position and according to the state of the test signal within a preset time period, a defect type corresponding to the defect position includes: Based on the defect position, the trained neural network model is used to perform defect identification on the state of the test signal in a preset time period to obtain the defect type corresponding to the defect position.

4. The method according to claim 3, characterized in that The defect identification is performed on the state of the test signal in a preset time period using a trained neural network model based on the defect position to obtain a defect type corresponding to the defect position, including: Determining the state of the test signal at each time node within a preset time period according to the defect location; The defect type corresponding to the defect position is determined according to the change trend of the state of the test signal within the preset time period.

5. The method according to claim 1, characterized in that: The method further comprises: Acquiring key performance indicators of the storage chip under actual working conditions within a preset time period through the communication line; Defect data of the memory chip is predicted according to the change trend of the key performance indicator.

6. The method according to claim 1, characterized in that The communication line includes a physical read-write line, and the method further includes: Sending a read / write instruction to the storage chip, and receiving read / write information determined by the storage chip based on the read / write instruction; Determine the physical read / write circuit state according to the read / write information; The physical read / write line status is added to the line detection report.

7. The method according to claim 1, characterized in that The line detection device is connected to the main control chip for communication, and the main control chip is connected to the storage chip for communication; the method further includes: Sending an information acquisition instruction to the main control chip, and receiving a unique identifier of the main control chip sent by the main control chip; Sending an information acquisition instruction to the storage chip, and receiving a unique identifier of the storage chip sent by the storage chip; According to the unique identifier of the main control chip and the unique identifier of the storage chip, the model of the main control chip, the number of the storage chips connected to the main control chip and the model of the storage chip are determined, and the model of the main control chip, the number of the storage chips connected to the main control chip and the model of the storage chip are added to the line detection report.

8. A line detection device, characterized in that: Applied to a line detection device, the line detection device is used to detect a packaged memory chip, the line detection device is connected to the memory chip via a communication line, and the device comprises: A sending module, used for sending a preset input signal to the storage chip at a preset frequency; An extraction module, used for extracting a test signal determined by the storage chip according to the preset input signal from a buffer area of ​​the storage chip; A comparison module, used for comparing the test signal with a preset input signal input in the line detection to obtain a defect position of the memory chip; A generating module is used to determine the defect type corresponding to the defect position based on the defect position and the state of the test signal within a preset time period, and to generate a circuit detection report of the storage chip.

9. A line detection device, characterized in that: The line detection device comprises a processor and a memory, wherein the memory stores computer executable instructions that can be executed by the processor, and the processor executes the computer executable instructions to implement the line detection method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the line detection method according to any one of claims 1 to 7 is implemented.

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