Surface treatment method of semiconductor substrate

Abstract

The surface treatment method of the semiconductor substrate comprises the following steps: forming a silicon oxide layer on the surface of the semiconductor substrate; forming a transition layer on the silicon oxide layer; forming a silicon-based layer on the transition layer; and forming a gate insulating layer on the silicon-based layer. The gate insulating film with a stable structure can be formed on the semiconductor substrate, and the method is simple to operate, low in cost and high in production efficiency.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, and in particular to a surface treatment method for a semiconductor substrate. Background Art

[0002] In the semiconductor device manufacturing process, the gate insulation film is a critical step. Its main function is to prevent electron leakage and charge accumulation, and ensure the reliability and stability of the device.

[0003] In conventional low temperature polysilicon (LTPS) technology, the gate insulator (GI) film layer is made by chemical vapor deposition (CVD). However, the traditional method has problems such as complex preparation process, low production efficiency, and unstable film structure.

[0004] Therefore, it is urgent to provide an improved surface treatment method for semiconductor substrate to overcome the above defects. Summary of the invention

[0005] The object of the present invention is to provide an improved surface treatment method for a semiconductor substrate, which can form a gate insulating film with a stable structure on the semiconductor substrate, and the method is simple to operate, low in cost and high in production efficiency.

[0006] To achieve the above object, the surface treatment method of a semiconductor substrate of the present invention comprises the following steps:

[0007] forming a silicon oxide layer on a surface of a semiconductor substrate;

[0008] forming a transition layer on the silicon oxide layer;

[0009] forming a silicon-based layer on the transition layer; and

[0010] A gate insulating layer is formed on the silicon-based layer.

[0011] Compared with the prior art, the present invention first forms a silicon oxide layer on the surface of a semiconductor substrate, then forms a thinner transition layer on the silicon oxide layer, then forms a silicon base layer on the transition layer, and finally forms a gate insulating layer on the silicon base layer. Through the combination of the oxide layer, the transition layer, the silicon base layer and the gate insulating layer, the contact interface between the gate insulating layer as the surface layer and the substrate is stabilized, the bonding force is greatly enhanced, the stability is high, and it is not easy to fall off; moreover, such a formation method is simple to operate, can reduce production costs, and improve production efficiency.

[0012] As a preferred embodiment, before forming the silicon oxide layer, the semiconductor substrate is cleaned.

[0013] As a preferred embodiment, the silicon oxide layer and the silicon-based layer are formed by vapor deposition.

[0014] As a preferred embodiment, the vapor deposition includes chemical vapor deposition (CVD) and / or physical vapor deposition (PVD).

[0015] As a preferred embodiment, the chemical vapor deposition includes plasma enhanced chemical vapor deposition (PECVD).

[0016] As a preferred embodiment, the gate insulating layer includes at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0017] As a preferred embodiment, the gate insulating layer is formed by etching.

[0018] As a preferred embodiment, the thickness of the silicon oxide layer is 200-300 nm.

[0019] As a preferred embodiment, the transition layer is aluminum, and the thickness of the transition layer is 20-30 nm.

[0020] As a preferred embodiment, the thickness of the silicon-based layer is 400-500 nm, and the thickness of the gate insulating layer is 150-250 nm. DETAILED DESCRIPTION

[0021] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with some embodiments. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0022] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0024] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0025] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0026] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0027] The surface treatment method of the semiconductor substrate of the present invention is further described below in conjunction with the embodiments, but the present invention is not limited thereby. The method of the present invention is intended to provide a surface treatment method of a semiconductor substrate, which can form a gate insulating film with a stable structure on the semiconductor substrate, and the method is simple to operate, low in cost and high in production efficiency.

[0028] As an embodiment, the surface treatment method of a semiconductor substrate of the present invention comprises the following steps:

[0029] forming a silicon oxide layer on a surface of a semiconductor substrate;

[0030] forming a transition layer on the silicon oxide layer;

[0031] forming a silicon-based layer on the transition layer; and

[0032] A gate insulating layer is formed on the silicon-based layer.

[0033] The present invention first forms a silicon oxide layer on the surface of a semiconductor substrate, then forms a thinner transition layer on the silicon oxide layer, then forms a silicon-based layer on the transition layer, and finally forms a gate insulating layer on the silicon-based layer. Through the combination of the oxide layer, the transition layer, the silicon-based layer and the gate insulating layer, the contact interface between the gate insulating layer as the surface layer and the substrate is stabilized, the bonding force is greatly enhanced, the stability is high, and it is not easy to fall off; moreover, such a formation method is simple to operate, can reduce production costs, and improve production efficiency.

[0034] Specifically, as an embodiment, a wafer or a silicon chip is prepared as a semiconductor substrate, and contaminants on its surface are cleaned and removed to prepare for the subsequent formation of various layers.

[0035] Specifically, first, a silicon oxide layer is formed on a semiconductor substrate by vapor deposition, such as chemical vapor deposition or physical vapor deposition, with a thickness of 200-300 nm, for example, preferably 250 nm. Preferably, PECVD has the outstanding advantage of low deposition temperature, and the deposited film has excellent electrical properties, good substrate adhesion and excellent step coverage, so it is preferably used in the present invention.

[0036] Next, a transition layer is formed on the silicon oxide layer. The transition layer is preferably made of metal material, such as aluminum. The thickness is much smaller than the thickness of other layers, preferably 20-30 nm. The presence of the transition layer makes the interface contact between the films more stable.

[0037] Next, a silicon-based layer is formed on the transition layer with a thickness of 150-250 nm. Similarly, chemical vapor deposition such as PECVD as described above can be used, which is easier to operate. Of course, other chemical vapor deposition methods can also be used. Preferably, the thickness of the silicon-based layer is the largest between the layers, which is 400-500 nm, to facilitate the stability of the structure.

[0038] Finally, an etching technique is used to form a gate insulating layer on the silicon base layer. Preferably, the gate insulating layer includes at least one of silicon nitride, silicon oxide and silicon oxynitride. Specifically, a resist can be used, and after covering the resist with a corresponding mask and irradiating with light, a photolithography process is first used to pattern the resist, and then at least a portion of the silicon base layer is exposed through an etching step to finally obtain a gate insulating layer of a specific pattern. Preferably, the thickness of the gate insulating layer is 150-250nm.

[0039] In summary, the present invention stabilizes the contact interface between the gate insulating layer as the surface layer and the substrate through the combination of the oxide layer, the transition layer, the silicon-based layer and the gate insulating layer, greatly enhances the bonding force, has high stability and is not easy to fall off; moreover, such a formation method is simple to operate, can reduce production costs and improve production efficiency.

[0040] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A method for surface treatment of a semiconductor substrate, characterized in that: include: forming a silicon oxide layer on a surface of a semiconductor substrate; forming a transition layer on the silicon oxide layer; forming a silicon-based layer on the transition layer; as well as A gate insulating layer is formed on the silicon-based layer.

2. The surface treatment method of a semiconductor substrate according to claim 1, wherein: Before forming the silicon oxide layer, the semiconductor substrate is cleaned.

3. The surface treatment method of a semiconductor substrate according to claim 1, characterized in that: The silicon oxide layer and the silicon-based layer are formed by vapor deposition.

4. The surface treatment method of a semiconductor substrate as claimed in claim 3, characterized in that: The vapor deposition includes chemical vapor deposition (CVD) and / or physical vapor deposition (PVD).

5. The surface treatment method of a semiconductor substrate according to claim 4, characterized in that: The chemical vapor deposition includes plasma enhanced chemical vapor deposition (PECVD).

6. The surface treatment method of a semiconductor substrate according to claim 1, wherein: The gate insulating layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

7. The surface treatment method of a semiconductor substrate according to claim 1, wherein: The gate insulating layer is formed by etching.

8. The surface treatment method of a semiconductor substrate according to claim 1, wherein: The thickness of the silicon oxide layer is 200-300 nm.

9. The surface treatment method of a semiconductor substrate according to claim 1, wherein: The transition layer is aluminum, and the thickness of the transition layer is 20-30 nm.

10. The surface treatment method of a semiconductor substrate according to claim 1, wherein: The thickness of the silicon-based layer is 400-500 nm, and the thickness of the gate insulating layer is 150-250 nm.