Wafer gap positioning method and device, electronic equipment and storage medium

Abstract

The invention provides a wafer gap positioning method and device, electronic equipment and a storage medium, and the method comprises the steps: firstly carrying out the data sampling of a wafer gap meeting the SEMI standard, constructing a mathematical model, and packaging the mathematical model into a function module; then, positioning the target wafer gap by using the functional module to obtain first position information; and finally, performing precision correction on the first position information based on the circle center deviation value to obtain second position information, and correcting the target wafer gap according to the second position information. Through mathematical modeling and precision correction, efficient and accurate positioning is realized, and the wafer manufacturing quality and production efficiency are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a wafer notch positioning method, device, electronic device and storage medium. Background Art

[0002] Wafer refers to the silicon chip used in the production of silicon semiconductor integrated circuits. Because of its round shape, it is called a wafer. Wafer is the carrier used in the production of integrated circuits and is the most commonly used semiconductor material. It is divided into 6-inch and 8-inch specifications according to its diameter. In recent years, in order to meet the needs of semiconductor manufacturing, 12-inch and even larger wafers have been developed. As the size of wafers continues to increase, the requirements for wafer manufacturing processes are also constantly increasing.

[0003] There are usually notches on the wafer to provide reference marks and identify the type, doping and crystal orientation of the wafer during the manufacturing and processing of the wafer. As a reference mark, the notch can help determine the direction and position of the wafer. As the size of wafers continues to increase, in order to reduce waste, large-size wafers usually use U-shaped or V-shaped small openings (NORCH) instead of flat angles. As the chip manufacturing process becomes more and more advanced and precise, the positioning accuracy of wafer notches is also improved. In practical applications, the original positioning accuracy of 0.1° is currently required to reach 0.03° or higher. The existing notch positioning methods are: one is to use the edge change rate method to calculate the angle and set the threshold, which has a large amount of calculation and requires that the amplitude of the adjacent data collected cannot change too much; the other method uses the extreme value method to find the notch. Although it can meet most of the existing application requirements, it also has accuracy limitations when the accuracy requirements are constantly increasing. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a wafer notch positioning method, device, electronic device and storage medium, which achieve efficient and accurate positioning through mathematical modeling and precision correction, and effectively improve the quality and production efficiency of wafer manufacturing.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a wafer notch positioning method, the method comprising:

[0007] Sampling data of wafer notches that meet SEMI standards, building a mathematical model based on the sampled data, and encapsulating the mathematical model library into a functional module;

[0008] Acquire target sampling data for a target wafer notch, and input the target sampling data into the functional module, so that the functional module locates the target wafer notch based on the target sampling data to obtain first position information;

[0009] The first position information is subjected to precision correction processing based on the circle center offset value to obtain second position information, and the target wafer notch is corrected based on the second position information.

[0010] In a second aspect, an embodiment of the present application further provides a wafer notch positioning device, the device comprising:

[0011] A construction module is used to sample data of wafer notches that meet SEMI standards, construct a mathematical model based on the sampled data, and encapsulate the mathematical model library into a functional module;

[0012] A sampling module, used for acquiring target sampling data for a target wafer notch, and inputting the target sampling data into the functional module, so that the functional module locates the target wafer notch based on the target sampling data to obtain first position information;

[0013] The correction module is used to perform precision correction processing on the first position information based on the center offset value to obtain second position information, and correct the target wafer gap based on the second position information.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to execute the wafer notch positioning method described in any one of the first aspects.

[0015] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the wafer notch positioning method described in any one of the first aspects is executed.

[0016] The embodiments of the present application have the following beneficial effects:

[0017] Through data sampling and mathematical model construction, efficient and accurate positioning of wafer notches is achieved. By encapsulating the mathematical model library as a functional module and processing it based on the target sampling data, this method can quickly obtain the first position information of the wafer notch. Furthermore, the first position information is accurately corrected using the center offset value to obtain more accurate second position information, thereby effectively guiding the correction of the wafer notch and ensuring the high quality and production efficiency of wafer manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a flowchart of steps S101-S103 provided in an embodiment of the present application;

[0020] Figure 2 It is a flowchart of steps S201-S202 provided in an embodiment of the present application;

[0021] Figure 3 It is a flowchart of steps S301-S302 provided in an embodiment of the present application;

[0022] Figure 4 It is a correction principle diagram provided in an embodiment of the present application;

[0023] Figure 5 It is a structural schematic diagram of a wafer notch positioning device provided in an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram of the composition structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0025] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0026] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0028] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0029] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0031] See also Figure 1 , Figure 1 is a flow chart of steps S101-S103 of the wafer notch positioning method provided in the embodiment of the present application, which will be combined with Figure 1 Steps S101-S103 are shown for explanation.

[0032] In step S101, data sampling is performed on wafer notches that comply with the SEMI standard, a mathematical model is constructed based on the sampled data, and the mathematical model library is encapsulated as a functional module.

[0033] Here, we first sample the wafer notches that meet the SEMI standard. The SEMI standard stipulates that there must be a small notch on the edge of the wafer, which can be arc-shaped or straight-line. During the sampling process, it is necessary to ensure the density and accuracy of the sampling points so that an accurate mathematical model can be constructed later. Based on the sampled data, a mathematical model describing the wafer notch characteristics is constructed. This model can be based on geometric shapes, image features, or other mathematical methods. The constructed mathematical model will be used in the subsequent positioning and correction process.

[0034] In some embodiments, the step of sampling data of wafer notches that comply with the SEMI standard and constructing a mathematical model based on the sampled data includes:

[0035] Place wafers of different specifications at the center of the calibrator respectively;

[0036] Data sampling is performed through a CCD laser edge detection sensor;

[0037] The notch edge information is modeled based on the sampled data.

[0038] Here, select wafers that meet SEMI standards and have uniform sizes and specifications. Wafers of different specifications (such as wafers with different diameters or different thicknesses) need to be placed and calibrated separately. Place the wafer in the center of the calibrator and ensure that the contact surface between the wafer and the calibrator is flat and free of contamination.

[0039] The CCD (charge coupled device) laser edge detection sensor is used to sample the wafer notch data. The CCD sensor has the characteristics of high sensitivity and high resolution, and can accurately capture the edge information of the wafer notch. The sensor emits a laser beam and scans the edge of the wafer notch. The reflected light generated by the interaction between the laser beam and the edge of the wafer notch is received by the sensor and converted into an electrical signal. After amplification and digital processing, the electrical signal forms sampling data that can be used for subsequent analysis.

[0040] The sampled data is preprocessed, including steps such as removing noise and smoothing data. Based on the preprocessed sampled data, the edge information of the wafer notch is modeled. The output of the model can accurately describe the edge shape, size and other characteristics of the wafer notch.

[0041] In step S102, target sampling data is acquired for a target wafer notch, and the target sampling data is input into the functional module, so that the functional module locates the target wafer notch based on the target sampling data to obtain first position information.

[0042] Here, the constructed mathematical model library is encapsulated as a functional module. This module can accept the input target sampling data and locate the target wafer notch based on the mathematical model. The design of the functional module should ensure efficiency, accuracy and ease of use. For the target wafer notch to be located, obtain its target sampling data. These data should have the same format and accuracy as the data previously used to build the mathematical model. Input the target sampling data into the encapsulated functional module.

[0043] After receiving the input target sampling data, the functional module uses a mathematical model to locate the target wafer notch. The positioning process may involve steps such as data matching, feature extraction and comparison. After the positioning is completed, the functional module outputs the first position information of the target wafer notch. This position information may be based on a certain coordinate system or relative to the center of the wafer.

[0044] In some embodiments, acquiring target sampling data for a target wafer notch includes:

[0045] The target wafer is placed on the calibrator, and the collected data of one rotation of the target wafer is obtained;

[0046] Based on a difference algorithm, data of adjacent sampling points in the sampling data are compared to obtain a difference image or a data sequence, and the difference image or the data sequence is used as the target sampling data.

[0047] Here, the target wafer is carefully placed in the center of the calibrator. The calibrator should ensure that the wafer remains stable during rotation and that the axis of rotation is aligned with the center of the wafer. Start the calibrator and rotate the target wafer in one circle at a constant speed. During the rotation of the wafer, the edge of the wafer is continuously sampled using a high-precision sensor (such as a CCD laser edge detection sensor). The sampling points should be evenly distributed at various positions around the circumference to ensure the comprehensiveness and accuracy of the data. The sensor converts the collected data (such as light intensity, displacement, etc.) into electrical signals, and after digital processing, forms a series of sampled data that can be used for subsequent analysis.

[0048] The collected data is input into the computer system, and the data of adjacent sampling points are compared using the differential algorithm. The differential algorithm can highlight the changes in the data by calculating the difference or ratio between adjacent sampling points. These changes usually correspond to the edge position of the wafer notch. Based on the processing results of the differential algorithm, a differential image or data sequence is generated. The differential image is an intuitive visual representation, in which the edge position of the wafer notch will show obvious features (such as light and dark contrast, edge contour, etc.). The data sequence represents the differential results in numerical form, which can be used for further quantitative analysis and processing. The generated differential image or data sequence is used as the target sampling data. These data contain the precise location and feature information of the wafer notch, which can be used for subsequent wafer notch positioning, correction or other related applications.

[0049] In some embodiments, the mathematical model is constructed based on approximate curve estimation and approximate straight line estimation, and the approximate curve transfer function is y1=a1x1 2+b1x1+c1, a1, b1, c1 are obtained through identification of the mathematical model; the approximate V-type transfer function is y2=k1|x2|+b2, k1, b2 are obtained through identification of the mathematical model; y1 and y2 are the edge distances of the target wafer notch, and x1 and x2 are the wafer rotation angles.

[0050] Here, the mathematical model consists of two main parts: an approximate curve transfer function and an approximate V-shaped transfer function, which are used to describe the distance change of the wafer notch edge at different rotation angles.

[0051] Function form: The approximate curve transfer function is y1=a1x1 2 +b1x1+c1.

[0052] Where y1 represents the distance from the edge of the wafer notch, and x1 represents the angle of wafer rotation (usually in radians or degrees). a1, b1, and c1 are coefficients obtained through mathematical model identification. These coefficients can be determined by fitting or optimizing the sampled data so that the function y1 = a1x1 2 +b1x1+c1 can best describe the actual distance variation of the wafer notch edge.

[0053] Function form: The approximate V-shaped transfer function is y2=k1|x2|+b2. Here, y2 also represents the distance from the edge of the wafer notch, and x2 represents the angle of wafer rotation. The absolute value symbol |x2| is used here to reflect the symmetry of the V-shaped curve. k1 and b2 are coefficients obtained through mathematical model identification. Similar to the approximate curve transfer function, these coefficients are also determined by fitting or optimizing the sampled data.

[0054] In practical applications, it is necessary to select which transfer function or combination of the two to use based on the actual shape and characteristics of the wafer notch. For example, if the wafer notch edge is closer to a quadratic curve shape, it may be more inclined to use an approximate curve transfer function; if the notch edge is closer to a V-shaped or straight line shape, it may be more inclined to use an approximate V-shaped transfer function.

[0055] In summary, this mathematical model combines approximate curve inference and approximate straight line inference (a simplified form of the V-curve), providing an effective method for describing the relationship between the edge distance of the target wafer notch and the wafer rotation angle. Through reasonable parameter identification and optimization process, accurate model parameters can be obtained, thereby achieving precise control and adjustment of the wafer notch.

[0056] In some embodiments, see Figure 2 , Figure 2It is a flow chart of steps S201-S202 provided in an embodiment of the present application. The functional module locates the target wafer notch through steps S201-S202, which will be described in conjunction with each step.

[0057] In step S201 , a mathematical model of a required type is determined based on the target sampling data.

[0058] In step S202, if the mathematical model is an approximate curve transfer function, the target wafer notch is located based on the extreme value of the approximate curve; if the mathematical model is an approximate V-shaped transfer function, the target wafer notch is located based on the intersection value of the approximate V-shaped curve.

[0059] Here, if the selected mathematical model is an approximate curve transfer function (such as y1 = a1x1 2 +b1x1+c1), the function module calculates the extreme points of the curve. The extreme points usually correspond to the farthest or closest points on the edge of the wafer notch, so they can be used to accurately locate the location of the wafer notch. By solving the derivative of the function and finding its zero point, the location of the extreme point can be determined.

[0060] If the selected mathematical model is an approximate V-shaped transfer function (such as y2=k1|x2|+b2), the functional module will look for the intersection value of the curve. In a V-shaped curve, the intersection value usually refers to the intersection of two symmetrical straight line parts on the y-axis (that is, the bottom of the V). Since the V-shaped curve describes the two side edges of the wafer notch, the intersection value can be used to determine the center position of the wafer notch. It should be noted that for an approximate V-shaped curve, it may be necessary to use fitting or interpolation methods to more accurately determine the intersection value.

[0061] The deepest dimension of the notch can be calculated based on the maximum value or intersection point, which is defined as h.

[0062] In step S103, the first position information is subjected to precision correction based on the circle center offset value to obtain second position information, and the target wafer notch is corrected based on the second position information.

[0063] Here, since the wafer may have a center offset during the manufacturing process, the first position information needs to be accurately corrected. The center offset value can be obtained through a measurement or calibration process. After the correction process, the second position information of the target wafer notch is obtained. This position information is more accurate and can be used in the subsequent correction process. Based on the second position information, the target wafer notch is corrected. The correction process involves adjusting the position, direction or other parameters of the wafer to ensure that the wafer notch meets the predetermined standards and requirements.

[0064] In some embodiments, see Figure 3 , Figure 3 It is a flowchart of steps S301-S302 provided in an embodiment of the present application. The precision correction processing of the first position information based on the center offset value can be achieved through steps S301-S302, which will be explained in combination with each step.

[0065] In step S301 , a correction angle is determined based on the center offset value, the radius of the target wafer, and the deepest size of the target wafer notch.

[0066] In step S302, the target wafer notch is corrected based on the correction angle.

[0067] For examples, see Figure 4 , Figure 4 is a correction principle diagram provided in the embodiment of the present application, such as Figure 4 As shown, the correction angle is calculated as follows:

[0068]

[0069] Where, l is the radius of the target wafer;

[0070] h is the deepest dimension of the target wafer notch;

[0071] p is the distance from the center of the circle to the horizontal axis;

[0072] q is the distance from the center of the circle to the longitudinal axis;

[0073] θ is the correction angle.

[0074] In summary, the embodiments of the present application have the following beneficial effects:

[0075] (1) High-precision positioning capability: By constructing a mathematical modeling library containing a variety of mathematical models (such as approximate curve transfer function, approximate V-shaped transfer function, etc.), the embodiment of the present application can accurately compare the characteristic values ​​of different types of sampled data, thereby restoring the true wafer notch information. This flexible mathematical modeling method ensures that high-precision notch positioning can be achieved even when the sampled data is small or the beat is high. With the help of high-precision mathematical models and data processing technology, the embodiment of the present application can calculate the precise positioning angle of the wafer notch. This accuracy is crucial for quality control, wafer alignment, and precise execution of subsequent processing steps during wafer manufacturing.

[0076] (2) Adaptability and flexibility: The embodiments of the present application are not only applicable to the high-precision requirements in current wafer manufacturing, but also can meet the needs of future high-tech development. With the continuous advancement of semiconductor technology, the requirements for wafer notch positioning accuracy are also constantly increasing, and the embodiments of the present application can maintain its adaptability and competitiveness through the continuous updating and optimization of the mathematical model library. Different wafer types, sizes and notch shapes may require different mathematical models and positioning strategies. The embodiments of the present application can cope with the notch positioning requirements of various wafer types by providing a rich mathematical model library and a flexible parameter adjustment mechanism.

[0077] (3) Improving production efficiency and reducing costs: In a production environment with a high tact rate, fast and accurate wafer notch positioning can significantly reduce the production cycle and improve production efficiency. The embodiments of the present application achieve this goal through high-precision mathematical models and efficient data processing algorithms. By reducing the costs of wafer scrapping, reprocessing, etc. caused by inaccurate positioning, the embodiments of the present application help to reduce overall production costs. At the same time, since the embodiments of the present application have a low dependence on sampled data, high accuracy can be maintained even when the sampled data is reduced, thereby further reducing the cost of data acquisition and processing.

[0078] Based on the same inventive concept, the embodiment of the present application also provides a wafer notch positioning device corresponding to the wafer notch positioning method in the first embodiment. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the above-mentioned wafer notch positioning method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0079] like Figure 5 As shown, Figure 5 : is a schematic diagram of the structure of a wafer notch positioning device 500 provided in an embodiment of the present application. The wafer notch positioning device 500 includes:

[0080] A construction module 501 is used to sample data of wafer notches that meet the SEMI standard, construct a mathematical model based on the sampled data, and encapsulate the mathematical model library into a functional module;

[0081] The sampling module 502 is used to obtain target sampling data for the target wafer notch, and input the target sampling data into the functional module, so that the functional module locates the target wafer notch based on the target sampling data to obtain first position information;

[0082] The correction module 503 is used to perform precision correction processing on the first position information based on the center offset value to obtain second position information, and correct the target wafer gap based on the second position information.

[0083] Those skilled in the art should understand that Figure 5The functions implemented by each unit in the wafer notch positioning device 500 shown can be understood by referring to the relevant description of the aforementioned wafer notch positioning method. Figure 5 The functions of the various units in the wafer notch positioning device 500 shown can be implemented by a program running on a processor, or can be implemented by a specific logic circuit.

[0084] In a possible implementation, the mathematical model is constructed based on approximate curve estimation and approximate straight line estimation, and the approximate curve transfer function is y1=a1x1 2 +b1x1+c1, a1, b1, c1 are obtained through identification of the mathematical model; the approximate V-type transfer function is y2=k1|x2|+b2, k1, b2 are obtained through identification of the mathematical model; y1 and y2 are the edge distances of the target wafer notch, and x1 and x2 are the wafer rotation angles.

[0085] In a possible implementation manner, the functional module locates the target wafer notch in the following manner:

[0086] Determining a desired type of mathematical model based on the target sampling data;

[0087] If the mathematical model is an approximate curve transfer function, the target wafer notch is located based on the extreme value of the approximate curve; if the mathematical model is an approximate V-shaped transfer function, the target wafer notch is located based on the intersection value of the approximate V-shaped curve.

[0088] In a possible implementation, the correction module 503 performs precision correction processing on the first position information based on the circle center offset value, including:

[0089] Determining a correction angle based on the center offset value, the radius of the target wafer, and the deepest dimension of the target wafer notch;

[0090] The target wafer notch is corrected based on the correction angle.

[0091] In a possible implementation, the correction angle is calculated in the following manner:

[0092]

[0093] Where, l is the radius of the target wafer;

[0094] h is the deepest dimension of the target wafer notch;

[0095] p is the distance from the center of the circle to the horizontal axis;

[0096] q is the distance from the center of the circle to the longitudinal axis;

[0097] θ is the correction angle.

[0098] In a possible implementation, the construction module 501 samples data of wafer notches that comply with the SEMI standard, and constructs a mathematical model based on the sampled data, including:

[0099] Place wafers of different specifications at the center of the calibrator respectively;

[0100] Data sampling is performed through a CCD laser edge detection sensor;

[0101] The notch edge information is modeled based on the sampled data.

[0102] In a possible implementation, the sampling module 502 acquires target sampling data for a target wafer notch, including:

[0103] The target wafer is placed on the calibrator, and the collected data of one rotation of the target wafer is obtained;

[0104] Based on a difference algorithm, data of adjacent sampling points in the sampling data are compared to obtain a difference image or a data sequence, and the difference image or the data sequence is used as the target sampling data.

[0105] The above wafer notch positioning device has the following beneficial effects:

[0106] (1) High-precision positioning capability: By constructing a mathematical modeling library containing a variety of mathematical models (such as approximate curve transfer function, approximate V-shaped transfer function, etc.), the embodiment of the present application can accurately compare the characteristic values ​​of different types of sampled data, thereby restoring the true wafer notch information. This flexible mathematical modeling method ensures that high-precision notch positioning can be achieved even when the sampled data is small or the beat is high. With the help of high-precision mathematical models and data processing technology, the embodiment of the present application can calculate the precise positioning angle of the wafer notch. This accuracy is crucial for quality control, wafer alignment, and precise execution of subsequent processing steps during wafer manufacturing.

[0107] (2) Adaptability and flexibility: The embodiments of the present application are not only applicable to the high-precision requirements in current wafer manufacturing, but also can meet the needs of future high-tech development. With the continuous advancement of semiconductor technology, the requirements for wafer notch positioning accuracy are also constantly increasing, and the embodiments of the present application can maintain its adaptability and competitiveness through the continuous updating and optimization of the mathematical model library. Different wafer types, sizes and notch shapes may require different mathematical models and positioning strategies. The embodiments of the present application can cope with the notch positioning requirements of various wafer types by providing a rich mathematical model library and a flexible parameter adjustment mechanism.

[0108] (3) Improving production efficiency and reducing costs: In a production environment with a high tact rate, fast and accurate wafer notch positioning can significantly reduce the production cycle and improve production efficiency. The embodiments of the present application achieve this goal through high-precision mathematical models and efficient data processing algorithms. By reducing the costs of wafer scrapping, reprocessing, etc. caused by inaccurate positioning, the embodiments of the present application help to reduce overall production costs. At the same time, since the embodiments of the present application have a low dependence on sampled data, high accuracy can be maintained even when the sampled data is reduced, thereby further reducing the cost of data acquisition and processing.

[0109] like Figure 6 As shown, Figure 6 The present invention provides a schematic diagram of the structure of an electronic device 600, wherein the electronic device 600 includes:

[0110] A processor 601, a storage medium 602 and a bus 603, wherein the storage medium 602 stores machine-readable instructions executable by the processor 601. When the electronic device 600 is running, the processor 601 communicates with the storage medium 602 via the bus 603, and the processor 601 executes the machine-readable instructions to perform the steps of the wafer notch positioning method described in the embodiment of the present application.

[0111] In actual application, the components in the electronic device 600 are coupled together via the bus 603. It is understood that the bus 603 is used to realize the connection and communication between these components. In addition to the data bus, the bus 603 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 6 Various buses are labeled as bus 603.

[0112] The electronic device has the following beneficial effects:

[0113] (1) High-precision positioning capability: By constructing a mathematical modeling library containing a variety of mathematical models (such as approximate curve transfer function, approximate V-shaped transfer function, etc.), the embodiment of the present application can accurately compare the characteristic values ​​of different types of sampled data, thereby restoring the true wafer notch information. This flexible mathematical modeling method ensures that high-precision notch positioning can be achieved even when the sampled data is small or the beat is high. With the help of high-precision mathematical models and data processing technology, the embodiment of the present application can calculate the precise positioning angle of the wafer notch. This accuracy is crucial for quality control, wafer alignment, and precise execution of subsequent processing steps during wafer manufacturing.

[0114] (2) Adaptability and flexibility: The embodiments of the present application are not only applicable to the high-precision requirements in current wafer manufacturing, but also can meet the needs of future high-tech development. With the continuous advancement of semiconductor technology, the requirements for wafer notch positioning accuracy are also constantly increasing, and the embodiments of the present application can maintain its adaptability and competitiveness through the continuous updating and optimization of the mathematical model library. Different wafer types, sizes and notch shapes may require different mathematical models and positioning strategies. The embodiments of the present application can cope with the notch positioning requirements of various wafer types by providing a rich mathematical model library and a flexible parameter adjustment mechanism.

[0115] (3) Improving production efficiency and reducing costs: In a production environment with a high tact rate, fast and accurate wafer notch positioning can significantly reduce the production cycle and improve production efficiency. The embodiments of the present application achieve this goal through high-precision mathematical models and efficient data processing algorithms. By reducing the costs of wafer scrapping, reprocessing, etc. caused by inaccurate positioning, the embodiments of the present application help to reduce overall production costs. At the same time, since the embodiments of the present application have a low dependence on sampled data, high accuracy can be maintained even when the sampled data is reduced, thereby further reducing the cost of data acquisition and processing.

[0116] The embodiment of the present application further provides a computer-readable storage medium, which stores executable instructions. When the executable instructions are executed by at least one processor 601, the wafer notch positioning method described in the embodiment of the present application is implemented.

[0117] In some embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CDROM); it can also be various devices including one or any combination of the above memories.

[0118] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0119] As an example, executable instructions may, but do not necessarily, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (for example, files storing one or more modules, subroutines, or code portions).

[0120] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0121] The computer-readable storage medium has the following advantages:

[0122] (1) High-precision positioning capability: By constructing a mathematical modeling library containing a variety of mathematical models (such as approximate curve transfer function, approximate V-shaped transfer function, etc.), the embodiment of the present application can accurately compare the characteristic values ​​of different types of sampled data, thereby restoring the true wafer notch information. This flexible mathematical modeling method ensures that high-precision notch positioning can be achieved even when the sampled data is small or the beat is high. With the help of high-precision mathematical models and data processing technology, the embodiment of the present application can calculate the precise positioning angle of the wafer notch. This accuracy is crucial for quality control, wafer alignment, and precise execution of subsequent processing steps during wafer manufacturing.

[0123] (2) Adaptability and flexibility: The embodiments of the present application are not only applicable to the high-precision requirements in current wafer manufacturing, but also can meet the needs of future high-tech development. With the continuous advancement of semiconductor technology, the requirements for wafer notch positioning accuracy are also constantly increasing, and the embodiments of the present application can maintain its adaptability and competitiveness through the continuous updating and optimization of the mathematical model library. Different wafer types, sizes and notch shapes may require different mathematical models and positioning strategies. The embodiments of the present application can cope with the notch positioning requirements of various wafer types by providing a rich mathematical model library and a flexible parameter adjustment mechanism.

[0124] (3) Improving production efficiency and reducing costs: In a production environment with a high tact rate, fast and accurate wafer notch positioning can significantly reduce the production cycle and improve production efficiency. The embodiments of the present application achieve this goal through high-precision mathematical models and efficient data processing algorithms. By reducing the costs of wafer scrapping, reprocessing, etc. caused by inaccurate positioning, the embodiments of the present application help to reduce overall production costs. At the same time, since the embodiments of the present application have a low dependence on sampled data, high accuracy can be maintained even when the sampled data is reduced, thereby further reducing the cost of data acquisition and processing.

[0125] In the several embodiments provided in the present application, it should be understood that the disclosed methods and electronic devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0126] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0127] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0128] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a platform server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0129] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wafer notch positioning method, characterized in that: The method comprises: Sampling data of wafer notches that meet SEMI standards, building a mathematical model based on the sampled data, and encapsulating the mathematical model library into a functional module; Acquire target sampling data for a target wafer notch, and input the target sampling data into the functional module, so that the functional module locates the target wafer notch based on the target sampling data to obtain first position information; The first position information is subjected to precision correction processing based on the circle center offset value to obtain second position information, and the target wafer notch is corrected based on the second position information.

2. The method according to claim 1, characterized in that The mathematical model is constructed based on approximate curve estimation and approximate straight line estimation, and the approximate curve transfer function is y1=a1x1 2 +b1x1+c1, a1, b1, c1 are obtained through identification of the mathematical model; the approximate V-type transfer function is y2=k1|x2|+b2, k1, b2 are obtained through identification of the mathematical model; y1 and y2 are the edge distances of the target wafer notch, and x1 and x2 are the wafer rotation angles.

3. The method according to claim 2, characterized in that The functional module locates the target wafer notch in the following manner: Determining a desired type of mathematical model based on the target sampling data; If the mathematical model is an approximate curve transfer function, the target wafer notch is located based on the extreme value of the approximate curve; if the mathematical model is an approximate V-shaped transfer function, the target wafer notch is located based on the intersection value of the approximate V-shaped curve.

4. The method according to claim 1, characterized in that: The performing precision correction processing on the first position information based on the circle center offset value includes: Determining a correction angle based on the center offset value, the radius of the target wafer, and the deepest dimension of the target wafer notch; The target wafer notch is corrected based on the correction angle.

5. The method according to claim 4, characterized in that The correction angle is calculated as follows: Where, l is the radius of the target wafer; h is the deepest dimension of the target wafer notch; p is the distance from the center of the circle to the horizontal axis; q is the distance from the center of the circle to the longitudinal axis; θ is the correction angle.

6. The method according to claim 1, characterized in that The method of sampling the wafer notches that meet the SEMI standard and building a mathematical model based on the sampled data includes: Place wafers of different specifications at the center of the calibrator respectively; Data sampling is performed through a CCD laser edge detection sensor; The notch edge information is modeled based on the sampled data.

7. The method according to claim 1, characterized in that The step of acquiring target sampling data for a target wafer notch includes: The target wafer is placed on the calibrator, and the collected data of one rotation of the target wafer is obtained; Based on a difference algorithm, data of adjacent sampling points in the sampling data are compared to obtain a difference image or a data sequence, and the difference image or the data sequence is used as the target sampling data.

8. A wafer notch positioning device, characterized in that: The device comprises: A construction module is used to sample data of wafer notches that meet SEMI standards, construct a mathematical model based on the sampled data, and encapsulate the mathematical model library into a functional module; A sampling module, used for acquiring target sampling data for a target wafer notch, and inputting the target sampling data into the functional module, so that the functional module locates the target wafer notch based on the target sampling data to obtain first position information; The correction module is used to perform precision correction processing on the first position information based on the center offset value to obtain second position information, and correct the target wafer gap based on the second position information.

9. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to execute the wafer notch positioning method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the wafer notch positioning method according to any one of claims 1 to 7 is executed.

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