Plasma processing apparatus and plasma processing method

Abstract

The plasma processing apparatus includes: a sample stage including a placement surface on which a semiconductor wafer is placed; a dielectric ring provided with an annular thin film electrode disposed around the sample stage; and a dielectric susceptor ring covering the thin film electrode. The thin film electrode includes: a first portion located at a position lower than the back surface of the semiconductor wafer; a second portion located at a position higher than the main surface of the semiconductor wafer; and a third portion connecting the first portion and the second portion, the first portion of the thin film electrode having an overlapping region overlapping the semiconductor wafer in plan view.

Description

[0001] This application is a divisional application of application No. 202180004956.7 entitled “Plasma Processing Device and Plasma Processing Method” filed with the State Intellectual Property Office of China on March 24, 2021. Technical Field

[0002] The present invention relates to a plasma processing device and a plasma processing method, and in particular to a plasma processing device and a plasma processing method suitable for processing a workpiece such as a semiconductor wafer. Background Art

[0003] In semiconductor manufacturing processes, dry etching using plasma is generally performed. Various types of plasma processing apparatuses are used for dry etching.

[0004] In general, a plasma processing apparatus is composed of a vacuum processing chamber, a gas supply device connected thereto, a vacuum exhaust system for maintaining the pressure in the vacuum processing chamber at a desired value, an electrode for mounting a semiconductor wafer as a workpiece, a plasma generating unit for generating plasma in the vacuum processing chamber, etc. The plasma generating unit converts the processing gas supplied from a shower plate or the like into a plasma state in the vacuum processing chamber, thereby performing etching processing on the semiconductor wafer held by the wafer mounting electrode.

[0005] In recent years, as the integration of semiconductor devices has increased, circuit structures have become more miniaturized, and therefore, micromachining, i.e., improved machining accuracy, has been required. Furthermore, in order to increase the yield of good semiconductor devices per semiconductor wafer, a plasma processing device that can manufacture good semiconductor devices up to the peripheral portion of the semiconductor wafer is sought.

[0006] In order to suppress the degradation of the performance at the peripheral portion of the semiconductor wafer, it is important to reduce the concentration of the electric field at the peripheral region of the semiconductor wafer placed on the sample stage. For example, in the case of etching processing, it is necessary to suppress the rapid increase of the processing speed (etching rate) at the peripheral portion of the semiconductor wafer. Therefore, it is necessary to make the thickness of the sheath formed on the upper portion of the semiconductor wafer uniform from the center portion of the semiconductor wafer to the peripheral region during the processing of the semiconductor wafer.

[0007] The following technology is disclosed in JP Patent Gazette No. 2020-43100 (Patent Document 1): a conductive thin film electrode is provided on a portion of an insulating ring arranged around the outer periphery of a sample stage on which a semiconductor wafer is placed, a first high-frequency power is applied to the sample stage, and a second high-frequency power is applied to the thin film electrode, thereby improving the uniformity of plasma processing up to the peripheral portion of the semiconductor wafer.

[0008] JP Patent Publication No. 2010-283028 (Patent Document 2) discloses the following technology: a dielectric ring is arranged to surround the outer periphery of a sample stage on which a semiconductor wafer is placed, and a conductive ring is provided thereon, wherein the conductive ring is integrally formed by an outer ring having an upper surface higher than the wafer and an inner ring having an upper surface lower than the wafer, and a DC voltage is applied to the conductive ring to control the ion incident angle, thereby improving the balance between the reduction of deposits and the processing results.

[0009] Prior art literature

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Publication No. 2020-43100

[0012] Patent Document 2: Japanese Patent Application Publication No. 2010-283028 Summary of the invention

[0013] Problems to be solved by the invention

[0014] In Patent Document 1, in order to suppress electrical interference with high-frequency power of other systems applied to the sample stage, an insulating ring formed with a thin-film electrode to which high-frequency power is applied is provided with a structure other than a sample stage mounting surface covered by a base ring made of a dielectric material. Therefore, the inner peripheral end of the thin-film electrode cannot be brought close to the end of the wafer, and further research is required for appropriate electric field control around the end of the wafer.

[0015] In addition, since there is no guard ring covering the periphery of the conductive ring in Patent Document 2, the temperature of the conductive ring rises due to the contact of the conductive ring with plasma. It is necessary to study the fact that the reliability of the device is impaired due to this influence, and the fact that the temperature of the processed wafer is uneven due to the influence of heat, resulting in a deviation in the processed shape.

[0016] That is, a plasma processing method is provided for improving the reliability of a plasma processing apparatus or improving the yield of semiconductor wafers to be processed.

[0017] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0018] Means for solving problems

[0019] A plasma processing device in one embodiment comprises: a sample stage, which is arranged in a processing chamber for forming plasma inside a vacuum processing device, and has a mounting surface on which a wafer to be processed is mounted, the sample stage comprising: a cylindrical convex portion arranged in the central part of the upper portion and having the mounting surface on the upper surface, a concave portion arranged in an annular shape surrounding the convex portion and constituting the outer peripheral portion of the upper portion, and a high-frequency electrode to which high-frequency power is supplied during processing of the wafer; and a base ring, which is arranged in the concave portion so as to surround the convex portion, and has an annular thin-film electrode and a dielectric portion, the thin-film electrode being supplied with high-frequency power of a different magnitude from the high-frequency power supplied to the high-frequency electrode during processing of the wafer, and the dielectric portion covering the thin-film electrode above the thin-film electrode. The thin film electrode is configured to include: a first portion constituting an inner peripheral end portion, being located at a position lower than the mounting surface and having a flat portion; a flat second portion being configured on the outer peripheral side of the first portion and the chip and being located at a position higher than the upper surface of the chip; and a third portion connecting the outer peripheral edge portion of the first portion with the inner peripheral edge portion of the second portion to form a step-shaped portion, and the base ring has: an inner peripheral end portion being located below the outer peripheral end portion of the chip when viewed from above when the chip is mounted on the mounting surface while covering the first portion of the thin film electrode, a flat outer peripheral portion covering the upper surface of the second portion, and a portion connecting the inner peripheral end portion and the outer peripheral portion as a whole and having an upper surface inclined higher toward the periphery and covering the second portion.

[0020] In addition, a plasma processing method in one embodiment places a wafer to be processed on a loading surface at an upper portion of a sample stage in a processing chamber arranged inside a vacuum container, and processes the wafer using plasma formed in the processing chamber, wherein the sample stage comprises: a cylindrical protrusion arranged at a central portion of an upper portion and having the loading surface on an upper surface, a recessed portion arranged to surround the protrusion in an annular shape and constituting an outer peripheral portion of the upper portion, and a high-frequency electrode to which high-frequency power is supplied during processing of the wafer, and a base ring, which is arranged to surround the protrusion in the recessed portion and has an annular thin-film electrode and a dielectric portion arranged to cover the thin-film electrode above the thin-film electrode, wherein the thin-film electrode comprises: a flat portion constituting an inner peripheral end portion and located at a position lower than the loading surface The base ring comprises: a first part; a flat second part arranged on the outer peripheral side of the first part and the wafer and located at a position higher than the upper surface of the wafer; and a third part which connects the outer peripheral edge of the first part and the inner peripheral edge of the second part to form a stepped part, the base ring comprising: an inner peripheral end portion which is located below the outer peripheral end portion of the wafer when viewed from above when the wafer is placed on the loading surface and the first part covers the thin film electrode, a flat outer peripheral portion which covers the upper surface of the second part, and a portion which connects the inner peripheral end portion and the outer peripheral portion as a whole and has an upper surface which is inclined higher toward the periphery and covers the second part, and supplies a high-frequency power of a different magnitude from that supplied to the high-frequency electrode during the processing of the wafer.

[0021] Effects of the Invention

[0022] According to one embodiment, the reliability of a plasma processing device can be improved. In addition, the yield rate of objects to be processed in plasma processing can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a cross-sectional view schematically showing the structure of a plasma processing apparatus according to one embodiment.

[0024] Figure 2 This is a cross-sectional view showing the periphery of a wafer placement electrode of a plasma processing apparatus according to an embodiment.

[0025] Figure 3 This is a plan view showing a wafer mounting electrode of a plasma processing apparatus according to an embodiment.

[0026] Figure 4 yes Figure 3 Cross-sectional view of line XX.

[0027] Figure 5 This is a cross-sectional view showing the periphery of a wafer mounting electrode of a plasma processing apparatus according to Modification 1.

[0028] Figure 6 This is a cross-sectional view schematically showing the structure of a plasma processing apparatus according to Modification 2. DETAILED DESCRIPTION

[0029] The following detailed description of the embodiment is based on the accompanying drawings. In addition, in all the figures used to illustrate the embodiment, the same reference numerals are used to mark the components with the same functions, and their repeated descriptions are omitted. In addition, in the following embodiments, the description of the same or identical parts is not repeated in principle except when it is particularly necessary.

[0030] (Implementation Method)

[0031] <Plasma processing equipment>

[0032] The following uses Figure 1 to Figure 4 The plasma processing apparatus according to this embodiment will be described. Figure 1 is a schematic cross-sectional view schematically showing the structure of a plasma processing apparatus according to this embodiment. Figure 2 1 is a cross-sectional view showing the periphery of a wafer placement electrode of a plasma processing apparatus according to the present embodiment. Figure 3 FIG. 1 is a plan view showing a wafer mounting electrode of the plasma processing apparatus according to the present embodiment. Figure 4 yes Figure 3 Cross-sectional view of line XX.

[0033] Figure 1 The plasma etching device 100 is an example of a plasma processing device. The plasma etching device 100 uses the electric field of microwaves as the electric field for forming plasma, induces ECR (Electron Cyclotron Resonance) of the electric field and magnetic field of microwaves to form plasma, and uses the plasma to etch substrate-shaped samples such as semiconductor wafers.

[0034] The plasma etching device 100 includes a vacuum container 101, which has a processing chamber 104 in which plasma is formed. The processing chamber 104 has a cylindrical shape on the upper part thereof, and a disc-shaped dielectric window 103 (for example, made of quartz) is installed as a cover member, constituting a part of the vacuum container 101. A sealing member such as an O-ring is arranged between the cylindrical vacuum container 101 and the dielectric window 103 to ensure the airtightness of the inside of the vacuum container 101 or the processing chamber 104.

[0035] In addition, a vacuum exhaust port 110 connected to the processing chamber 104 is arranged at the lower part of the vacuum container 101, and is connected to a vacuum exhaust device (not shown) arranged below the vacuum container 101. Furthermore, a shower plate 102 constituting a circular top plate surface of the processing chamber 104 is provided below the dielectric window 103. The shower plate 102 has a circular plate shape with a plurality of gas introduction holes 102a arranged through the center, and the gas for etching processing is introduced into the processing chamber 104 through the gas introduction holes 102a. The shower plate 102 is made of a dielectric material such as quartz.

[0036] An electric field / magnetic field forming unit 160 for forming an electric field and a magnetic field for generating plasma 116 is arranged above the vacuum container 101. The electric field / magnetic field forming unit 160 includes a waveguide 105 and an electric field generating power supply 106. A high-frequency electric field oscillated from the electric field generating power supply 106 is transmitted inside the waveguide 105 and introduced into the processing chamber 104. For example, a microwave of 2.45 GHz is used as the frequency of the electric field.

[0037] Magnetic field generating coils 107 are disposed around the lower end of the waveguide 105 and around the vacuum container 101. The magnetic field generating coils 107 are composed of an electromagnet and a yoke that are supplied with a direct current to form a magnetic field.

[0038] When the processing gas is introduced into the processing chamber 104 from the gas inlet hole 102a of the shower plate 102, the electric field of the microwave oscillated by the electric field generating power supply 106 propagates inside the waveguide 105, passes through the dielectric window 103 and the shower plate 102, and is supplied from the top to the processing chamber 104 downward. Furthermore, the magnetic field caused by the direct current supplied to the magnetic field generating coil 107 is supplied to the processing chamber 104, so that it interacts with the electric field of the microwave, and induces ECR (Electron Cyclotron Resonance). Through ECR, the atoms or molecules of the processing gas are excited, dissociated or ionized, and a high-density plasma 116 is generated in the processing chamber 104.

[0039] A wafer placement electrode 120 is disposed below the space where the plasma 116 is formed. The wafer placement electrode 120 has a cylindrical protrusion (convex) portion at the center of its upper portion, the upper surface of which is higher than the outer peripheral side, and a placement surface 120a on which a semiconductor wafer (hereinafter also simply referred to as a wafer) 109 as a sample (processing object) is placed is disposed on the upper surface of the convex portion. The placement surface 120a is disposed to face the shower plate 102 or the dielectric window 103.

[0040] like Figure 2As shown, the wafer mounting electrode 120 includes an electrode substrate 108 , a dielectric film 140 provided on the electrode substrate 108 , an insulating plate 150 and a ground plate 151 provided under the electrode substrate 108 , a dielectric ring 139 , and a susceptor ring 113 .

[0041] The electrode substrate 108 includes a convex portion (protrusion) 108p and a concave portion (depressed portion) 108d. The convex portion 108p, which is circular when viewed from above, is located in the center of the electrode substrate 108, and the annular concave portion 108d is located around it. The convex portion 108p includes an upper surface 108a, which is circular when viewed from above, and the upper surface 108a is covered with a dielectric film 140. In addition, the dielectric film 140 includes a mounting surface 120a, and the semiconductor wafer 109 is mounted on the mounting surface 120a. The mounting surface 120a has a circular shape when viewed from above, and its radius is equal to the radius of the upper surface 108a, and the centers of the two circles overlap each other.

[0042] A plurality of conductive films, namely, conductive films 111, are arranged inside the dielectric film 140. Figure 1 As shown in FIG. 1 , the conductor film 111 is connected to a DC power source 126 via a high frequency filter 125. When DC power is supplied to the conductor film 111, the semiconductor wafer 109 is adsorbed on the mounting surface 120a via the dielectric film 140 on the conductor film 111. The conductor film 111 is an electrode for electrostatic adsorption. For convenience, the convex portion (protrusion) 108p of the electrode substrate 108 and the dielectric film 140 including the conductor film 111 are referred to as a sample stage ST.

[0043] The electrode substrate 108 is connected to the high frequency power source 124 via the junction box 127 and the matching device 129. The high frequency power source 124 and the matching device 129 are arranged closer to the distance between the high frequency filter 125 and the conductor film 111. The high frequency power source 124 is connected to the ground 112.

[0044] During the processing of the semiconductor wafer 109, a high frequency power of a given frequency is supplied to the electrode substrate 108 (i.e., the sample stage ST) from the high frequency power supply 124. A bias potential having a distribution corresponding to the difference between the potential of the plasma 116 and the potential of the electrode substrate 108 is formed above the semiconductor wafer 109 adsorbed and held on the mounting surface 120a via the dielectric film 140.

[0045] In order to cool the wafer mounting electrode 120, the electrode substrate 108 is provided with a refrigerant flow path 152 that is arranged in a spiral or concentric manner in multiple layers around the central axis of the electrode substrate 108 in the vertical direction. The inlet and outlet of the wafer mounting electrode 120 are connected to a temperature regulator that has a refrigeration cycle (not shown) and regulates the temperature of the refrigerant to a given range through heat transfer through a pipeline, and the refrigerant that flows through the refrigerant flow path 152 and changes in temperature through heat exchange flows out from the outlet, passes through the pipeline and passes through the flow path inside the temperature regulator to be set to a given temperature range, and is then supplied to the refrigerant flow path 152 in the electrode substrate 108 for circulation.

[0046] An annular dielectric ring 139 surrounding the convex portion 108p is mounted on the concave portion 108d of the electrode substrate 108, and a base ring 113 is mounted on the dielectric ring 139. The dielectric ring 139 and the base ring 113 are made of a dielectric material such as ceramics such as quartz or alumina. The side surface of the electrode substrate 108 and the bottom surface of the concave portion 108b are at least covered by the dielectric ring 139 or the base ring 113, which can prevent the electrode substrate 108 from being damaged by plasma. In addition, the surface of the dielectric ring 139 in contact with the base ring 113 is, for example, a rough surface with a surface roughness Ra of 1.0 or more. In this way, heat transfer from the base ring 113, which is in contact with plasma and becomes high temperature, to the dielectric ring 139 is suppressed.

[0047] The dielectric ring 139 is composed of a dielectric ring 139a and a thin film electrode 139b, and the thin film electrode 139b is formed on the stepped upper surface of the dielectric ring 139a. The thin film electrode 139b is connected to the junction box 127 via the load impedance variable box 130. That is, the electrode substrate 108 of the sample stage ST on which the semiconductor wafer 109 is mounted and the thin film electrode 139b of the dielectric ring 139 are connected to the high frequency power supply 124 as a single power supply, and the high frequency power supply 124 supplies high frequency power to the electrode substrate 108 and the thin film electrode 139b.

[0048] The chip mounting electrode 120 includes: an insulating plate 150 which is arranged in contact with the lower surface of the electrode substrate 108 and is in the shape of a disk; and a grounding plate 151 which is a member made of a conductive disk and arranged in contact with the lower surface of the insulating plate 150 and is set to a ground potential.

[0049] like Figure 1 As shown, the electric field generating power supply 106, the magnetic field generating coil 107, the high frequency power supply 124, the high frequency filter 125, the DC power supply 126, the junction box 127, the matching device 129, the load impedance variable box 130 and the controller 170 are connected to each other via wired or wireless communication.

[0050] use Figure 3 A top view of Figure 4 A cross-sectional view is used to illustrate the mounting surface 120a of the sample stage ST, the semiconductor wafer 109, and the thin film electrode 139b. In addition, as Figure 4 shown, the semiconductor wafer 109 has: a main surface 109a that has been subjected to plasma treatment; a back surface 109b that contacts the mounting surface 120a; and an end portion 109e that is an arc portion of the main surface 109a.

[0051] As Figure 3 shown, the mounting surface 120a has a circular shape with a radius R1 starting from the center OS. The annular thin film electrode 139b has: an inner peripheral end 139bie with a circular shape having a radius R3 starting from the center OS; and an outer peripheral end 139boe with a circular shape having a radius R4 starting from the center OS. In addition, the main surface 109a (in other words, the end portion 109e) of the semiconductor wafer 109 has a circular shape with a radius R2 starting from the center OU. In addition, due to the "mating deviation" when the semiconductor wafer 109 is mounted on the mounting surface 120a, there is a case where the center OU deviates from the center OS, but the consistent case is shown in Figure 3 . Even if there is a "mating deviation", as long as it is within an allowable range, plasma treatment is performed. The radius R2 of the main surface 109a of the semiconductor wafer 109 is larger than the radius R1 of the mounting surface 120a (R2 > R1). In addition, the radius R4 of the outer peripheral end 139boe of the thin film electrode 139b is larger than the radius R3 of the inner peripheral end 139bie (R4 > R3). The characteristic point of the present embodiment is that the radius R3 of the inner peripheral end 139bie of the thin film electrode 139b is smaller than the radius R2 of the end portion 109e of the semiconductor wafer 109 (R3 < R2). That is, in a top view, the thin film electrode 139b and the semiconductor wafer 109 have an "overlap region ( Figure 3 the shaded region in

[0052] As Figure 4As shown in the figure, the upper surface of the dielectric ring 139a includes a first surface 139a1, a third surface 139a3, and a second surface 139a2 arranged in a step shape. The first surface 139a1 and the second surface 139a2 are horizontal surfaces parallel to the main surface 109a or the mounting surface 120a of the semiconductor wafer 109, and the third surface 139a3 is a surface connecting the first surface 139a1 and the second surface 139a2, and is a surface perpendicular to the main surface 109a or the mounting surface 120a of the semiconductor wafer 109. In addition, a thin film electrode 139b is provided on the upper surface of the dielectric ring 139a. In addition, an insulating film may be provided on the upper surface of the dielectric ring 139a, and the thin film electrode 139b may be formed thereon.

[0053] The thin film electrode 139b is composed of a conductive film such as a thermal spray film of tungsten. The annular thin film electrode 139b has a ring width from the inner peripheral end 139bie to the outer peripheral end 139bоe, and has a first part 139b1, a third part 139b3 and a second part 139b2 in the width direction. The first part 139b1, the third part 139b3 and the second part 139b2 are formed corresponding to the first surface 139a1, the third surface 139a3 and the second surface 139a2 of the upper surface of the dielectric ring 139a, respectively. Therefore, the first part 139b1 and the second part 139b2 are horizontal planes parallel to the main surface 109a or the mounting surface 120a of the semiconductor wafer 109, and the third part 139b3 is a vertical plane connecting the first part 139b1 and the second part 139b2. In addition, the first portion 139b1 is located at a position lower than the back surface 109b of the semiconductor wafer 109 in the vertical direction, and the inner peripheral end 139bie is located below the semiconductor wafer 109 and overlaps with the semiconductor wafer 109. The first portion 139b1 is arranged to be separated from the back surface 109b of the semiconductor wafer 109 by a distance A in the vertical direction, and has an "overlapping area" with the semiconductor wafer 109 when viewed from above. The second portion 139b2 is located at a position higher than the main surface 109a of the semiconductor wafer 109 in the entire region. In addition, the third portion 139b3 is separated from the end 109e of the semiconductor wafer 109 by a distance B in the horizontal direction. The present embodiment is characterized in that the distance A is smaller than the distance B. The so-called horizontal direction is a direction orthogonal to the vertical direction, and is a direction parallel to the mounting surface 120a or the main surface 109a of the semiconductor wafer 109.

[0054] In addition, if Figure 2 As shown, the first portion 139b1, the third portion 139b3, and the second portion 139b2 of the thin film electrode 139b have their surfaces (upper surfaces) covered by the susceptor ring 113. The susceptor ring 113 has a surface higher than the main surface 109a of the semiconductor wafer 109 above the second portion 139b2.

[0055] <Plasma treatment method>

[0056] Next, a plasma processing method using the aforementioned plasma etching apparatus 100 will be described.

[0057] First, the aforementioned plasma etching apparatus 100 is prepared.

[0058] Next is the process of carrying in the semiconductor wafer 109. The side wall of the vacuum container 101 is connected to a vacuum transport chamber that is decompressed to the same pressure as the processing chamber 104. The semiconductor wafer 109 is placed on the front end of the arm of the wafer transport robot arranged in the vacuum transport chamber and carried into the processing chamber 104. Next, the semiconductor wafer 109 is placed on the mounting surface 120a and is held on the sample stage ST by electrostatic adsorption.

[0059] Next is the etching gas introduction process. After the transport robot exits into the vacuum transport chamber, the interior of the processing chamber 104 is sealed. In this state, the gas for etching treatment is supplied to the processing chamber 104. The introduced gas is introduced into the processing chamber 104 through the gas introduction hole 102a of the shower plate 102. The gas and particles inside the processing chamber 104 are exhausted through the vacuum exhaust port 110 by the action of the vacuum exhaust device connected to the vacuum exhaust port 110. Corresponding to the balance between the supply amount of gas from the gas introduction hole 102a of the shower plate 102 and the exhaust amount from the vacuum exhaust port 110, the processing chamber 104 is adjusted to a given pressure suitable for the processing of the semiconductor wafer 109.

[0060] Next is the plasma etching (plasma treatment) process. Although the details are omitted, after adjusting the temperature of the semiconductor wafer 109 as needed, the electric field and magnetic field of microwaves are supplied to the processing chamber 104, and the plasma 116 is generated using gas. When the plasma 116 is formed, high-frequency (RF) power is supplied to the electrode substrate 108 from the high-frequency power supply 124, and a bias potential is formed above the main surface 109a of the semiconductor wafer 109, and the ions and other charged particles in the plasma 116 are induced to the main surface 109a of the semiconductor wafer 109 in accordance with the potential difference with the potential of the plasma 116. Furthermore, the charged particles collide with the surface of the film layer of the processing object pre-configured on the main surface 109a of the semiconductor wafer 109, thereby performing etching processing. In addition, as Figure 2 to Figure 4 As described in the figure, high frequency (RF) power is supplied from the high frequency power supply 124 to the thin film electrode 139b provided in the dielectric ring 139 via the matching circuit 129, the junction box 127 and the load impedance variable box 130. In addition, during the etching process, the process gas introduced into the process chamber 104 and the particles of the reaction product generated during the process are exhausted from the vacuum exhaust port 110.

[0061] Next is the step of carrying out the semiconductor wafer 109 . The semiconductor wafer 109 after the etching process is supported by the front end of the arm of the aforementioned transport robot and carried out of the processing chamber 104 .

[0062] <Features of this embodiment>

[0063] In the plasma processing apparatus of this embodiment, high-frequency power is supplied from a single high-frequency power supply 124 to the electrode substrate 108 of the sample stage ST and the thin-film electrode 139b provided on the dielectric ring 139 during the processing of the semiconductor wafer 109. The high-frequency power output from the high-frequency power supply 124 is supplied to the thin-film electrode 139b provided on the inner side of the susceptor ring 113 via the load impedance variable box 130 provided on the power supply path that electrically connects the junction box 127 and the thin-film electrode 139b. At this time, by adjusting the impedance on the power supply path to a value within an appropriate range in the load impedance variable box 130, the impedance value to the high-frequency power from the high-frequency power supply 124 through the junction box 127 and through the electrode substrate 108 to the peripheral edge of the semiconductor wafer 109 becomes relatively low with respect to the relatively high impedance portion of the upper portion of the susceptor ring 113. Thus, high frequency power can be effectively supplied to the peripheral portion and the outer peripheral region of the semiconductor wafer 109, and the concentration of the electric field in the peripheral portion and the outer peripheral region of the semiconductor wafer 109 can be alleviated to make the height distribution of the equipotential surface of the bias potential above these regions uniform. Therefore, the reliability of the plasma processing device is improved, and the yield rate of the plasma processing of the semiconductor wafer 109 can be improved.

[0064] In addition, the thin film electrode 139b includes: a first portion 139b1 located at a lower position than the back surface 109b of the semiconductor wafer 109; a second portion 139b2 located at a higher position than the main surface 109a of the semiconductor wafer 109; and a third portion 139b3 connecting the first portion 139b1 and the second portion 139b2. In addition, the first portion 139b1 has an "overlapping region" overlapping with the semiconductor wafer 109 when viewed from above. In addition, the first portion 139b1 is arranged to be separated from the back surface 109b by a distance A in the vertical direction, and the third portion 139b3 is arranged to be separated from the end 109e of the semiconductor wafer 109 by a distance B in the horizontal direction, and the distance A is smaller than the distance B.

[0065] The sheath potential distribution of the peripheral area of ​​the semiconductor chip 109 obtained by supplying high-frequency power to the thin film electrode 139b is mainly formed by the first part 139b1 and the second part 139b2. By bringing the first part 139b1 and the second part 139b2 close to the semiconductor chip 109, the potential distribution can enhance the electric field strength and expand the control domain of the sheath potential. However, if the third part 139b3 is brought too close to the semiconductor chip 109, the sheath potential distribution will have a steep slope along the shape of the base ring 113 near the end 109e of the semiconductor chip 109, and it will become inappropriate as a control domain. On the other hand, when the first part 139b1 is brought close to the back side 109b of the semiconductor chip 109, the influence is shown only in the sheath potential distribution near the end 109e of the semiconductor chip 109, and the controllability becomes better than when the third part 139b3 is brought too close. As described above, in order to have an appropriate sheath potential control domain, it is desirable that the correlation (A is smaller than the distance B) be smaller than the distance A. <B)。

[0066] In addition, since the upper surface of the dielectric ring 139 having the thin film electrode 139b is covered with the dielectric susceptor ring 113 and does not contact the plasma 116, an excessive temperature rise can be suppressed. Furthermore, since the surface of the dielectric ring 139 in contact with the susceptor ring 113 is composed of a rough surface (for example, the surface roughness Ra is 1.0 or more), heat transfer from the susceptor ring 113 that has become high temperature due to contact with the plasma to the dielectric ring 139 can be suppressed. Therefore, the reliability of the plasma processing device can be improved, and further, since the occurrence of processing shape deviation can be suppressed, the manufacturing yield of the semiconductor wafer 109 can be improved.

[0067] Furthermore, by supplying high-frequency power from the single high-frequency power source 124 to the electrode substrate 108 of the sample stage ST and the thin-film electrode 139b provided on the dielectric ring 139, electrical mutual interference between the high-frequency power applied to the electrode substrate 108 and the high-frequency power applied to the thin-film electrode 139b can be suppressed. Under the back surface 109b of the semiconductor wafer 109, the inner peripheral end 139bie of the thin-film electrode 139b can be brought close to the sample stage ST, and the first portion 139b1 and the second portion 139b2 of the thin-film electrode 139b can be brought close to the semiconductor wafer 109. As a result, since appropriate electric field control and sheath potential control can be performed at the peripheral portion and the outer peripheral region of the semiconductor wafer 109, the reliability of the plasma processing apparatus can be improved and the yield rate of the semiconductor wafer 109 can be improved.

[0068] (Variant 1)

[0069] Figure 5 This is a cross-sectional view showing the periphery of a wafer mounting electrode of a plasma processing apparatus according to Modification 1. Figure 5 yes Figure 4A variation of .

[0070] The shape of the dielectric ring 139' is similar to the above-mentioned embodiment. Figure 4 The upper surface of the dielectric ring 139a' includes a first surface 139a1, a third surface 139a3', and a second surface 139a2. The third surface 139a3' has an inclination greater than 90° relative to the first surface 139a1 and the second surface 139a2. The third surface 139a3' has an inclination close to the sample stage ST along the vertical direction.

[0071] The annular thin film electrode 139b' has a ring width from the inner peripheral end 139bie to the outer peripheral end 139b'e, and has a first portion 139b1, a third portion 139b3', and a second portion 139b2 in the width direction. The first portion 139b1, the third portion 139b3', and the second portion 139b2 are formed corresponding to the first surface 139a1, the third surface 139a3', and the second surface 139a2 of the upper surface of the dielectric ring 139a', respectively. Therefore, the third portion 139b3' has an inclination close to the sample stage ST along the vertical direction.

[0072] In the first modification, similarly to the above-mentioned embodiment, in a plan view, the first portion 139b1 has an "overlapping region" with the semiconductor wafer 109. In addition, the first portion 139b1 is disposed at a distance A apart from the back surface 109b in the vertical direction, and the third portion 139b3' is disposed at a distance B' apart from the end portion 109e of the semiconductor wafer 109 in the horizontal direction, and the distance A is smaller than the distance B'.

[0073] According to Modification 1, compared with the above-described embodiment, the lower portion of the third portion 139b3' can be brought closer to the end 109e of the semiconductor wafer 109. Therefore, the sheath potential distribution around the end 109e of the semiconductor wafer 109 is affected, and the sheath potential control region can be changed.

[0074] (Variant 2)

[0075] Figure 6 2 is a cross-sectional view schematically showing the structure of a plasma processing device according to a second modification. Figure 2 In the second modification, the high frequency power source 124 is connected to the conductor film 111 via the matching device 129 and the junction box 127 .

[0076] exist Figure 6 In the structure, the load impedance is corrected by appropriately changing the high frequency power value of the high frequency power source 124. Figure 2 The sheath potential distribution of the peripheral portion and the outer peripheral region of the semiconductor wafer 109 formed by the conductive film 111 becomes similar to Figure 2 The sheath potential distribution in the case of is the same, and the same effect as the above-mentioned embodiment can be obtained.

[0077] In addition, in the above-mentioned embodiment or modification, the etched film pre-arranged on the main surface of the semiconductor wafer 109 before processing is a silicon oxide film, and tetrafluoromethane gas, oxygen gas, and trifluoromethane gas are used as a processing gas for etching and a cleaning gas for cleaning. In addition, as the etched film, not only silicon oxide films can be used, but also polysilicon films, photoresist films, anti-reflection organic films, anti-reflection inorganic films, organic materials, inorganic materials, silicon oxide films, silicon nitride oxide films, silicon nitride films, Low-k materials, High-k materials, amorphous carbon films, Si substrates, metal materials, etc. can be used, and the same effect can be obtained in these cases.

[0078] In addition, as the processing gas for etching, chlorine gas, hydrogen bromide gas, tetrafluoromethane gas, trifluoromethane gas, difluoromethane gas, argon gas, helium gas, oxygen, nitrogen gas, carbon dioxide gas, carbon monoxide gas, hydrogen gas, etc. can be used. Furthermore, as the processing gas for etching, ammonia gas, octafluoropropane gas, nitrogen trifluoride gas, sulfur hexafluoride gas, methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, neon gas, krypton gas, xenon gas, radon gas, etc. can be used.

[0079] The invention made by the inventors has been specifically described above based on the embodiment, but the present invention is not limited to the embodiment, and it is self-evident that various changes can be made within the scope of the gist thereof. For example, the wafer mounting electrode 120 may include a heater for adjusting the temperature of the semiconductor wafer 109 inside the dielectric film 140 or inside the substrate electrode 108. In addition, for such temperature adjustment, at least one temperature sensor that can be arranged to communicate with the controller 170 and detect the temperature may be provided inside the substrate electrode 108.

[0080] In the above embodiment, the following structure is described: an electric field of microwaves with a frequency of 2.45 GHz and a magnetic field that can form ECR are supplied to the processing chamber 104, so that the processing gas is discharged to form plasma. However, the structure described in the above embodiment can also play the same role and effect as described in the above embodiment, etc., when other discharges (UHF discharge with magnetic field, capacitive coupling discharge, inductive coupling discharge, magnetron discharge, surface wave excitation discharge, transfer coupling discharge) are used to form plasma. In addition, the above embodiment and Modifications 1 and 2 can also play the same role and effect when applied to a wafer mounting electrode arranged in other plasma processing devices that perform plasma processing, such as a plasma CVD device, an ashing device, a surface modification device, etc.

[0081] Description of Reference Numerals

[0082] OS Center

[0083] OU Center

[0084] ST Sample Stage

[0085] 100 Plasma Etching Device

[0086] 101 Vacuum Container

[0087] 102 Shower Panel

[0088] 102a Gas inlet hole

[0089] 103 Dielectric Window

[0090] 104 Processing Room

[0091] 105 Waveguide

[0092] 106 Power supply for generating electric field

[0093] 107 Magnetic field generating coil

[0094] 108 Electrode substrate

[0095] 108a Upper surface

[0096] 108d concave part (recessed part)

[0097] 108p convex part (protruding part)

[0098] 109 Semiconductor wafer

[0099] 109a Main surface

[0100] 109b Back

[0101] 109e End (arc part)

[0102] 110 Vacuum exhaust port

[0103] 111 Conductive film

[0104] 112 Ground

[0105] 113 Base ring

[0106] 116 Plasma

[0107] 120 Wafer mounting electrode

[0108] 120a Loading surface

[0109] 120b Upper surface

[0110] 124 High frequency power supply

[0111] 125 High frequency filter

[0112] 126 DC power supply

[0113] 127 Junction Box

[0114] 129 Matcher

[0115] 130 Load impedance variable box

[0116] 139 Dielectric Ring

[0117] 139a Dielectric Ring

[0118] 139a1 Page 1

[0119] 139a2 Page 2

[0120] 139a3 Page 3

[0121] 139a3´ Page 3

[0122] 139b Thin Film Electrode

[0123] 139b1 Part 1

[0124] 139b2 Part 2

[0125] 139b3 Part 3

[0126] 139b3´ Part 3

[0127] 139bie inner peripheral end

[0128] 139bоe peripheral end

[0129] 140 Dielectric Film

[0130] 150 Insulation Board

[0131] 151 Ground Plate

[0132] 152 Refrigerant flow path

[0133] 160 Electric field / magnetic field forming unit

[0134] 170 controller.

Claims

1. A plasma processing device, characterized in that: have: A sample stage, which is arranged in a plasma-forming processing chamber inside a vacuum processing device, and has a mounting surface on which a wafer to be processed is mounted, the sample stage comprising: a cylindrical convex portion arranged in the center of an upper portion and having the mounting surface on an upper surface, a concave portion arranged in an annular shape surrounding the convex portion and constituting an outer peripheral portion of the upper portion, and a high-frequency electrode to which high-frequency power is supplied during processing of the wafer; as well as A base ring is arranged in the concave portion so as to surround the convex portion, and comprises an annular thin film electrode and a dielectric portion, the thin film electrode is supplied with a high frequency power having a magnitude different from that supplied to the high frequency electrode during the processing of the wafer, and the dielectric portion is arranged above the thin film electrode so as to cover the thin film electrode, The thin film electrode includes: a first portion constituting an inner peripheral end portion and located at a position lower than the mounting surface and having a flat portion; a flat second portion arranged on the outer peripheral side of the first portion and the wafer and located at a position higher than the upper surface of the wafer; and a third portion connecting the outer peripheral edge portion of the first portion and the inner peripheral edge portion of the second portion to form a stepped portion, The base ring comprises: an inner peripheral end portion which is located below the outer peripheral end portion of the chip when viewed from above when the chip is placed on the mounting surface and covers the first portion of the thin film electrode; an outer peripheral portion which has a flat upper surface and covers the second portion; and a portion which connects the inner peripheral end portion and the outer peripheral portion as a whole and has an upper surface which is inclined to become higher toward the periphery and covers the second portion.

2. The plasma processing device according to claim 1, characterized in that: The inner peripheral end of the thin film electrode is located below the outer peripheral end of the wafer placed on the placement surface in a plan view.

3. The plasma processing device according to claim 1 or 2, characterized in that: The plasma processing apparatus includes an insulating ring made of a dielectric material disposed between an upper surface of the recess and the thin-film electrode.

4. The plasma processing device according to claim 1 or 2, characterized in that: The sample stage includes a substrate and a dielectric film which is disposed on the substrate and has an upper surface forming the mounting surface.

5. The plasma processing device according to claim 4, characterized in that: The plasma processing apparatus includes a high-frequency power supply that supplies the high-frequency power to the substrate.

6. The plasma processing device according to claim 4, characterized in that: The dielectric film includes a conductor film that supplies the high-frequency power therein.

7. A plasma processing method, comprising placing a wafer to be processed on a mounting surface on an upper portion of a sample stage disposed in a processing chamber inside a vacuum container, and processing the wafer using plasma formed in the processing chamber, The sample stage comprises: a cylindrical convex portion arranged in the central part of the upper part and having the mounting surface on the upper surface; a concave portion arranged in an annular shape surrounding the convex portion and constituting the outer peripheral portion of the upper part; a high-frequency electrode to which high-frequency power is supplied during the processing of the wafer; and a base ring, which is arranged in the concave portion surrounding the convex portion and has an annular thin-film electrode and a dielectric portion arranged above the thin-film electrode to cover the thin-film electrode. The thin film electrode includes: a first portion constituting an inner peripheral end portion and located at a position lower than the mounting surface and having a flat portion; a flat second portion arranged on the outer peripheral side of the first portion and the wafer and located at a position higher than the upper surface of the wafer; and a third portion connecting the outer peripheral edge portion of the first portion and the inner peripheral edge portion of the second portion to form a stepped portion, The base ring comprises: an inner peripheral end portion which is located below the outer peripheral end portion of the wafer in a plan view when the wafer is placed on the placement surface and covers the first portion of the thin film electrode, an outer peripheral portion which has a flat upper surface and covers the second portion, and a portion which connects the inner peripheral end portion and the outer peripheral portion as a whole and has an upper surface which is inclined to become higher toward the periphery and covers the second portion. A high frequency power having a magnitude different from that of the high frequency power supplied to the high frequency electrode during processing of the wafer is supplied.

8. The plasma processing method according to claim 7, characterized in that: The inner peripheral end of the thin film electrode is located below the outer peripheral end of the wafer placed on the placement surface in a plan view.

9. The plasma processing method according to claim 7 or 8, characterized in that: The present invention comprises an insulating ring made of a dielectric material and arranged between an upper surface of the recessed portion and the thin film electrode.

10. The plasma processing method according to claim 7 or 8, characterized in that: The sample stage includes a substrate and a dielectric film which is disposed on the substrate and has an upper surface forming the mounting surface.

11. The plasma processing method according to claim 10, characterized in that: The high frequency power is supplied to the substrate.

12. The plasma processing method according to claim 10, characterized in that: The high-frequency power is supplied to the conductor film disposed inside the dielectric film.

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