3D DRAM three-dimensional stacked chip packaging structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor preparation, in particular to a 3D DRAM three-dimensional stacked chip packaging structure and a preparation method thereof.The 3D DRAM three-dimensional stacked chip packaging structure comprises a packaging substrate, an intermediary layer substrate, a three-dimensional stacked chip assembly, a heat dissipation bridge and a heat dissipation cover plate, and the intermediary layer substrate is arranged on the packaging substrate; the three-dimensional stacked chip assembly comprises a plurality of chip assemblies which are sequentially arranged from bottom to top, the size of the chip assembly on the lowest layer is larger than that of the chip assembly on the upper layer, and the chip assembly on the lowest layer is arranged on the interposer substrate; the heat dissipation bridge is arranged on the edge of the chip assembly on the lowest layer, and a gap exists between the heat dissipation bridge and the chip assembly on the upper layer. And the heat dissipation cover plate is arranged on the packaging substrate and covers the interposer substrate, the three-dimensional stacked chip assembly and the heat dissipation bridge. According to the three-dimensional stacked chip packaging structure disclosed by the invention, the heat dissipation problem of the 3D DRAM three-dimensional stacked chip is obviously improved through a series of elaborately designed component layout and configuration.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a 3D DRAM three-dimensional stacked chip packaging structure and a manufacturing method thereof. Background Art

[0002] With the rapid development of information technology, the requirements for storage density, performance and power consumption are increasing. Traditional two-dimensional dynamic random access memory (2D DRAM) can no longer meet the needs of high-performance computing and big data applications. As an advanced storage technology, 3D DRAM significantly improves storage density, reduces power consumption and increases bandwidth by stacking multiple storage layers and using vertical interconnection technology, becoming an important solution to current storage challenges. However, 3D DRAM packaging technology also faces a series of challenges, especially heat dissipation, which limits its integration and performance improvement.

[0003] 3D DRAM achieves higher storage density by stacking multiple storage layers vertically together. Each layer contains a large number of storage cells arranged in rows and columns, similar to the planar arrangement of traditional DRAM. Vertical interconnect technology (Through-Silicon Via, TSV) is crucial in 3D DRAM, which connects different storage layers by drilling holes in the wafer and filling them with conductive materials. TSV technology can significantly reduce signal transmission paths, reduce latency and increase data transmission rates.

[0004] In the structure of three-dimensional stacked chips, different types of chips are stacked together, which makes it difficult for the heat of the chips to dissipate. Stacked chips are prone to failure due to high junction temperature, thus limiting the integration and performance improvement of the entire device.

[0005] Specifically, the heat dissipation problems in stacked chips are mainly reflected in the following aspects:

[0006] Heat is difficult to dissipate: In stacked chips, the upper chip is composed of multiple layers, each layer includes a micro-bump array interconnection form, and is filled with a bottom fill layer (underfill). This structure results in a large thermal resistance from the bottom to the external heat dissipation cover, which makes the temperature of the bottom chip too high and cannot guarantee normal operation.

[0007] Complex process: Some existing heat dissipation technologies are complex, and some technologies introduce large series thermal resistance when plastic packaging materials are introduced, making it difficult to fully dissipate the heat. In particular, the thermal resistance of the bottom chip to the outside is too large, the chip temperature is too high, and it is easy to fail.

[0008] Limited performance: Due to heat dissipation issues, the integration and performance of stacked chips are limited. In high temperature environments, the performance of the chips will degrade or even fail, affecting the stability and reliability of the entire system.

[0009] In view of this, the present invention is proposed. Summary of the invention

[0010] The purpose of the present invention is to provide a 3D DRAM three-dimensional stacked chip packaging structure and a preparation method thereof. The three-dimensional stacked chip packaging structure of the present invention significantly improves the heat dissipation problem of 3D DRAM three-dimensional stacked chips through innovative heat dissipation design, optimized space utilization, enhanced structural stability and comprehensive heat dissipation coverage, thereby improving the performance and reliability of the system.

[0011] In a first aspect, the present invention provides a 3D DRAM three-dimensional stacked chip packaging structure, comprising a packaging substrate, an interposer substrate, a three-dimensional stacked chip assembly, a heat dissipation bridge and a heat dissipation cover plate,

[0012] Wherein, the interposer substrate is arranged on the packaging substrate;

[0013] The three-dimensional stacked chip assembly includes a plurality of chip assemblies arranged in sequence from bottom to top, and the size of the chip assembly at the bottom layer is larger than the size of the chip assembly at the top layer, and the chip assembly at the bottom layer is arranged on the interposer substrate;

[0014] The heat dissipation bridge is arranged at the edge of the chip assembly of the lowest layer, and there is a gap between the heat dissipation bridge and the chip assembly of the upper layer;

[0015] The heat dissipation cover plate is arranged on the packaging substrate and covers the interposer substrate, the three-dimensional stacked chip assembly and the heat dissipation bridge.

[0016] As a preferred embodiment of the present technical solution, the interposer substrate comprises a substrate body and the first conductive structure arranged in the substrate body, and the bottom of the substrate body is arranged on the packaging substrate through a second conductive structure.

[0017] As a preferred embodiment of the present technical solution, the three-dimensional stacked chip assembly includes a first chip assembly and a plurality of second chip assemblies sequentially arranged on the first chip assembly, the size of the first chip assembly is larger than the size of the second chip assembly, and the plurality of second chip assemblies are sequentially arranged in the central area of ​​the first chip assembly, and the heat dissipation bridge is arranged on the first chip assembly around the plurality of second chip assemblies.

[0018] As a preferred embodiment of the present technical solution, a plurality of solder balls are arranged between the first chip component and the substrate body, between the second chip component and the first chip component, and between the second chip components.

[0019] As a preferred embodiment of the present technical solution, a first heat dissipation interface is provided between the heat dissipation bridge, the second chip assembly on the uppermost layer and the heat dissipation cover plate.

[0020] As a preferred embodiment of the present technical solution, a radiator is further included, and the radiator is arranged above the heat dissipation cover plate.

[0021] As a preferred embodiment of the present technical solution, a second heat dissipation interface is provided between the radiator and the heat dissipation cover plate.

[0022] As a preferred embodiment of the present technical solution, a first cavity is formed between the heat dissipation bridge and the second chip component, and a second cavity is formed between the heat dissipation bridge and the heat dissipation cover plate, wherein a plurality of first through holes are opened on the heat dissipation bridge, and the first through holes connect the first cavity and the second cavity.

[0023] As a preferred embodiment of the present technical solution, a plurality of second through holes are formed on the heat dissipation cover plate, and the second through holes connect the second cavity with the external environment.

[0024] In a second aspect, the present invention further provides a method for preparing the above-mentioned three-dimensional stacked chip packaging structure, comprising the following steps:

[0025] Disposing an interposer substrate on the packaging substrate;

[0026] sequentially arranging a first chip assembly and one or more second chip assemblies on the interposer substrate;

[0027] Disposing a heat dissipation bridge at the edge of the first chip assembly;

[0028] A first heat dissipation interface is arranged above the heat dissipation bridge and the first chip assembly;

[0029] A heat dissipation cover plate is arranged on the packaging substrate, and covers the interposer substrate, the first chip assembly and one or more second chip assemblies, the heat dissipation bridge, and the first heat dissipation interface;

[0030] A second heat dissipation interface and a heat sink are sequentially arranged on the heat dissipation cover plate.

[0031] The 3D DRAM three-dimensional stacked chip packaging structure of the present invention has at least the following beneficial effects:

[0032] The 3D DRAM three-dimensional stacked chip packaging structure of the present invention includes a packaging substrate, an interposer substrate, a three-dimensional stacked chip assembly, a heat dissipation bridge and a heat dissipation cover plate. By arranging a heat dissipation bridge at the edge of the bottom chip assembly of the three-dimensional stacked chip assembly, the heat generated by the lower chip assembly can not only be effectively conducted out, but also because it is located at the edge position, it avoids direct contact with the upper chip assembly, thereby reducing the accumulation of heat in the upper chip assembly, ensuring that the heat can be more evenly distributed and effectively dissipated through the heat dissipation bridge, and improving the overall heat dissipation efficiency. The design that the size of the bottom chip assembly is larger than that of the upper chip assembly not only conforms to the common hierarchical decreasing structure of the three-dimensional stacked chip, but also cleverly utilizes the packaging space, so that the heat dissipation bridge can be more stably arranged at the edge of the larger lower chip assembly without affecting the layout and function of the upper chip assembly, and at the same time optimizes the space utilization inside the package, making the entire packaging structure more compact and efficient. The setting of the heat dissipation bridge not only helps to dissipate heat, but also enhances the structural stability between the three-dimensional stacked chip assembly and the packaging substrate through physical connection, helps to resist stress and vibration during the packaging process, and improves the reliability and durability of the packaging structure. Finally, the heat dissipation cover covers the entire packaging structure, including the interposer substrate, the three-dimensional stacked chip assembly and the heat dissipation bridge, forming a complete heat dissipation system. This comprehensive coverage design ensures that heat can be effectively dissipated from all directions, avoiding the occurrence of local overheating. At the same time, the material and thickness of the heat dissipation cover can be optimized according to specific needs to achieve the best heat dissipation effect. Therefore, the 3D DRAM three-dimensional stacked chip packaging structure of the present invention significantly improves the heat dissipation problem of the 3D DRAM three-dimensional stacked chip through innovative heat dissipation design, optimized space utilization, enhanced structural stability and comprehensive heat dissipation coverage, and improves the performance and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a structural schematic diagram of the 3D DRAM three-dimensional stacked chip packaging structure of the present invention.

[0035] Description of reference numerals:

[0036] 1: packaging substrate; 2: interposer substrate; 3: heat dissipation bridge; 4: heat dissipation cover; 5: second conductive structure; 6: first chip assembly; 7: second chip assembly; 8: solder ball material; 9: first heat dissipation interface; 10: heat sink; 11: second heat dissipation interface; 12: first cavity; 13: second cavity; 14: first through hole; 15: second through hole. DETAILED DESCRIPTION

[0037] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] Example 1

[0041] The present embodiment provides a 3D DRAM three-dimensional stacked chip packaging structure, including a packaging substrate 1, an interposer substrate 2, a three-dimensional stacked chip assembly, a heat dissipation bridge 3 and a heat dissipation cover plate 4, wherein the interposer substrate 2 is arranged on the packaging substrate 1; the three-dimensional stacked chip assembly includes a plurality of chip assemblies arranged in sequence from bottom to top, and the size of the chip assembly in the bottom layer is larger than the size of the chip assembly in the upper layer, and the chip assembly in the bottom layer is arranged on the interposer substrate 2; the heat dissipation bridge 3 is arranged at the edge of the chip assembly in the bottom layer, and there is a gap between it and the chip assembly in the upper layer; the heat dissipation cover plate 4 is arranged on the packaging substrate 1, and covers the interposer substrate 2, the three-dimensional stacked chip assembly and the heat dissipation bridge 3.

[0042] The 3D DRAM three-dimensional stacked chip packaging structure of the present invention includes a packaging substrate 1, an interposer substrate 2, a three-dimensional stacked chip assembly, a heat dissipation bridge 3 and a heat dissipation cover plate 4. By arranging the heat dissipation bridge 3 at the edge of the bottom chip assembly of the three-dimensional stacked chip assembly, not only can the heat generated by the bottom chip assembly be effectively conducted away, but also because it is located at the edge position, it avoids direct contact with the upper chip assembly, thereby reducing the accumulation of heat in the upper chip assembly, ensuring that the heat can be more evenly distributed and effectively dissipated through the heat dissipation bridge 3, and improving the overall heat dissipation efficiency. The design that the bottom chip assembly is larger than the upper chip assembly not only conforms to the common hierarchical decreasing structure of the three-dimensional stacked chip, but also cleverly utilizes the packaging space, so that the heat dissipation bridge 3 can be more stably arranged at the edge of the larger lower chip assembly without affecting the layout and function of the upper chip assembly, and at the same time optimizes the space utilization inside the package, making the entire packaging structure more compact and efficient. The setting of the heat dissipation bridge 3 not only helps to dissipate heat, but also enhances the structural stability between the three-dimensional stacked chip assembly and the packaging substrate 1 through physical connection, helps to resist stress and vibration during the packaging process, and improves the reliability and durability of the packaging structure. Finally, the heat dissipation cover plate 4 covers the entire packaging structure, including the interposer substrate 2, the three-dimensional stacked chip assembly and the heat dissipation bridge 3, forming a complete heat dissipation system. This comprehensive coverage design ensures that heat can be effectively dissipated from all directions, avoiding the occurrence of local overheating. At the same time, the material and thickness of the heat dissipation cover plate 4 can be optimized according to specific needs to achieve the best heat dissipation effect.

[0043] Therefore, the 3D DRAM three-dimensional stacked chip packaging structure of the present invention significantly improves the heat dissipation problem of the 3D DRAM three-dimensional stacked chip through innovative heat dissipation design, optimized space utilization, enhanced structural stability and comprehensive heat dissipation coverage, and improves the performance and reliability of the system.

[0044] On the basis of the above technical solution, further, the interposer substrate 2 includes a substrate body and the first conductive structure arranged in the substrate body, and the bottom of the substrate body is arranged on the packaging substrate 1 through the second conductive structure 5. The interposer substrate 2 realizes high-speed signal transmission between the packaging substrate 1 and the three-dimensional stacked chip assembly through the first conductive structure inside it, which helps to reduce signal delay and increase data transmission rate, thereby meeting the needs of high-performance computing and big data applications. At the same time, the interposer substrate 2 can also serve as part of the heat dissipation path to effectively conduct the heat generated by the three-dimensional stacked chip assembly to the packaging substrate 1, and then dissipate it through the heat dissipation structure of the packaging substrate 1, which helps to reduce the chip temperature and improve the stability and reliability of the system. Finally, as a part of the packaging structure, the interposer substrate 2 enhances the stability of the entire packaging structure through its solid structure and close connection with the packaging substrate 1 and the three-dimensional stacked chip assembly.

[0045] Specifically, the substrate body is usually made of silicon material, because silicon has good electrical conductivity and thermal conductivity, which can meet the needs of high-performance packaging. In addition, the substrate body can also adopt multi-layer wiring technology, and achieve high-density integration through micro blind hole / buried hole technology, further improving signal transmission efficiency and heat dissipation performance. The first conductive structure is usually a conductive column or conductive line made of metal (such as copper, aluminum or gold, etc.), and the first conductive structure is electrically connected to the packaging substrate 1 and the three-dimensional stacked chip assembly through a through hole or micro blind hole / buried hole that runs through the substrate body. The shape and layout of the first conductive structure can be optimized according to the specific application requirements to achieve the best signal transmission efficiency and heat dissipation performance.

[0046] On the basis of the above technical solution, it is further preferred that the three-dimensional stacked chip assembly includes a first chip assembly 6 and a plurality of second chip assemblies 7 arranged in sequence on the first chip assembly 6, the size of the first chip assembly 6 is larger than the size of the second chip assembly 7, and the plurality of second chip assemblies 7 are arranged in sequence in the central area of ​​the first chip assembly 6, and the heat dissipation bridge 3 is arranged on the first chip assembly 6 around the plurality of second chip assemblies 7.

[0047] By setting a heat dissipation bridge 3 at the edge of the bottom first chip assembly 6 of the three-dimensional stacked chip assembly, not only can the heat generated by the bottom chip assembly be effectively conducted away, but also because it is located at the edge, it avoids direct contact with the upper second chip assembly 7, thereby reducing the accumulation of heat in the upper second chip assembly 7, ensuring that the heat can be more evenly distributed and effectively dissipated through the heat dissipation bridge 3, thereby improving the overall heat dissipation efficiency. The design that the bottom chip assembly is larger than the upper chip assembly not only conforms to the common hierarchical decreasing structure of three-dimensional stacked chips, but also cleverly utilizes the packaging space, so that the heat dissipation bridge 3 can be more stably set at the edge of the larger bottom first chip assembly 6 without affecting the layout and function of the upper chip assembly, while optimizing the space utilization inside the package, making the entire package structure more compact and efficient.

[0048] In a specific embodiment of the present invention, a plurality of solder balls 8 are disposed between the first chip assembly 6 and the substrate body, between the second chip assembly 7 and the first chip assembly 6 , and between the second chip assembly 7 .

[0049] In the three-dimensional stacked structure, the solder ball material 8 provides a vertical electrical path, allowing chips at different levels to communicate with each other. In addition, the solder ball material 8 forms a mechanical support between the chip assembly and the substrate body, enhancing the stability of the packaging structure. Finally, the solder ball material 8 not only serves as an electrical connection, but also as a part of the heat dissipation, which helps to transfer the heat generated by the chip to the substrate body or other heat dissipation structures. Therefore, through a reasonable layout and number of solder balls, the heat dissipation performance can be optimized and the chip temperature can be reduced.

[0050] Specifically, the solder ball material 8 is usually made of metal materials with good electrical conductivity, such as copper, tin, silver or their alloys. These materials have good electrical conductivity and thermal conductivity, and can meet the needs of high-performance packaging. In particular, certain alloy materials such as tin-silver-copper (Sn / Ag / Cu) alloys have been widely used in three-dimensional stacked chip packaging due to their good mechanical and electrical properties. The shape of the solder ball material 8 is usually spherical or approximately spherical, which helps to ensure that they form uniform contact between chip components and substrate bodies at different levels. However, depending on the specific application requirements and packaging process, the shape of the solder ball material 8 may also vary. For example, in some cases, flattened or specially shaped solder ball materials 8 may be used to adapt to specific packaging structures and process requirements. In addition, the diameter and spacing of the solder ball material 8 are also important parameters, which will affect the electrical, mechanical and heat dissipation properties of the packaging structure. Therefore, when designing and manufacturing a three-dimensional stacked chip packaging structure, it is necessary to carefully consider the material, shape, diameter and spacing of the solder ball material 8 to ensure the best packaging effect and performance.

[0051] As a preferred embodiment of the present technical solution, a first heat dissipation interface 9 is arranged between the heat dissipation bridge 3, the second chip component 7 on the top layer and the heat dissipation cover plate 4. The setting of the first heat dissipation interface 9 can fill or reduce the gap between the 3D DRAM three-dimensional stacked chip and the heat dissipation cover plate 4 to promote heat conduction between components.

[0052] Specifically, the material of the first heat dissipation interface 9 of the present invention includes a polymer matrix, a phase change polymer, a substrate based on polysilicon, a matrix additive (flux), a filler, and the like.

[0053] On the basis of the above technical solution, it is further preferred that the 3D DRAM three-dimensional stacked chip packaging structure of the present invention further includes a heat sink 10, which is arranged above the heat dissipation cover plate 4, and a second heat dissipation interface 11 is arranged between the heat sink 10 and the heat dissipation cover plate 4. The heat sink 10 can quickly absorb and dissipate the heat conducted from the heat dissipation cover plate 4, effectively reducing the operating temperature of the three-dimensional stacked chip assembly. The heat sink 10 can significantly improve the heat dissipation efficiency by increasing the heat dissipation area and optimizing the heat dissipation structure, ensuring that the chip can remain stable under long-term high-load operation.

[0054] Specifically, according to the specific needs and heat dissipation performance requirements of the three-dimensional stacked chip packaging structure, common types of heat sinks 10 include air-cooled heat sinks 10, liquid-cooled heat sinks 10, and the like.

[0055] A second heat dissipation interface 11 is further provided between the heat sink 10 and the heat dissipation cover plate 4 of the present invention, and the heat sink 10 is tightly connected to the heat dissipation cover plate 4 through the second heat dissipation interface 11 to ensure that heat can be efficiently transferred from the heat dissipation cover plate 4 to the heat sink 10. Specifically, the second heat dissipation interface 11 here includes a heat conductive medium such as a thermal conductive glue and a thermal conductive pad.

[0056] On the basis of the above technical solution, more preferably, a first cavity 12 is formed between the heat dissipation bridge 3 and the second chip assembly 7, and a second cavity 13 is formed between the heat dissipation bridge 3 and the heat dissipation cover plate 4, wherein a plurality of first through holes 14 are provided on the heat dissipation bridge 3, and the first through holes 14 connect the first cavity 12 and the second cavity 13, and a plurality of second through holes 15 are provided on the heat dissipation cover plate 4, and the second through holes 15 connect the second cavity 13 with the external environment.

[0057] The design of the first cavity 12 and the second cavity 13 increases the volume of the heat dissipation channel, which is beneficial to the storage and conduction of heat. The first through hole 14 and the second through hole 15, as the key part of the heat dissipation channel, enable the heat to be more smoothly conducted from the chip assembly to the heat dissipation cover plate 4, and finally dissipated to the external environment. In addition, through the design of the heat dissipation bridge 3 and the through hole, the heat is more evenly distributed in the three-dimensional stacked chip packaging structure, avoiding the problem of local overheating.

[0058] Example 2

[0059] This embodiment provides a method for preparing the above-mentioned 3D DRAM three-dimensional stacked chip packaging structure, comprising the following steps:

[0060] Precisely place the interposer substrate 2 on the package substrate 1, ensure that the first conductive structure is aligned with the corresponding conductive structure on the package substrate 1, and fix the interposer substrate 2 on the package substrate 1 using a suitable adhesive or welding technique;

[0061] Place the first chip assembly 6 on the interposer substrate 2, ensure that it is aligned with the conductive structure on the interposer substrate 2, and use solder balls 8 or other conductive connecting materials to connect the first chip assembly 6 to the interposer substrate 2; sequentially place one or more second chip assemblies 7 above or beside the first chip assembly 6, ensure that they are aligned with the conductive structure on the interposer substrate 2 or the first chip assembly 6, and similarly use solder balls 8 or other conductive connecting materials to connect these chip assemblies;

[0062] The heat dissipation bridge 3 is precisely placed at the edge of the first chip assembly 6 to ensure that a certain gap is formed between the heat dissipation bridge 3 and the chip assembly to form a first cavity 12, and the heat dissipation bridge 3 is fixed to the package substrate 1 or the interposer substrate 2 using a suitable adhesive or welding technology;

[0063] A first heat dissipation interface 9 is provided above the heat dissipation bridge 3 and the first chip assembly 6. This is usually a material layer with good thermal conductivity, such as thermal conductive glue or thermal conductive pad, to ensure that the first heat dissipation interface 9 is in close contact with the heat dissipation bridge 3 and the second chip assembly 7 to provide a good heat conduction path;

[0064] Place the heat dissipation cover plate 4 on the package substrate 1, ensure that it completely covers the interposer substrate 2, the first chip assembly 6, the second chip assembly 7, the heat dissipation bridge 3 and the first heat dissipation interface 9, and fix the heat dissipation cover plate 4 on the package substrate 1 using appropriate fixing techniques (such as screws, buckles, etc.);

[0065] The second heat dissipation interface 11 and the heat sink 10 are sequentially arranged on the heat dissipation cover plate 4 , and the heat sink 10 is fixed on the heat dissipation cover plate 4 using appropriate fixing techniques (such as screws, buckles, adhesives, etc.).

[0066] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3D DRAM three-dimensional stacked chip packaging structure, characterized in that: It comprises a packaging substrate (1), an intermediate layer substrate (2), a three-dimensional stacked chip assembly, a heat dissipation bridge (3) and a heat dissipation cover plate (4), Wherein, the interposer substrate (2) is arranged on the packaging substrate (1); The three-dimensional stacked chip assembly comprises a plurality of chip assemblies arranged in sequence from bottom to top, and the size of the chip assembly at the bottom layer is larger than the size of the chip assembly at the top layer, and the chip assembly at the bottom layer is arranged on the interposer substrate (2); The heat dissipation bridge (3) is arranged at the edge of the chip assembly at the bottom layer, and there is a gap between the heat dissipation bridge (3) and the chip assembly at the upper layer; The heat dissipation cover plate (4) is arranged on the packaging substrate (1) and covers the intermediate layer substrate (2), the three-dimensional stacked chip assembly and the heat dissipation bridge (3).

2. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 1, characterized in that: The interposer substrate (2) comprises a substrate body and a first conductive structure arranged in the substrate body, and the bottom of the substrate body is arranged on the packaging substrate (1) via a second conductive structure (5).

3. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 1, characterized in that: The three-dimensional stacked chip component comprises a first chip component (6) and a plurality of second chip components (7) arranged in sequence on the first chip component (6); the size of the first chip component (6) is larger than the size of the second chip component (7), and the plurality of second chip components (7) are arranged in sequence in a central area of ​​the first chip component (6); and the heat dissipation bridge (3) surrounds the plurality of second chip components (7) and is arranged on the first chip component (6).

4. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 3, characterized in that: A plurality of solder balls (8) are arranged between the first chip component (6) and the substrate body, between the second chip component (7) and the first chip component (6), and between the second chip component (7).

5. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 3, characterized in that: A first heat dissipation interface (9) is provided between the heat dissipation bridge (3), the second chip assembly (7) on the uppermost layer, and the heat dissipation cover plate (4).

6. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 1, characterized in that: It also comprises a radiator (10), wherein the radiator (10) is arranged above the heat dissipation cover plate (4).

7. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 6, characterized in that: A second heat dissipation interface (11) is provided between the radiator (10) and the heat dissipation cover plate (4).

8. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 3, characterized in that: A first cavity (12) is formed between the heat dissipation bridge (3) and the second chip assembly (7), and a second cavity (13) is formed between the heat dissipation bridge (3) and the heat dissipation cover plate (4), wherein a plurality of first through holes (14) are provided on the heat dissipation bridge (3), and the first through holes (14) communicate with the first cavity (12) and the second cavity (13).

9. The 3D DRAM three-dimensional stacked chip packaging structure according to claim 8, characterized in that: The heat dissipation cover plate (4) is provided with a plurality of second through holes (15), and the second through holes (15) connect the second cavity (1) 3 with the external environment.

10. The method for preparing the 3D DRAM three-dimensional stacked chip packaging structure according to any one of claims 1 to 9, characterized in that: The following steps are involved: Arranging an intermediate layer substrate (2) on the packaging substrate (1); A first chip component (6) and one or more second chip components (7) are sequentially arranged on the interposer substrate (2); A heat dissipation bridge (3) is provided at the edge of the first chip assembly (6); A first heat dissipation interface (9) is arranged above the heat dissipation bridge (3) and the first chip assembly (6); A heat dissipation cover plate (4) is arranged on the packaging substrate (1) to cover the intermediate layer substrate (2), the first chip component (6) and one or more second chip components (7), the heat dissipation bridge (3), and the first heat dissipation interface (9); A second heat dissipation interface (11) and a heat sink (10) are sequentially arranged on the heat dissipation cover plate (4).

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