Layout structure of power semiconductor module and power semiconductor module

Abstract

The invention discloses a layout structure of a power semiconductor module and the power semiconductor module. Negative electrode power terminals, lower bridge arm chips, upper bridge arm chips and alternating current power terminals of the layout structure are sequentially arranged in the first direction of a substrate, the negative electrode power terminals are arranged in the second direction of the substrate and are arranged on first metal layers respectively, the lower bridge arm chips are arranged in the second direction of the substrate and are arranged on second metal layers respectively, and the alternating current power terminals are arranged in the second direction of the substrate and are arranged on second metal layers respectively. The upper bridge arm chips are arranged in the second direction of the substrate and are arranged on the fourth metal layer, the alternating current power terminals are arranged in the second direction of the substrate and are arranged on the third metal layers, and the positive electrode power terminal and the upper bridge arm chips are sequentially arranged in the second direction of the substrate and are arranged on the fourth metal layer. According to the layout structure of the power semiconductor module, current flows out from one side of the upper bridge arm chip to the lower bridge arm chip, and flows out from the other side of the upper bridge arm chip to the alternating current power terminal, so that the space utilization rate of a power semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of power semiconductor technology, and in particular to a layout structure of a power semiconductor module and a power semiconductor module. Background Art

[0002] In modern power systems, the application scenarios of power semiconductors are very extensive and complex, which requires the functions of power semiconductors to be more and more integrated, so the demand for the power density of power semiconductors is also increasing. However, in the design of traditional power semiconductor modules, such as insulated gate bipolar transistors (IGBTs) or full silicon carbide (SiC) power semiconductor modules, the AC power terminals usually share the same metal layer with the lower bridge arm to achieve current flow. However, this design method shows obvious limitations in the face of high power density requirements.

[0003] Specifically, because the AC power terminals and the lower bridge arms share a metal layer inside traditional power semiconductor modules, the internal space utilization efficiency is low, which limits the layout flexibility of the terminals and the current outflow path of the terminals, thereby affecting the overall heat dissipation performance and electrical characteristics of the power semiconductor module. In addition, this layout method also makes the current outflow position of the terminals inflexible, making it difficult to add KS (Kelvin-Source) signal terminals for improving current accuracy to the power semiconductor module, limiting the overall efficiency improvement of the power module. Summary of the invention

[0004] In view of the above problems, the present application provides a layout structure of a power semiconductor module and a power semiconductor module to solve the above technical problems.

[0005] In a first aspect, the present application provides a layout structure of a power semiconductor module, including: a substrate, at least one pair of lower bridge arm chips and upper bridge arm chips, the same number of negative power terminals as the lower bridge arm chips, the same number of AC power terminals as the lower bridge arm chips, and one positive power terminal;

[0006] The substrate is provided with a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the same number as the lower bridge arm chips;

[0007] The negative power terminal, the lower bridge arm chip, the upper bridge arm chip and the AC power terminal are arranged in sequence along the first direction of the substrate, and each negative power terminal is arranged along the second direction of the substrate and is respectively arranged on each first metal layer, each lower bridge arm chip is arranged along the second direction of the substrate and is respectively arranged on each second metal layer, each upper bridge arm chip is arranged along the second direction of the substrate and is arranged on the fourth metal layer, and each AC power terminal is arranged along the second direction of the substrate and is respectively arranged on each third metal layer;

[0008] The positive power terminal and each upper bridge arm chip are sequentially arranged along the second direction of the substrate and are disposed on the fourth metal layer.

[0009] In some embodiments, in the layout structure of the power semiconductor module provided by the present application, the positive power terminal is configured to receive current and transmit the current to each upper bridge arm chip, the upper bridge arm chip is configured to transmit the current to the corresponding lower bridge arm chip and the corresponding AC power terminal respectively, and the lower bridge arm chip is configured to transmit the current to the corresponding negative power terminal.

[0010] In some embodiments, in the layout structure of the power semiconductor module provided in the present application, at least one pair of lower bridge arm chips and upper bridge arm chips are configured to be connected in a half-bridge manner, or are configured to be connected in a full-bridge manner.

[0011] In some embodiments, in the layout structure of the power semiconductor module provided in the present application, at least one signal terminal metal layer is further provided on the substrate, and each signal terminal metal layer is used to provide a signal terminal;

[0012] Each signal terminal metal layer is arranged in parallel with the first metal layer along the second direction of the substrate, and is arranged in parallel with each third metal layer along the second direction of the substrate.

[0013] In some embodiments, in the layout structure of the power semiconductor module provided by the present application, the signal terminal at least includes a Kelvin source signal terminal.

[0014] In some embodiments, in the layout structure of the power semiconductor module provided by the present application, the upper bridge arm chip and the lower bridge arm chip are silicon carbide metal oxide semiconductor field effect transistor chips.

[0015] In some embodiments, in the layout structure of the power semiconductor module provided by the present application, the upper bridge arm chip and the lower bridge arm chip are insulated gate bipolar transistor chips.

[0016] In some embodiments, in the layout structure of the power semiconductor module provided in the present application, a thermistor is further disposed on the substrate for detecting the temperature of the power semiconductor module.

[0017] In some embodiments, in the layout structure of the power semiconductor module provided by the present application, the substrate is a direct copper bonding structure or an advanced multi-layer bonding structure.

[0018] In a second aspect, the present application provides a power semiconductor module, comprising at least one layout structure of a power semiconductor module as described in any one of the first aspects above.

[0019] The present application provides a layout structure of a power semiconductor module and a power semiconductor module. In the layout structure of the power semiconductor module, the negative power terminal, the lower bridge arm chip, the upper bridge arm chip and the AC power terminal are arranged in sequence along the first direction of the substrate, and each negative power terminal is arranged along the second direction of the substrate and is respectively arranged on each first metal layer of the substrate, each lower bridge arm chip is arranged along the second direction of the substrate and is respectively arranged on each second metal layer of the substrate, each upper bridge arm chip is arranged along the second direction of the substrate and is arranged on the fourth metal layer of the substrate, each AC power terminal is arranged along the second direction of the substrate and is respectively arranged on each third metal layer of the substrate; the positive power terminal and each upper bridge arm chip are arranged in sequence along the second direction of the substrate and are arranged on the fourth metal layer of the substrate. The layout structure of the power semiconductor module provided by the present application sets the negative power terminal close to the lower bridge arm chip, the AC power terminal close to the upper bridge arm chip, and the positive power terminal and the upper bridge arm chip on the same metal layer, so that the AC power terminal and the lower bridge arm chip are distributed on both sides of the upper bridge arm chip. Based on the layout structure of the power semiconductor module, it is possible to make the current flow from the positive power terminal to the upper bridge arm chip, and the current flows from one side of the upper bridge arm chip to the lower bridge arm chip while the other side flows to the AC power terminal. And based on the layout structure of the power semiconductor module, more signal terminals can be added to the empty positions between the negative power terminals and the AC power terminals, which greatly improves the space utilization of the power semiconductor module.

[0020] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of a conventional power semiconductor module is shown.

[0023] Figure 2 A schematic diagram showing the layout structure of a power semiconductor module provided in an embodiment of the present application is shown.

[0024] Figure 3 Another schematic diagram showing the layout structure of the power semiconductor module provided in an embodiment of the present application.

[0025] Figure 4 A schematic diagram of a lower bridge arm chip and an upper bridge arm chip connected in a half-bridge manner is shown.

[0026] Figure 5 A schematic diagram of a lower bridge arm chip and an upper bridge arm chip connected in a full-bridge manner is shown.

[0027] Figure 6 Another schematic diagram showing the layout structure of the power semiconductor module provided in an embodiment of the present application.

[0028] Figure 7 A schematic diagram of a power semiconductor module provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0030] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0031] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0032] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0033] Figure 1 A schematic diagram of a conventional power semiconductor module is shown in FIG. Figure 1As shown, in the design of traditional power semiconductor modules, such as insulated gate bipolar transistors (IGBTs) or full silicon carbide (SiC) power semiconductor modules, the AC power terminal AC usually shares the same metal layer with the lower bridge arm chip to realize current flow. Obviously, this design method reserves fewer layout positions for signal terminals, which in turn limits the layout flexibility of the terminals and the current outflow path of the terminals, thereby affecting the overall heat dissipation performance and electrical characteristics of the power semiconductor module. In addition, this layout method also leads to inflexible outflow positions of terminal currents, which makes it difficult for traditional power semiconductor modules to add KS (Kelvin-Source: Kelvin source) signal terminals for improving current accuracy, limiting the improvement of the overall efficiency of the power module, especially in the face of miniaturized packaging. The internal layout space of the traditional power semiconductor module is further compressed, making its internal space utilization rate even lower. Therefore, how to break through these limitations through innovative internal layout design without sacrificing reliability has become one of the key issues that need to be solved in the current development of the power semiconductor industry.

[0034] In view of the above problems, an embodiment of the present application provides a layout structure of a power semiconductor module. Figure 2 A schematic diagram showing the layout structure of a power semiconductor module provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the layout structure of the power semiconductor module provided in the embodiment of the present application includes a substrate 110, at least one pair of lower bridge arm chips 210 and upper bridge arm chips 220, the same number of negative power terminals (i.e., DC-) 310 as the lower bridge arm chips 210, the same number of alternating current power terminals (AC) 410 as the lower bridge arm chips 210, and one positive power terminal (i.e., DC+) 320.

[0035] like Figure 2 As shown, the substrate 110 is provided with the same number of first metal layers C1 , second metal layers C2 , third metal layers C3 and a fourth metal layer C4 as the number of the lower bridge arm chips 210 . Among them, the negative power terminal 310, the lower bridge arm chip 210, the upper bridge arm chip 220 and the AC power terminal 410 are arranged in sequence along the first direction (y direction) of the substrate 110, and each negative power terminal 310 is arranged along the second direction (x direction) of the substrate 110, and is respectively arranged on each first metal layer C1, each lower bridge arm chip 210 is arranged along the second direction (x direction) of the substrate 110, and is respectively arranged on each second metal layer C2, each upper bridge arm chip 220 is arranged along the second direction (x direction) of the substrate 110, and is arranged on the fourth metal layer C4, each AC power terminal 410 is arranged along the second direction (x direction) of the substrate 110, and is respectively arranged on each third metal layer C3, the positive power terminal 320 and each upper bridge arm chip 220 are arranged in sequence along the second direction (x direction) of the substrate 110, and are arranged on the fourth metal layer C4.

[0036] The layout structure of the power semiconductor module provided in the embodiment of the present application sets the negative power terminal close to the lower bridge arm chip, the AC power terminal close to the upper bridge arm chip, and the positive power terminal and the upper bridge arm chip are set on the same metal layer, so that the AC power terminal and the lower bridge arm chip are distributed on both sides of the upper bridge arm chip. Based on the layout structure of the power semiconductor module, it is possible to achieve that the current flows from the positive power terminal to the upper bridge arm chip, and one side of the upper bridge arm chip flows to the lower bridge arm chip while the other side flows to the AC power terminal. And based on the layout structure of the power semiconductor module, more signal terminals can be added to the vacant positions between the negative power terminals and the AC power terminals according to the packaging characteristics of different packages, which greatly improves the space utilization of the power semiconductor module.

[0037] Compared with traditional power semiconductor modules, the embodiment of the present application has a higher space utilization rate under the same volume, so a higher power density can be achieved, and it is compatible with miniaturized packaging and high power density.

[0038] In some embodiments, in the layout structure of the power semiconductor module provided in the embodiment of the present application, the positive power terminal is configured to receive current and transmit the current to each upper bridge arm chip, the upper bridge arm chip is configured to transmit the current to the corresponding lower bridge arm chip and the corresponding AC power terminal respectively, and the lower bridge arm chip is configured to transmit the current to the corresponding negative power terminal. Optionally, based on the layout structure of the power semiconductor module provided in the embodiment of the present application, the outflow direction of the current can be set to the positive power terminal, the upper bridge arm chip, the AC power terminal and the lower bridge arm chip, and the outflow position of the current of each terminal is flexible, thereby improving the space utilization of the layout structure.

[0039] In some embodiments, in the layout structure of the power semiconductor module provided in the embodiments of the present application, at least one pair of lower bridge arm chips and upper bridge arm chips are configured to be connected in a half-bridge manner to serve as the layout structure of a half-bridge power semiconductor module, or are configured to be connected in a full-bridge manner to serve as the layout structure of a three-phase full-bridge power semiconductor module.

[0040] In some embodiments, Figure 3 Another schematic diagram showing the layout structure of the power semiconductor module provided by the embodiment of the present application is shown in FIG. Figure 3 As shown, in the layout structure of the power semiconductor module provided in the embodiment of the present application, at least one signal terminal metal layer C5 is further provided on the substrate 110 , and each signal terminal metal layer C5 is used to provide a signal terminal 500 .

[0041] Each of the signal terminal metal layers C5 is arranged in parallel with the first metal layer C1 along the second direction (x direction) of the substrate 110 , and is arranged in parallel with each of the third metal layers C3 along the second direction (x direction) of the substrate 110 .

[0042] It can be understood that in the layout structure of the power semiconductor module, the layout position of the signal terminal is determined by the package type. The layout structure of the power semiconductor module provided in the embodiment of the present application aims to provide a layout structure including a negative power terminal, a positive power terminal, an AC power terminal, a lower bridge arm chip and an upper bridge arm chip, so as to improve the layout space utilization of the power semiconductor module through the layout structure, thereby adding more signal terminals. Therefore, the position of the signal terminal can be any idle position of the layout structure, and the specific position of the signal terminal should be determined by the package type, and the embodiment of the present application does not limit this.

[0043] In some embodiments, in the layout structure of the power semiconductor module provided by the embodiments of the present application, each signal terminal 500 includes at least a Kelvin-Source signal terminal (Ks signal terminal).

[0044] Compared with the problem of low space utilization of traditional power semiconductor modules due to the limitation of the current outflow position of the terminals, the layout structure of the power semiconductor module provided by the present application significantly improves the layout space utilization of the power semiconductor module. Based on this utilization, the layout structure of the power semiconductor module can also set additional Kelvin source signal terminals to improve the performance of the power semiconductor.

[0045] In some embodiments, in the layout structure of the power semiconductor module provided by the embodiments of the present application, the upper bridge arm chip and the lower bridge arm chip are silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) chips.

[0046] In some embodiments, in the layout structure of the power semiconductor module provided in the embodiments of the present application, the upper bridge arm chip and the lower bridge arm chip are insulated gate bipolar transistor (IGBT) chips.

[0047] In some embodiments, Figure 4 A schematic diagram of a lower bridge arm chip and an upper bridge arm chip connected in a half-bridge manner is shown, such as Figure 4As shown, in the layout structure of the power semiconductor module provided in the embodiment of the present application, the lower bridge arm chip and the upper bridge arm chip are (SiC MOSFET) chips or IGBT chips, the drain of the lower bridge arm chip is connected to the positive power terminal DC+, the source is connected to the drain of the upper bridge arm chip and the AC power terminal AC, and the source of the upper bridge arm chip is connected to the negative power terminal DC-, wherein G1 and G2 respectively represent the gates of the lower bridge arm chip and the upper bridge arm chip, and S1 and S2 respectively represent the sources of the lower bridge arm chip and the upper bridge arm chip.

[0048] In some embodiments, Figure 5 FIG. 1 shows a schematic diagram of a lower bridge arm chip and an upper bridge arm chip connected in a full-bridge manner, such as Figure 5 As shown, in the layout structure of the power semiconductor module provided in the embodiment of the present application, the lower bridge arm chip and the upper bridge arm chip are (SiC MOSFET) chips or IGBT chips, and the layout structure includes three pairs of lower bridge arm chips and upper bridge arm chips connected in parallel.

[0049] It is understandable that Figure 5 The parallel connection mode of the three pairs of lower bridge arm chips and upper bridge arm chips is not shown, because the embodiment of the present application does not limit the specific circuit structure of the full-bridge structure.

[0050] In some embodiments, Figure 6 Another schematic diagram showing the layout structure of the power semiconductor module provided in the embodiment of the present application is shown in FIG. Figure 6 As shown, in the layout structure of the power semiconductor module provided in the embodiment of the present application, a thermistor 600 is further disposed on the substrate 110 for detecting the temperature of the power semiconductor module.

[0051] In some embodiments, in the layout structure of the power semiconductor module provided in the embodiments of the present application, the substrate is a direct copper bonding (Direct Copper Bonding) structure. Optionally, the direct copper bonding substrate structure includes two upper and lower metal layers and a middle layer of aluminum oxide. The metal layer is used to provide excellent electrical conductivity, while the aluminum oxide layer has good thermal conductivity and chemical stability. The upper surface metal layer of the direct copper bonding substrate includes the first to fifth metal layers.

[0052] In some embodiments, in the layout structure of the power semiconductor module provided in the embodiments of the present application, the substrate is an Advanced Multi-layer Bonding structure, and optionally, the Advanced Multi-layer Bonding (AMB) substrate includes two upper and lower metal layers and a middle layer of silicon nitride. The metal layer is used to provide excellent electrical conductivity, while the silicon nitride layer has good thermal conductivity, chemical stability and mechanical strength, wherein the upper surface metal layer of the Advanced Multi-layer Bonding (AMB) substrate includes the first to fifth metal layers.

[0053] It can be understood that the layout structure of the power semiconductor module provided in the embodiment of the present application aims to provide a layout structure including a negative power terminal, a positive power terminal, an AC power terminal, a lower bridge arm chip and an upper bridge arm chip, so as to improve the layout space utilization of the power semiconductor module through the layout structure, thereby adding more signal terminals. There is no restriction on the structure of the substrate here, that is, the substrate is not limited to the direct copper bonding (Direct Copper Bonding) structure and the advanced multi-layer bonding (Advanced Multi-layer Bonding) structure described in the above embodiments.

[0054] In some embodiments, in the layout structure of the power semiconductor module provided by the embodiments of the present application, the metal material of the first to fifth metal layers is preferably metal copper.

[0055] Based on the layout structure of the power semiconductor module provided in the above-mentioned embodiment, the embodiment of the present application further provides a power semiconductor module. The power semiconductor module provided in the embodiment of the present application includes a layout structure of at least one power semiconductor module to achieve different functions through the layout structure of each power semiconductor module.

[0056] In some embodiments, Figure 7 A schematic diagram of a power semiconductor module provided in an embodiment of the present application is shown, Figure 7 As shown, the power semiconductor module includes a layout structure of two three-phase full-bridge power semiconductor modules, so as to realize the rectification function and the motor driving function respectively by setting the layout structure of the two three-phase full-bridge power semiconductor modules. In the layout structure of the two three-phase full-bridge power semiconductor modules, the negative power terminal 310, the lower bridge arm chip 210, the upper bridge arm chip 220, and the AC power terminal 410 are arranged in sequence along the first direction (y direction) of the substrate, and the positive power terminal 510 and each upper bridge arm chip 220 are arranged in sequence along the second direction (x direction) of the substrate, and are located on the same metal layer, and the metal layer where each signal terminal 500 is located is arranged in parallel with the metal layer where the negative power terminal 310 is located along the second direction (x direction) of the substrate, and is arranged in parallel with the metal layer where each AC power terminal 410 is located along the second direction (x direction) of the substrate. Optionally, as Figure 7 As shown, each signal terminal 500 includes at least a Kelvin source signal terminal 510 .

[0057] The power semiconductor module provided in the embodiment of the present application sets the negative power terminal close to the lower bridge arm chip, the AC power terminal close to the upper bridge arm chip, and the positive power terminal and the upper bridge arm chip on the same metal layer, so that the AC power terminal and the lower bridge arm chip are distributed on both sides of the upper bridge arm chip. Based on the layout structure of the power semiconductor module, it is possible to make the current flow from the positive power terminal to the upper bridge arm chip, and the upper bridge arm chip flows from one side to the lower bridge arm chip while the other side flows to the AC power terminal. Furthermore, based on the layout structure of the power semiconductor module, more signal terminals can be added to the vacant positions between the negative power terminals and the AC power terminals according to the packaging characteristics, which greatly improves the space utilization of the power semiconductor module.

[0058] Compared with traditional power semiconductor modules, the embodiment of the present application has a higher space utilization rate under the same volume, so a higher power density can be achieved, and it is compatible with miniaturized packaging and high power density.

[0059] The above contents are further detailed descriptions of the present application in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be regarded as the protection scope of the present application.

Claims

1. A layout structure of a power semiconductor module, characterized in that: include: A substrate, at least one pair of lower bridge arm chips and upper bridge arm chips, the same number of negative power terminals as the lower bridge arm chips, the same number of AC power terminals as the lower bridge arm chips, and one positive power terminal; The substrate is provided with a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the number of which is the same as the number of the lower bridge arm chips; The negative power terminal, the lower bridge arm chip, the upper bridge arm chip and the AC power terminal are sequentially arranged along the first direction of the substrate, and each of the negative power terminals is arranged along the second direction of the substrate and is respectively arranged on each of the first metal layers, each of the lower bridge arm chips is arranged along the second direction of the substrate and is respectively arranged on each of the second metal layers, each of the upper bridge arm chips is arranged along the second direction of the substrate and is arranged on the fourth metal layer, and each of the AC power terminals is arranged along the second direction of the substrate and is respectively arranged on each of the third metal layers; The positive power terminal and each of the upper bridge arm chips are arranged in sequence along the second direction of the substrate and are disposed on the fourth metal layer.

2. The layout structure of the power semiconductor module according to claim 1, characterized in that: The positive power terminal is configured to receive current and transmit the current to each of the upper bridge arm chips. The upper bridge arm chips are configured to transmit current to the corresponding lower bridge arm chips and the corresponding AC power terminals respectively. The lower bridge arm chips are configured to transmit current to the corresponding negative power terminals.

3. The layout structure of the power semiconductor module according to claim 1, characterized in that: The at least one pair of lower bridge arm chips and upper bridge arm chips are configured to be connected in a half-bridge manner, or configured to be connected in a full-bridge manner.

4. The layout structure of the power semiconductor module according to claim 1, characterized in that: At least one signal terminal metal layer is also provided on the substrate, and each signal terminal metal layer is used to provide a signal terminal; Each of the signal terminal metal layers is arranged in parallel with the first metal layer along the second direction of the substrate, and is arranged in parallel with each of the third metal layers along the second direction of the substrate.

5. The layout structure of the power semiconductor module according to claim 3, characterized in that: The signal terminals at least include a Kelvin source signal terminal.

6. The layout structure of the power semiconductor module according to claim 1, characterized in that: The upper bridge arm chip and the lower bridge arm chip are silicon carbide metal oxide semiconductor field effect transistor chips.

7. The layout structure of the power semiconductor module according to claim 1, characterized in that: The upper bridge arm chip and the lower bridge arm chip are insulated gate bipolar transistor chips.

8. The layout structure of the power semiconductor module according to claim 1, characterized in that: The substrate is also provided with a thermistor for detecting the temperature of the power semiconductor module.

9. The layout structure of the power semiconductor module according to claim 1, characterized in that: The substrate is a direct copper bonding structure or an advanced multi-layer bonding structure.

10. A power semiconductor module, characterized in that: A layout structure comprising at least one power semiconductor module as claimed in any one of claims 1 to 9.

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