Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a semiconductor layer and a device structure at least located on the semiconductor layer. The device structure comprises a contact structure located on the semiconductor layer; the first connecting structure is located on one side, close to the semiconductor layer, of the contact structure and penetrates through the semiconductor layer; the first connecting structure is coupled with the contact structure; wherein the first connecting structure at least comprises a first sub-connecting structure and a second sub-connecting structure, the first sub-connecting structure and the second sub-connecting structure extend in the thickness direction, and a gap is formed between the first sub-connecting structure and the second sub-connecting structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A three-dimensional integrated circuit can be formed by stacking semiconductor chips, and the semiconductor chip has an electronic circuit system formed therein or thereon. These stacked semiconductor chips can be interconnected vertically. The stacked semiconductor chips can be interconnected using through silicon vias (TSV) to form a circuit structure with electrical functions. For example, multiple memory chips, logic chips, or communication chips can be stacked, and multiple memory chips can be interconnected using through silicon vias to obtain high-bandwidth and high-computing power integrated circuits or electronic systems, shortening the length of interconnections between chips to improve performance. With the improvement of the integration of semiconductor chips, the integration of through silicon vias is also getting higher and higher, and there is still a lot of room for improvement in the chip stacking process. Summary of the invention

[0003] According to some aspects of the embodiments of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor layer, and a device structure at least located on the semiconductor layer; the device structure comprises a contact structure located on the semiconductor layer; a first connection structure, located on a side of the contact structure close to the semiconductor layer and penetrating the semiconductor layer; the first connection structure is coupled to the contact structure; wherein the first connection structure comprises at least a first sub-connection structure and a second sub-connection structure extending in a thickness direction, and a gap is provided between the first sub-connection structure and the second sub-connection structure.

[0004] In some embodiments, the contact structure includes: a plurality of spaced-apart bumps, including at least a first bump and a second bump; the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

[0005] In some embodiments, the semiconductor structure further includes: a barrier layer located between the first connection structure and the semiconductor layer; the barrier layer surrounds a sidewall of the first connection structure extending along the thickness direction.

[0006] In some embodiments, the first sub-connection structure is in partial contact with the second sub-connection structure.

[0007] In some embodiments, the semiconductor structure further includes: a contact located on a side of the first connection structure away from the contact structure; and the contact is coupled to the first connection structure.

[0008] In some embodiments, the size of the contact in the first direction is greater than the size of the first connection structure in the first direction; the contact is coupled to at least part of the sub-connection structure in the first connection structure; and the first direction intersects with the thickness direction.

[0009] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a semiconductor layer, and forming a device structure at least on the semiconductor layer; the device structure includes a contact structure located on the semiconductor layer; the contact structure includes a plurality of bumps arranged at intervals, including at least a first bump and a second bump; etching a side of the semiconductor layer away from the contact structure to form a first opening that penetrates the semiconductor layer; the first opening exposes the contact structure; forming a first connection structure in the first opening, the first connection structure at least including a first sub-connection structure and a second sub-connection structure extending in a thickness direction, a gap being formed between the first sub-connection structure and the second sub-connection structure; wherein the first sub-connection structure is in contact with the first bump, and the second sub-connection structure is in contact with the second bump.

[0010] In some embodiments, the manufacturing method further includes: before forming the first opening, thinning a side of the semiconductor layer away from the device structure.

[0011] In some embodiments, the manufacturing method includes performing an electroplating process using at least the first bump and the second bump as a seed layer to form the first sub-connection structure and the second sub-connection structure in the first opening.

[0012] In some embodiments, the manufacturing method further includes: forming a barrier layer between the first connection structure and the semiconductor layer, wherein the barrier layer surrounds a side wall of the first connection structure extending along the thickness direction.

[0013] In some embodiments, the device structure includes a conductive structure, and the first connecting structure is coupled to the conductive structure through the contact structure; the method of forming the contact structure includes: attaching an insulating film having a plurality of second openings on the conductive structure; the plurality of second openings expose the conductive structure; forming a first dielectric layer covering the insulating film; forming a third opening penetrating the first dielectric layer at a position of the first dielectric layer corresponding to the conductive structure; the third opening exposes the plurality of second openings, and the third opening exposes the conductive structure through the plurality of second openings; forming a plurality of the bumps in the plurality of the second openings that expose the conductive structure, and the plurality of the bumps constitute the contact structure.

[0014] In some embodiments, the manufacturing method further includes: forming a contact on a side of the first connecting structure away from the contact structure, wherein the contact is coupled to the first connecting structure.

[0015] An embodiment of the present disclosure provides a semiconductor structure, including: a semiconductor layer, and a device structure at least located on the semiconductor layer, the device structure including a contact structure located above the semiconductor layer; a first connection structure coupled to the contact structure, located on a side of the contact structure close to the semiconductor layer, and the first connection structure penetrates the semiconductor layer along the thickness direction, the first connection structure includes a plurality of sub-connection structures extending along the thickness direction such as at least a first sub-connection structure and a second sub-connection structure, and a gap is provided between the first sub-connection structure and the second sub-connection structure; compared with a solid, integral connection structure, the gap between each sub-connection structure is conducive to dispersing stress, reducing stress concentration caused by thermal strain, and reducing deformation of the connection structure or structural rupture caused by differences in thermal expansion coefficients between the connection structure and other materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 4 is a schematic diagram of manufacturing a semiconductor structure according to an exemplary embodiment;

[0017] Figures 5 to 8 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0018] Fig. 9 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0019] Figures 10 to 19 It is a schematic diagram of semiconductor structure manufacturing according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0021] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0022] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] It should be understood that the "some embodiments" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0025] In some embodiments, for some connection structures, including but not limited to TSV, conductive plugs, and conductive channels, they can extend along the thickness direction of the wafer or device, such as the z direction in the attached figure; they can be used to conduct electrical or signal interconnection for semiconductor structures, devices, and chips. The z direction can be a third direction, and the x direction and the y direction are directions that intersect and are perpendicular to the z direction. The x direction and the y direction can be recorded as the first direction and the second direction respectively; the x and y directions intersect or are perpendicular, and the plane formed by the x and y directions intersects and is perpendicular to the z direction.

[0026] In some embodiments, some methods for making the connection structure 104 are described by way of example; Figure 1 As shown, the semiconductor layer 100 or the dielectric layer is etched to form an opening 101 that penetrates a portion of the thickness of the semiconductor layer 100 or completely penetrates the semiconductor layer 100, and the opening 101 may extend along the z direction. The semiconductor layer 100 may be a semiconductor substrate or a film layer epitaxially grown on a semiconductor substrate; after the opening 101 only penetrates a portion of the thickness of the semiconductor layer 100, the semiconductor layer 100 may be back-thinned to expose the bottom of the opening 101 or the bottom of the connection structure in the opening 101, so that the opening 101 or the connection structure in the opening 101 penetrates the semiconductor layer 100. The etching process may include, but is not limited to, dry etching, wet etching, and combinations thereof.

[0027] Reference Figure 2 As shown, a barrier layer 102 is deposited on the sidewall and / or bottom of the opening 101. The material of the barrier layer 102 may include but is not limited to metal nitrides, including but not limited to titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride or a combination thereof. The deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0028] exist Figure 2 The opening 101 with the barrier layer 102 is filled with a conductive material to form a connection structure 104. A deposition process may be performed to form the connection structure 104. The materials of the connection structure 104 may include but are not limited to: copper, aluminum, tungsten, gold, silver, platinum, chromium, nickel, cobalt, titanium and other conductive materials. Figure 3 As shown, a seed layer 103 may be deposited in the opening 101 having the barrier layer 102, and the seed layer 103 may include but is not limited to copper; Figure 4 As shown, a connection structure 104 is formed in the opening 101 with the seed layer 103 by deposition or electroplating process, and the connection structure 104 includes copper. A portion of the conductive material covering the semiconductor layer can be removed by chemical mechanical polishing, and the connection structure 104 in the opening 101 is retained.

[0029] In some embodiments, a dielectric layer may be formed between the barrier layer 102 and the semiconductor layer 100, such as silicon oxide formed by atomic layer deposition or chemical deposition, such as thermal silicon oxide (high-temperature silicon oxide) formed by thermal oxidation; the thermal expansion coefficients of the conductive material in the connection structure 104, the barrier layer 102, and the dielectric layer are different. For example, the connection structure 104-barrier layer 102-dielectric layer is copper-tantalum nitride-silicon oxide. When subjected to high temperature, the expansion degree of copper is greater than that of tantalum nitride and silicon oxide. The copper expands to a greater length in the z direction, which makes the length of the copper layer in the z direction greater than that of tantalum nitride and silicon oxide, resulting in peeling between the copper layer and the tantalum nitride and silicon oxide, and delamination and cracking of the connection structure 104 and the barrier layer 102; in the x direction or other horizontal directions, because copper has a larger thermal expansion coefficient, the copper layer expands laterally, causing an increase in horizontal stress, resulting in bending and cracking of the product. In some embodiments, the front-end, middle-end and back-end processes in the semiconductor manufacturing process may have a larger process temperature range. For example, the front-end process may mainly involve the manufacture of transistors and device structures, and the temperature treatment may include a high temperature of 1000°C. The middle-end and back-end processes may include the manufacture of metal contacts, metal connections and metal wiring, and the temperature treatment may include 400-500°C to prevent the metal from melting or deforming. In some embodiments, in order to facilitate process integration and reduce manufacturing costs, connection structures such as TSV can be manufactured at various process stages, with a larger temperature range. Reducing the thermal strain deformation of the connection structure is conducive to improving the manufacturing yield and device stability.

[0030] According to some aspects of the embodiments of the present disclosure, Figure 5A semiconductor structure 20 is provided, comprising: a semiconductor layer 200, and a device structure at least located on the semiconductor layer; the device structure comprises a contact structure 210 located on the semiconductor layer 200; a first connection structure 220, located on a side of the contact structure 210 close to the semiconductor layer 200 and penetrating the semiconductor layer 200; the first connection structure 220 is coupled to the contact structure 210; wherein the first connection structure 220 comprises at least a first sub-connection structure 221a and a second sub-connection structure 221b extending in a thickness direction (z direction), and a gap 222 is provided between the first sub-connection structure 221a and the second sub-connection structure 221b. The first sub-connection structure 221a and the second sub-connection structure 221b may be adjacent or not adjacent.

[0031] Figure 5 The lower surface of the semiconductor layer 200 can be the front or back of the wafer or substrate, such as the back; the semiconductor layer 200 can be a film layer after back thinning, and various device structures can be formed on or in the semiconductor layer 200. Figure 5 Only some examples of device structures are shown, which may include but are not limited to logic control circuits composed of various transistors, volatile or non-volatile storage structures, including but not limited to NAND flash memory, dynamic random access memory unit DRAM, including but not limited to radio frequency circuits, including but not limited to various wiring layers, conductive plugs, etc. For example, there is a dielectric material on the front side of the semiconductor layer 200, and the dielectric material has a device structure and an interconnection layer; or, part of the device structure may be arranged in the semiconductor layer 200, such as the source, drain and channel of the transistor. The semiconductor structure 20 may include a plurality of interconnection layers, and the interconnection layers are coupled to each device structure to provide power supply or control signal, data interaction, and the contact structure 210 may be directly in contact with the interconnection layer or coupled through other conductive structures to lead out the electrical signal of the interconnection layer. The first connection structure 220 penetrates the semiconductor layer 200 and other dielectric materials. The first connection structure 220 is coupled to the contact structure 210 to lead out the electrical signal of the semiconductor structure 20, and the semiconductor structure 20 may be powered or signal interacted through the first connection structure 220.

[0032] The contact structure 210 can be directly contacted and coupled with the first connection structure 220, or connected through other conductive structures, including but not limited to a connection layer, a transition layer, including but not limited to metal silicide, metal nitride, or a low-resistance material with a resistance lower than that of the first connection structure 220, so as to increase the adhesion between the contact structure 210 and the first connection structure 220 to reduce the contact resistance.

[0033] In some embodiments, the device structure may include an electrode layer 231 partially located in the semiconductor layer 200 and stacked in the z direction, wherein a portion of the electrode layer 231 extends into the semiconductor layer 200 and a portion covers the semiconductor layer 200 and extends on the semiconductor layer 200; adjacent electrode layers 231 are separated by dielectric material to form a capacitor structure, or a multi-polar capacitor structure, and the capacitor structure can be configured as a decoupling capacitor, a resonant capacitor, or a storage capacitor.

[0034] In some embodiments, Figure 5 A partially enlarged schematic diagram of the first connection structure 220 is also shown. The first connection structure 220 has a gap 222 inside, which can provide a buffer space when heated, reduce deformation and film peeling; when the stress in the x direction or z direction is generated by heat, the first connection structure 220 deforms inward along the x direction to disperse the stress, and reduce the film rupture caused by stress concentration. The first connection structure 220 may include at least a first sub-connection structure 221a and a second sub-connection structure 221b extending in the z direction, and there may be a gap 222 between the first sub-connection structure 221a and the second sub-connection structure 221b. The first sub-connection structure 221a and the second sub-connection structure 221b may be partially in contact, and the uncontacted part forms the gap 222. There is no restriction on the size and shape of the gap 222. For example, the first sub-connection structure 221a and the second sub-connection structure 221b may be linear structures, the gap 222 is a linear gap structure, and the size of the first sub-connection structure 221a in the x or y direction is nanometer-level, such as 0-10 nanometers.

[0035] In some embodiments, the contact structure 210 includes: a plurality of spaced bumps 211, including at least a first bump 211a and a second bump 211b; a first sub-connection structure 221a in contact with the first bump 211a, and a second sub-connection structure 221b in contact with the second bump 211b.

[0036] The semiconductor structure 20 may include a conductive structure, which is a wiring layer or other lead structure for coupling with devices such as transistors and capacitors, and the contact structure 210 is coupled to the conductive structure for electrical signal interconnection; Figure 5In the figure, the contact structure 210 may be located between the conductive structure and the first connection structure 220 in the z direction, and the specific structure of the conductive structure is not shown. The contact structure 210 may have a plurality of convex points 211 arranged at intervals, and the plurality of convex points 211 are used to draw electricity to the conductive structure. Compared with the integral, solid contact structure, the filling amount of conductive materials such as copper can be reduced, and the stress concentration caused by the thermal strain of copper can be reduced to reduce the structural deformation and damage caused by the stress concentration; for example, when the thermal strain is deformed in the x direction, there is a buffer and deformation space between the convex points 211 arranged at intervals, which reduces the deformation of the overall contact structure 210; in the thermal strain deformation in the z direction, the convex points 211 do not affect each other, which reduces the stress concentration in the z direction to reduce the delamination and rupture of the film layer.

[0037] In some embodiments, a dielectric material is formed, and the dielectric material is etched to form a plurality of through holes penetrating the dielectric material, and the through holes reveal the conductive structure; a conductive material is filled in the through holes to form a bump 211, and the bump 211 is coupled to the conductive structure; no through holes may be formed in the area where the dielectric material is not aligned with or does not correspond to the first connection structure 220; when the arrangement density of the through holes is increasing and the size of the through holes is decreasing to improve the conductive performance of the contact structure 210, the difficulty of etching the openings is increasing. In some other embodiments, the semiconductor structure 20 further includes an insulating film 212 covering the conductive structure, and the insulating film 212 has a plurality of through holes, as described below. Fig.15 The second opening 22 and the insulating film 212 shown in the example may be attached to the dielectric layer having the conductive structure, and the attachment method may include but is not limited to hot pressing or gluing; some second openings 22 correspond to the conductive structure in the z direction, and other second openings 22 that do not correspond to the conductive structure may also be provided; the second openings 22 of the insulating film 212 may be nanometer-level, and the insulating film 212 is used as a template for the formation of the bumps 211, and the bumps 211 are arranged in a plurality of second openings 22 corresponding to the conductive structure, and the plurality of bumps 211 are arranged at intervals to form a contact structure 210 coupled to the conductive structure. The insulating film 212 may include a polymer material, such as polycarbonate or polyurethane, and the pore size is 0 to 10 nanometers.

[0038] In some embodiments, a dielectric layer covering the insulating film 212 may be provided, as described below. Fig.16The first dielectric layer 242 shown in the example is located between the insulating film 212 and the first connecting structure 220; the first dielectric layer 242 has a third opening 23, the aperture of the third opening 23 is larger than the aperture of the first opening 21, the third opening 23 is aligned with the conductive structure in the z direction and exposes multiple second openings 22 of the insulating film 212, the first dielectric layer 242 removes part of the third opening 23 that blocks or fills the second openings 22 in the insulating film 212 that do not correspond to the conductive structure, so that the third opening 23 can be used to form a bump 211 in the second opening 22 to couple with the conductive structure, and the second opening 22 that does not correspond to the conductive structure may not form the bump 211, which can reduce leakage and interference, and can also reduce the etching pressure when forming the second opening 22 to expand the manufacturing process window.

[0039] The distribution of the bumps 211 on the insulating film 212 can be as follows: Figure 6 As shown, a plurality of bumps 211 may constitute a bump array, a plurality of bumps 211 are coupled to a conductive structure, and a contact structure 210 formed by a plurality of bumps 211 is coupled to a first connection structure 220. The cross-sectional outer contour shape of the contact structure 210 in the xoy plane may include but is not limited to a circle, an ellipse or other regular or irregular arcs; may include a rectangle, a triangle or other regular or irregular polygons; may also include other figures composed of arcs and straight lines; the cross-sectional figure of the first connection structure 220 in the xoy plane may refer to the contact structure 210 and will not be described in detail. The bump 211 may be a column extending along the z direction, and there is no restriction on the cross-sectional shape of the bump 211 in the xoy plane, and there is no restriction on the arrangement and number of the bumps 211, and may include but is not limited to Figure 5 The contact structures 210 (or the predetermined positions of the contact structures 210) are arranged in a circle around the center of the circle. Figure 5 As shown, the top of the first connection structure 220 may be coupled to at least a portion of the bump 211 , such as may be fully coupled to increase the conductive performance.

[0040] In some embodiments, reference Figure 5 The illustrated first bump 211a, the second bump 211b, the first sub-connection structure 221a contacting the first bump 211a, and the second sub-connection structure 221b contacting the second bump 211b, the bump 211 and the sub-connection structure have nanometer-scale dimensions in the x or y direction, such as 0-10 nanometers.

[0041] In some embodiments, an opening may be formed through the back surface of the semiconductor layer 200 and expose the contact structure 210, such as Fig.11The first opening 21 in the example can be electroplated with the bump 211 in the contact structure 210 as a seed layer to form a first connection structure 220 in the first opening 21; the electroplating process parameters, including the concentration of the electroplating solution, the electroplating time, and the electroplating voltage / current, are adjusted to guide the formation of a gap 222 inside the first connection structure 220. The first connection structure 220 has a linear or columnar structure extending along the z direction, such as a nanowire nanocolumnar structure. For example, taking the first sub-connection structure 221a and the second sub-connection structure 221b as examples, there is a gap 222 between the first sub-connection structure 221a and the second sub-connection structure 221b, and the first sub-connection structure 221a and the second sub-connection structure 221b may not be in contact or may be in contact in some areas to form the gap 222. The first sub-connection structure 221a can be formed by electroplating growth or electroplating deposition of the seed layer of the first bump 211a, and the first sub-connection structure 221a is coupled to the first bump 211a; the second sub-connection structure 221b can be formed by electroplating growth or electroplating deposition of the seed layer of the second bump 211b, and the second sub-connection structure 221b is coupled to the second bump 211b. The disclosed embodiment does not limit the number of sub-connection structures, the number of bumps 211, and the specific shape of the gap 222; the sub-connection structure and the bump 211 are made of the same material, the bump 211 can be formed by physical deposition, chemical deposition or electroplating, and the sub-connection structure is formed by an electroplating process; there may be no obvious physical boundary between the sub-connection structure and the bump 211.

[0042] In some embodiments, the first sub-connection structure 221 a is partially in contact with the second sub-connection structure 221 b . Figure 5 The schematic diagram of the sub-connection structure in the figure is an ideal schematic diagram. In the specific embodiment, some sub-connection structures of the first connection structure 220 may be in contact in some areas to form gaps 222 of various shapes. The formation position of the gaps 222 may not be limited; some linear or columnar sub-connection structures are in contact without boundaries, but not all sub-connection structures are in contact, and some areas are gaps 222. In some embodiments, the first connection structure 220 is a conductive column extending in the z direction as a whole, and there is a gap 222 inside the conductive column. The gap 222 may be an irregular linear gap extending in the z direction or in a direction having an angle with the z direction. In some embodiments, the cross-section of the first connection structure 220 in the xoz plane is schematically shown as a multi-layer structure in the x direction, with gaps 222 between layers, and the layers may be partially in contact with each other, and the contact position may be close to the bump 211 in the z direction.

[0043] In some embodiments, taking the first sub-connection structure 221a as an example, when the first connection structure 220 is formed by the electroplating process, the first sub-connection structure 221a may include a plurality of linear structures extending or diverging away from the first connection structure 220 with the first bump 211a as the base point, and the plurality of linear structures extend away from the bump with the first bump 211a as the starting point and diverge in the x direction to form a gap 222, and the plurality of linear structures may be partially in contact. The gap 222 in the first connection structure 220 can provide a buffer space when heated, reduce deformation and film peeling; when the stress in the x direction or z direction is generated by heat, the first connection structure 220 deforms inwardly along the x direction to disperse the stress, and reduce the film rupture caused by stress concentration.

[0044] In some embodiments, reference Figure 7 As shown, the semiconductor structure 20 further includes: a barrier layer 241, located between the first connection structure 220 and the semiconductor layer 200; the barrier layer 241 surrounds the sidewall of the first connection structure 220 extending in the thickness direction. The constituent materials of the barrier layer 241 may include but are not limited to metal nitrides, may include but are not limited to: titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride or a combination thereof, and may also include silicon nitride, etc.; the barrier layer 241 may be a single-layer film layer or a multi-layer film layer, such as a composite film layer of tantalum nitride and silicon nitride, or tantalum nitride and silicon oxide. The barrier layer 241 can be used to prevent the metal elements in the first connection structure 220 from diffusing into the dielectric layer and the semiconductor layer 200 to reduce leakage. The barrier layer 241 may also include a photoresist, specifically a cured photoresist, which may have a certain elasticity, and may provide a certain deformation buffer while improving the bonding force between the first connection structure 220 and the semiconductor layer 200 and reducing leakage, and may absorb the stress generated by thermal strain to reduce deformation and cracking. The photoresist may also facilitate the use of a photolithography process to remove the non-retained portion, and retain the portion as the barrier layer 241, so as to facilitate the control of the thickness of the barrier layer 241 and to facilitate the expansion of the manufacturing process window. For example, the barrier layer 241 may be a multi-layer structure to optimize electrical isolation and reduce stress concentration performance, such as a multi-layer structure of tantalum nitride and photoresist.

[0045] In some embodiments, reference Figure 8As shown, the semiconductor structure 20 further includes: a contact 251, which is located on a side of the first connection structure 220 away from the contact structure 210; the contact 251 is coupled to the first connection structure 220. The contact 251 can be used as a contact pad, a contact bump, or a bonding pad, and is used to connect to an external integrated circuit for power supply, control signal interaction, or data transmission. Exemplarily, the contact 251 can be used as an IO pad; or as a bonding pad for bonding with other semiconductor structures 20 for electrical signal interconnection, or as a contact point 251 adapted to adapt leads or conductive bumps (such as solder balls, conductive balls, etc.) to other semiconductor structures for electrical signal interconnection, or coupled to a packaging substrate or a silicon interposer.

[0046] In some embodiments, reference Figure 8 As shown, the size of the contact 251 in the x-direction (first direction) is larger than the size of the first connection structure 220 in the x-direction; the contact 251 is coupled to at least part of the sub-connection structures in the first connection structure 220; the x-direction intersects with the thickness direction. The first connection structure 220 may include a plurality of sub-connection structures, and the size of the first connection structure 220 in the x-direction is the size of the outer wall in the x-direction, not the size of a single sub-connection structure in the x-direction, specifically the size of the end of the first connection structure 220 that contacts the contact 251. The size of the end of the first connection structure 220 that contacts the contact 251 in the x-direction may be smaller than the size of the contact 251, so that more sub-connection structures or all sub-connection structures in the first connection structure 220 are coupled to the contact 251, thereby improving the connection stability.

[0047] According to some aspects of the embodiments of the present disclosure, Fig. 9 A method for manufacturing a semiconductor structure 20 is provided, comprising:

[0048] Providing a semiconductor layer, at least forming a device structure on the semiconductor layer; the device structure includes a contact structure located on the semiconductor layer; the contact structure includes a plurality of bumps arranged at intervals, including at least a first bump and a second bump;

[0049] Etching a side of the semiconductor layer away from the contact structure to form a first opening penetrating the semiconductor layer; the first opening exposes the contact structure;

[0050] A first connection structure is formed in the first opening, and the first connection structure at least includes a first sub-connection structure and a second sub-connection structure extending along the thickness direction, and a gap is formed between the first sub-connection structure and the second sub-connection structure; wherein the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

[0051] Reference Fig.10As shown, a semiconductor layer 200 is provided, or a semiconductor structure having a semiconductor layer 200 is provided, a device structure is formed in or on the semiconductor layer 200, and the semiconductor structure also has other device structures not shown, and the semiconductor structure may be an intermediate product of performing some manufacturing processes rather than a final product, and may be an intermediate state in a certain manufacturing step. The device structure may include a contact structure 210 located on the semiconductor layer 200, and the contact structure 210 may be coupled to a conductive structure such as a wiring layer and a conductive plug, or coupled to a structure such as a transistor and a capacitor. Fig.10 Also shown is an enlarged schematic cross-section of the contact structure 210 in the xoy plane. The contact structure 210 may include a plurality of bumps 211 arranged at intervals, including at least a first bump 211a and a second bump 211b; the plurality of bumps 211 may constitute a bump 211 array, with no restrictions on the arrangement and quantity, such as a circular or concentric circle arrangement.

[0052] Reference Fig.11 As shown, a carrier wafer can be used to support the semiconductor structure 20, and the semiconductor structure 20 can be turned over to expose the back side of the semiconductor layer 200. The back side of the semiconductor layer 200 is etched to form a first opening 21 that penetrates the semiconductor layer 200 and continues to extend to the dielectric layer under the semiconductor layer 200. The first opening 21 exposes the contact structure 210 under the semiconductor layer 200. The aperture of the first opening 21 is larger than the maximum size of the outer contour of the contact structure 210 to expose all the bumps 211 of the contact structure 210. Before etching the semiconductor layer 200 to open the hole, the back side of the semiconductor layer 200 can be thinned to reduce the etching amount. The thinning process may include, but is not limited to, etching, chemical mechanical polishing, or a combination thereof.

[0053] In some embodiments, the manufacturing method further includes: before forming the first opening 21, thinning the side of the semiconductor layer 200 away from the device structure. After thinning the side (back side) of the semiconductor layer 200 away from the device structure, a dielectric material may be formed on the back side of the semiconductor layer 200 to reduce oxidation of the semiconductor layer 200 and over-etching damage when etching the opening, and the dielectric material and the semiconductor layer 200 are etched to form the first opening 21. In some embodiments, due to the loading effect of etching, Fig.11 The size of the opening end of the first opening 21 in the x or y direction may be greater than or equal to the size of the bottom, so that the first connection structure 220 ( Fig.13 The size of the top (as shown) may be greater than or equal to the size of the bottom.

[0054] In some embodiments, the manufacturing method further includes: forming a first connection structure 220 and the semiconductor layer 200 between the first connection structure 220 and the semiconductor layer 200 Fig.12 The barrier layer 241 shown in the figure surrounds the sidewalls of the first connection structure 220 extending in the thickness direction. Fig.11 The barrier layer 241 is formed on the sidewall of the first opening 21 by atomic layer deposition, and the barrier layer 241 at the bottom of the first opening 21 is removed; or a dielectric layer may be formed on the first opening 21 first, and the sidewall of the first opening 21 may be directly oxidized to form an oxide layer, and then the barrier layer 241 is formed. The constituent materials of the barrier layer 241 may include but are not limited to metal nitrides, and may include but are not limited to: titanium nitride, tantalum nitride, chromium nitride, aluminum nitride, tungsten nitride or a combination thereof, and may also include silicon nitride, etc.; the barrier layer 241 may be a single-layer film layer or a multi-layer film layer.

[0055] In some embodiments, the barrier layer 241 may include photoresist, and the photoresist may be spin-coated on a wafer including the semiconductor layer 200 and cured, and the photoresist may be filled into the first opening 21; the position of the first opening 21 may be aligned for photolithography and development, and a portion of the photoresist in the first opening 21 may be cleaned and removed, and the photoresist on the sidewall of the first opening 21 may be retained to form the barrier layer 241. The barrier layer 241 including the photoresist may be formed by combining the photolithography process, and the film thickness of the barrier layer 241 in the x direction may be controlled by the photolithography process, which is beneficial to improving the morphology uniformity of the first connection structure 220 and improving the manufacturing yield.

[0056] In some embodiments, the method comprises: referring to Fig.13 As shown, at least the first bump 211 a and the second bump 211 b are used as seed layers, and an electroplating process is performed to form a first sub-connection structure 221 a and a second sub-connection structure 221 b in the first opening 21 .

[0057] Electroplating is performed with the bump 211 as a seed layer to form a first connection structure 220 in the first opening 21, and the first connection structure 220 is located on the bump 211; the electroplating process parameters, including the concentration of the electroplating solution, the electroplating time, and the electroplating voltage / current, are adjusted to guide the first connection structure 220 to form a gap 222 in the first opening 21. The first connection structure 220 has a linear or columnar structure extending along the z direction, such as a nanowire nanocolumnar structure. For example, taking the first sub-connection structure 221a and the second sub-connection structure 221b as examples, there is a gap 222 between the first sub-connection structure 221a and the second sub-connection structure 221b, and the first sub-connection structure 221a and the second sub-connection structure 221b may not be in contact or may be in contact in some areas to form the gap 222. The first sub-connection structure 221a can be formed by electroplating growth or electroplating deposition of the seed layer of the first bump 211a, and the first sub-connection structure 221a is coupled to the first bump 211a; the second sub-connection structure 221b can be formed by electroplating growth or electroplating deposition of the seed layer of the second bump 211b, and the second sub-connection structure 221b is coupled to the second bump 211b. The disclosed embodiment does not limit the number of sub-connection structures, the number of bumps 211, and the specific shape of the gap 222; the sub-connection structure and the bump 211 are made of the same material, the bump 211 can be formed by physical deposition, chemical deposition or electroplating, and the sub-connection structure is formed by an electroplating process; there is no obvious physical boundary between the sub-connection structure and the bump 211.

[0058] Fig.13 The illustration of the sub-connection structure is an ideal illustration. In the specific embodiment, some sub-connection structures of the first connection structure 220 may be in contact with each other in some areas to form gaps 222 of various shapes, and the formation positions of the gaps 222 may not be restricted; some linear or columnar sub-connection structures are in contact without boundaries, but not all sub-connection structures are in contact with each other, and some areas are gaps 222.

[0059] In some embodiments, Fig.13 There may be a gap between the first connection structure 220 and the semiconductor, and a barrier layer 241 or a dielectric material may be deposited in the gap by atomic layer deposition. The barrier layer 241 may fill the recess at the top of the first connection structure 220 to provide a relatively flat landing surface for the subsequent production of contacts 251.

[0060] In some embodiments, reference Fig.14 As shown, the manufacturing method further includes: forming a contact 251 on a side of the first connection structure 220 away from the contact structure 210, and the contact 251 is coupled to the first connection structure 220. Fig.13A dielectric material is formed on the first connection structure 220, the dielectric material is etched to form a groove that penetrates the dielectric material and exposes the first connection structure 220, and the groove is filled with a conductive material to form a contact 251. The contact 251 may include, but is not limited to: copper, aluminum, tungsten, gold, silver, platinum, chromium, nickel, cobalt, titanium and other conductive materials; for example, copper and aluminum may be included to reduce the manufacturing cost. The contact 251 can be used as a contact pad, a contact bump, or a bonding pad, and is used to connect to an external integrated circuit for power supply, control signal interaction, or data transmission.

[0061] In some embodiments, the device structure includes Fig.15 The conductive structure 252 shown, the first connection structure 220 is coupled to the conductive structure 252 through the contact structure 210; other parts of the device structure are omitted; the method of forming the contact structure 210 includes:

[0062] Reference Fig.15 As shown, an insulating film 212 having a plurality of second openings 22 is attached to the conductive structure; the plurality of second openings 22 expose the conductive structure 252; Fig.15 Also shown is a schematic diagram of an enlarged cross section of a portion of the insulating film 212 in the xoy plane, where a portion of the second openings 22 correspond to the conductive structure 252 and expose the conductive structure 252, and other portions of the second openings 22 do not correspond to the conductive structure 252; Fig.16 As shown, a first dielectric layer 242 covering the insulating film 212 is formed; Fig.17 As shown, at the position of the first dielectric layer 242 corresponding to the conductive structure, a third opening 23 penetrating the first dielectric layer 242 is formed; the third opening 23 reveals a plurality of second openings 22, and the third opening 23 reveals the conductive structure 252 through the plurality of second openings 22; Fig.18 As shown, a plurality of bumps 211 are formed in the plurality of second openings 22 that expose the conductive structure 252, and the plurality of bumps 211 constitute a contact structure 210. In some embodiments, part of the material of the first dielectric layer is filled into the second opening 22, and the dielectric material in the second opening 22 can be removed to release the second opening 22 when forming the third opening 23.

[0063] exist Fig.15 In the embodiment, the insulating film 212 may be a polymer material film having a plurality of second openings 22, and is attached to the dielectric layer having the conductive structure 252 by heat pressing or gluing. Fig.16 A first dielectric layer 242 is formed by deposition. The first dielectric layer 242 may include but is not limited to silicon oxide, silicon nitride, and silicon oxynitride. The first dielectric layer 242 may be filled into the second opening 22 of the insulating film 212. Fig.17In the process, the position of the first dielectric layer 242 corresponding to the conductive structure is etched to form a third opening 23 penetrating the first dielectric layer 242, the third opening 23 reveals multiple first openings 21, the third opening 23 corresponds to the conductive structure and the third opening 23 reveals the conductive structure 252 through multiple second openings 22, that is, one third opening 23 corresponds to multiple second openings 22, and correspondingly reveals one conductive structure 252; the second opening 22 that does not correspond to the conductive structure is filled with the first dielectric layer 242. Fig.18 In the embodiment, the second opening 22 is filled with a conductive material to form a bump 211, such as forming the bump 211 by a deposition process or an electroplating process; after the bump 211 is formed, the conductive material may extend toward the third opening 23 along the z direction, or a portion of the bump 211 extends into the third opening 23, but the conductive material in the third opening 23 may become sticky and collapse; Fig.19 As shown, chemical mechanical grinding or etching can be performed to remove the first dielectric layer 242 and the conductive material in the third opening 23, and retain the insulating film 212 and the bump 211 located in the insulating film 212; Fig.13 The first connection structure 220 having the gap 222 is formed to provide a flat landing surface and a seed layer with good morphology to facilitate the formation of a sub-connection structure having the gap 222 .

[0064] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor layer, and a device structure at least located on the semiconductor layer; the device structure includes a contact structure located on the semiconductor layer; A first connection structure is located on a side of the contact structure close to the semiconductor layer and penetrates the semiconductor layer; the first connection structure is coupled to the contact structure; wherein the first connection structure at least includes a first sub-connection structure and a second sub-connection structure extending along the thickness direction, and there is a gap between the first sub-connection structure and the second sub-connection structure.

2. The semiconductor structure according to claim 1, characterized in that: The contact structure comprises: A plurality of convex points arranged at intervals, including at least a first convex point and a second convex point; The first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The barrier layer is located between the first connection structure and the semiconductor layer; the barrier layer surrounds the side wall of the first connection structure extending along the thickness direction.

4. The semiconductor structure according to claim 1, characterized in that The first sub-connection structure is in partial contact with the second sub-connection structure.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The contact point is located at a side of the first connection structure away from the contact structure; the contact point is coupled to the first connection structure.

6. The semiconductor structure according to claim 5, characterized in that: The size of the contact in the first direction is greater than the size of the first connection structure in the first direction; the contact is coupled to at least part of the sub-connection structures in the first connection structure; and the first direction intersects with the thickness direction.

7. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a semiconductor layer, at least forming a device structure on the semiconductor layer; the device structure includes a contact structure located on the semiconductor layer; the contact structure includes a plurality of bumps arranged at intervals, including at least a first bump and a second bump; Etching a side of the semiconductor layer away from the contact structure to form a first opening penetrating the semiconductor layer; the first opening exposes the contact structure; A first connection structure is formed in the first opening, and the first connection structure at least includes a first sub-connection structure and a second sub-connection structure extending along the thickness direction, and a gap is formed between the first sub-connection structure and the second sub-connection structure; wherein the first sub-connection structure contacts the first bump, and the second sub-connection structure contacts the second bump.

8. The method according to claim 7, characterized in that: The production method further comprises: Before forming the first opening, the side of the semiconductor layer away from the device structure is thinned.

9. The manufacturing method according to claim 7, characterized in that: The manufacturing method includes performing an electroplating process using at least the first bump and the second bump as a seed layer to form the first sub-connection structure and the second sub-connection structure in the first opening.

10. The manufacturing method according to claim 8, characterized in that: The production method further comprises: A barrier layer is formed between the first connection structure and the semiconductor layer, and the barrier layer surrounds a side wall of the first connection structure extending along the thickness direction.

11. The manufacturing method according to claim 7, characterized in that: The device structure includes a conductive structure, and the first connecting structure is coupled to the conductive structure through the contact structure; The method of forming the contact structure comprises: An insulating film having a plurality of second openings is attached to the conductive structure; the plurality of second openings expose the conductive structure; forming a first dielectric layer covering the insulating film; A third opening penetrating the first dielectric layer is formed at a position of the first dielectric layer corresponding to the conductive structure; the third opening exposes a plurality of the second openings, and the third opening exposes the conductive structure through the plurality of the second openings; A plurality of the bumps are formed in the plurality of the second openings exposing the conductive structure, and the plurality of the bumps constitute the contact structure.

12. The manufacturing method according to claim 7, characterized in that: The production method further comprises: A contact is formed on a side of the first connecting structure away from the contact structure, and the contact is coupled to the first connecting structure.

Images