Buried interconnect across trench isolation

Abstract

The invention relates to a buried interconnect across trench isolation. The present disclosure relates to semiconductor structures, and more particularly to buried interconnect structures and methods of manufacture. The structure comprises a semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; and at least one buried interconnect structure in the semiconductor substrate and traversing the trench isolation structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to buried interconnect structures and methods of fabrication. Background Art

[0002] In electronic design, routing is a step in integrated circuit (IC) design. Routing adds the wires required to properly connect components while adhering to integrated circuit design rules.

[0003] Design rules vary significantly between layers and circuits. For example, the width and spacing allowed on the lower layer may be much smaller than the width and spacing allowed on the upper layer. This introduces many complexities. In addition, technology routing density limitations may negatively impact latency of dense logic and memory blocks. Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; and at least one buried interconnect structure located in the semiconductor substrate and crossing the trench isolation structure.

[0005] In one aspect of the present disclosure, a structure includes: a semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; a buried interconnect structure including a metal material, the buried interconnect structure being located below a top surface of the semiconductor substrate and adjacent to the trench isolation structure; and a via interconnect structure contacting the buried interconnect structure and extending through the trench isolation structure.

[0006] In one aspect of the present disclosure, a method includes forming a trench isolation structure extending into a semiconductor substrate; and forming at least one buried interconnect structure in the semiconductor substrate that traverses the trench isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings.

[0008] Figure 1A A top view of a buried interconnect structure and corresponding fabrication process is shown, among other features, in accordance with some aspects of the present disclosure.

[0009] Figure 1B Shows a cross section taken along line AA Figure 1A Cross-sectional view of a buried interconnect structure.

[0010] Figure 2 A buried interconnect structure is shown, among other features, in accordance with additional aspects of the present disclosure.

[0011] Figure 3 A buried interconnect structure is shown, among other features, in accordance with further aspects of the present disclosure.

[0012] Figure 4A A top view of a buried interconnect structure is shown, among other features, in accordance with some aspects of the present disclosure.

[0013] Figure 4B Shows a cross section taken along line AA Figure 4A Cross-sectional view of a buried interconnect structure.

[0014] Figure 4C Shows a section taken along line BB Figure 4A Cross-sectional view of a buried interconnect structure.

[0015] Figure 5 A circuit diagram is shown having, among other features, a buried interconnect structure in accordance with some aspects of the present disclosure.

[0016] Figure 6 A logic cell having a buried interconnect structure according to some aspects of the present disclosure, among other features, is shown.

[0017] Figure 7 Devices having buried interconnect structures according to, among other features, some aspects of the present disclosure are shown.

[0018] Figures 8A-8D A fabrication process for fabricating a buried interconnect structure according to some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0019] The present disclosure relates to semiconductor structures, and more particularly to buried interconnect structures and methods of manufacturing. More particularly, the present disclosure relates to buried interconnect structures that traverse trench isolation structures within a semiconductor substrate. Advantageously, for example, the present disclosure provides improved wiring density (e.g., about 30% higher than conventional schemes), reduced well resistance, and reduced gate resistance in dense logic and memory blocks. When the buried interconnect is routed parallel to the gate line, a reduced gate resistance can be provided. The reduced gate resistance also provides a beneficial delay reduction.

[0020] In a more specific embodiment, the buried metal interconnect structure increases the wiring density, reduces the delay in dense logic and memory blocks, and reduces the well resistance. The buried metal interconnect structure can be disposed in the semiconductor substrate, below the active device. The active device can be, for example, a transistor. The buried interconnect structure can also traverse the trench isolation structure. In an embodiment, the via contact connects the back-end of line (BEOL) metal to the buried metal interconnect structure through, for example, the trench isolation structure.

[0021] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithographic process. Specifically, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; (iii) selectively etching the film to the mask; and (iv) an implantation step. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants from the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0022] Figure 1A A top view showing, among other features, a buried interconnect structure and a corresponding fabrication process, Figure 1B Shows Figure 1A More specifically, referring to Figure 1A and 1B , structure 10 includes an interconnect structure 12 buried in a semiconductor substrate 14. In an embodiment, semiconductor substrate 14 may be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate. Semiconductor substrate 14 may include any semiconductor material, including but not limited to Si. For example, semiconductor substrate 14 may be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors.

[0023] The buried interconnect structure 12 is located below the top surface of the semiconductor substrate 14. In an embodiment, the buried interconnect structure 12 may be located about 150 nanometers below the surface of the semiconductor substrate 14; although other dimensions are also contemplated herein. It should be understood by those skilled in the art that the buried interconnect structure 12 will improve (e.g., increase) routing density because the interconnect structure 12 is not within any FEOL or BEOL metal layer.

[0024] The buried interconnect structure 12 may be any conductive material. For example, as examples, the buried interconnect structure 12 may be tungsten, aluminum, or ruthenium. In alternative embodiments, the buried interconnect structure 12 may be other refractory metals or thermally stable metals. In an embodiment, the buried interconnect structure 12 may also include an optional dielectric liner 12a. The dielectric liner 12a may be an oxide material or other insulator material, such as a nitride or the like.

[0025] like Figure 1BAs further shown, the buried interconnect structure 12 traverses (e.g., extends through) the trench isolation structure 16. The trench isolation structure 16 may surround or enclose a portion of the buried interconnect structure 12. For example, the trench isolation structure 16 may be located at a side surface and below (e.g., a bottom surface) the buried interconnect structure 12.

[0026] The trench isolation structure 16 can be formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, the resist formed above the semiconductor substrate 14 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemical action, such as reactive ion etching (RIE), will be used to transfer the pattern from the resist layer to the semiconductor substrate 14 to form one or more trenches in the semiconductor substrate 14 through the openings of the resist. After the resist is removed by a conventional oxygen ashing process or other known stripping agent, an insulator material (e.g., SiO2) can be deposited by any conventional deposition process (e.g., a chemical vapor deposition (CVD) process). Any residual material on the surface of the semiconductor substrate 14 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0027] The via interconnect 18 extends within the trench isolation structure 16 and makes physical and electrical contact with the buried interconnect structure 12. In an embodiment, the via interconnect 18 can be any conductive material known to those of ordinary skill in the art, and therefore, no further explanation is required. For example, the via interconnect 18 can be tungsten, aluminum, or other known metals known in the art. The upper via interconnect 20 can be physically and electrically connected to the via interconnect 19. The upper via interconnect 20 can be tungsten, aluminum, or other known metals known in the art. Although not shown, the upper via interconnect 20 can be connected to an upper wiring layer (BEOL wiring structure) set in a specific wiring scheme based on the desired design layout.

[0028] The trench isolation structure 16 may be located between the active regions 22 of the device 24. For example, the device 24 may be a plurality of transistors, such as a gate structure, such as Figure 1A As shown. The gate structure 24 may be, for example, a finFET structure (e.g., a gate line) or a planar structure disposed on a bulk substrate or a semiconductor-on-insulator substrate (SOI) (e.g., semiconductor substrate 14). In addition, in an embodiment, the gate structure 24 may be a finger (e.g., a gate line) extending on the side of the trench isolation structure 16. In an embodiment, the gate structure 24 may include a low-k or high-k dielectric material as well as polysilicon or a work function metal or a combination thereof as known in the art.

[0029] In an embodiment, active regions (eg, structured fins) 22 may be raised source and drain regions adjacent to gate structure 24. Source and drain regions 22 may be formed by an epitaxial growth process using an in-situ doping process, or subsequently performing an ion implantation process as is known in the art.

[0030] Figure 2 A buried interconnect structure is shown, among other features, in accordance with additional aspects of the present disclosure. Figure 2 In structure 10a, epitaxial semiconductor material 26 may be formed on the surface of semiconductor substrate 14. Thus, buried interconnect structure 12 is located below the surface of epitaxial semiconductor material 26 and semiconductor substrate 14. For example, buried interconnect structure 12 may be located approximately 50 nanometers below the top surface of semiconductor substrate 14 and approximately 150 nanometers below the top surface of epitaxial semiconductor material 26; although other dimensions are contemplated herein. Thus, the depth of the trench used to form buried interconnect structure 12 in semiconductor substrate 14 may be greater than 10 nanometers. Figure 1A and 1B The structure 10 shown is shallow, which in turn provides certain manufacturing and electrical advantages, such as reducing the energy of the ion implantation process that forms the trenches used to create the buried interconnect structure 12.

[0031] Still reference Figure 2 , the epitaxial semiconductor material 26 can be formed, for example grown, after the buried interconnect structure 12 is formed. In an embodiment, the epitaxial semiconductor material 26 can be Si; although other materials are also contemplated herein as described with respect to the semiconductor substrate 14. Moreover, in this embodiment, the buried interconnect structure 12 surrounds the trench isolation structure 16, for example, on the sides; although the present disclosure also contemplates other configurations described herein. For example, in this configuration, the buried interconnect structure 12 does not extend through the trench isolation structure 16. Therefore, in this embodiment, the trench isolation structure 16 does not contact the bottom surface of the buried interconnect structure 12. The remaining features of the structure 10a are similar to those of FIG. Figure 1A and 1B The structure 10 is shown, therefore, and no further explanation is required to fully understand the present disclosure.

[0032] Figure 3 10b shows a buried interconnect structure according to further aspects of the present disclosure, among other features. In this structure 10b, the buried interconnect structure 12 is buried deeper into the semiconductor substrate 14. In this configuration, the trench isolation structure 16 does not extend below the buried interconnect structure 12. For example, the buried interconnect structure 12 can be about 300 nanometers below the surface of the semiconductor substrate 14, which allows the buried interconnect structure 12 to traverse at the bottom of the trench isolation structure 16. The remaining features of the structure 10b are similar to those of FIG. Figure 1A and 1BThe structure 10 is shown, therefore, and no further explanation is required to fully understand the present disclosure.

[0033] Figure 4A A top view of a buried interconnect structure showing, among other features, Figure 4B Shows a cross section taken along line AA Figure 4A A cross-sectional view of a buried interconnect structure, Figure 4C Shows a section taken along line BB Figure 4A A cross-sectional view of a buried interconnect structure. Figures 4A-4C In the structure 10c shown, the buried interconnect structure 12 surrounds the trench isolation structure 16. More specifically, the buried interconnect structure 12 will stop at the boundary of the trench isolation structure 16. As in each embodiment, the trench isolation structure 16 may include a tapered profile so that Figure 4A and 4B In the configuration shown, the buried interconnect structure 12 stops at the tapered sidewalls of the trench isolation structure 16. The via interconnect 18 also extends partially within the trench isolation structure 16 and physically and electrically contacts the buried interconnect structure 12. Figure 4A As shown, the via interconnect 20 may also extend over the gate structure 24. The remaining features of the structure 10c are similar to those of Figure 1A and 1B The structure 10 is shown, therefore, and no further explanation is required to fully understand the present disclosure.

[0034] Figure 5 A circuit 100 having a buried interconnect structure 12 is shown, among other features, in accordance with some aspects of the present disclosure. In an embodiment, the circuit diagram 100 may be part of a dense logic or memory block. The circuit 100 includes a long continuous gate structure 24, such as a finFET or a gate line, positioned adjacent to an active area 22. The buried interconnect structure 12 is disposed within the semiconductor substrate 14, between and parallel to the long continuous gate structures 24. The buried interconnect structure 12 may be strapped to the gate structure 24 by via interconnects 18, 20, thereby reducing resistance and delay.

[0035] Figure 6 1 shows a logic cell 200 having a buried interconnect structure 12 according to some aspects of the present disclosure, among other features. In an embodiment, the logic cell 200 may represent an inverter. Figure 6In the structure shown, the buried interconnect structures 12 are Vdd and Vss lines, respectively. The buried interconnect structures 12 (Vdd and Vss) reduce the track height of the standard primitive library. That is, since the power / ground rails are no longer located on the upper metal layer, the buried interconnect structures 12 (Vdd and Vss) reduce the wiring complexity. In this configuration, wiring 28 and external wiring 30 can be provided to the active area 22, and the via interconnects 18, 20 can electrically connect the buried interconnect structures 12 (Vdd and Vss) to the active area 22.

[0036] Figure 7 A device 300 having, among other features, a buried interconnect structure 12 according to some aspects of the present disclosure is shown. Figure 7 In the device 300, the semiconductor substrate 14 may include a fully depleted semiconductor-on-insulator technology. The semiconductor substrate 14 may include an N-well 14a and a P-well 14b located between the N-wells 14a, wherein a gate structure 24 (e.g., a finFET or a gate line) extends parallel to the N-well 14a and the P-well 14b and above the N-well 14a and the P-well 14b. A buried interconnect structure 12 may be disposed in each of the N-well 14a and the P-well 14b, extending perpendicularly to the gate structure 24. Via interconnects 18, 20 may be disposed in each of the N-well 14a and the P-well 14b at the ends of the buried interconnect structure 12.

[0037] For example, in Figure 7 In the integrated scheme of FIG. 1 , the buried interconnect structure 12 is electrically connected to the P well 14 b between the N wells 14 a. Therefore, the embodiment of the buried interconnect structure 12 can reduce the well resistance, thereby reducing the density of the well taps. It will be appreciated by those skilled in the art that in conventional structures, the well resistance requires the well taps to be placed close to each other. In addition, the use of the buried interconnect structure 12 saves area because the connections to the N well 14 a and the P well 14 b can be placed between adjacent gate structures 24.

[0038] Figures 8A-8D A fabrication process for fabricating a buried interconnect structure according to some aspects of the present disclosure is shown. Fig. 8A and 8B is a cross-sectional view of the constructed structure; and Figure 8B'-8D This is a top view of the building structure.

[0039] refer to Fig. 8A, an implantation mask 30 is formed over the semiconductor substrate 14. The implantation mask 30 is patterned using conventional photolithography and etching processes to form openings 32, which correspond to selected exposed areas for forming sacrificial regions 34. The implantation mask may include a layer of photosensitive material, such as an organic photoresist layer, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and blocking capability sufficient to prevent the masked area from receiving a certain dose of implanted ions.

[0040] Ion implantation is performed through the opening 32 of the implantation mask 30, followed by an annealing process, thereby forming a sacrificial region (crystalline material) 34 deep into the semiconductor substrate 14. The sacrificial region 34 can be set at the same depth as the buried interconnect structure, for example, a depth of 50 to 300 nm. The ion implantation can use lower energy to form the sacrificial region 34 at a shallower position in the semiconductor substrate. In an embodiment, the ion implantation can be, for example, N+, O+, or Ge+. The sacrificial region 34 can be, for example, SiN, SiO, or SiGe (or other materials selective to the semiconductor substrate 14), respectively.

[0041] exist Figure 8B and 8B ', the implantation mask is removed and a hard mask 36 is formed over the semiconductor substrate 14. In an embodiment, an opening 38 is formed in the hard mask 36. The opening 38 can be formed by conventional photolithography and etching processes. A selective etch, such as RIE, is performed to form a trench 40 in the semiconductor substrate 14. The etching will stop on the sacrificial region 34.

[0042] exist Figure 8C In the embodiment, an air gap 42 is formed in the semiconductor substrate 14, connecting the two trenches 40. In an embodiment, the air gap 42 can be formed by wet etching the remaining sacrificial region (e.g., SiN material). In this way, a tunnel or air gap is formed below the surface of the semiconductor substrate 14, the ends of which are connected by the trenches 40. It should be understood that more than two trenches can be used to form the air gap 42.

[0043] exist Fig.8D In the embodiment, the air gap 42 is filled with a refractory metal to form a buried interconnect structure 12. In an embodiment, a dielectric liner 12a may be deposited before depositing the refractory metal. In other embodiments, the refractory metal may also be used to form a via interconnect 18 within the trench 40. The refractory metal may be formed by a conventional deposition process (e.g., chemical vapor deposition). The refractory metal may be, for example, a nitride with an excellent fill factor, such as TiN, TaN, or a metal material. When the size of the air gap 42 is several microns, the CVD gas should not cause pinch-off; although other manufacturing processes and sizes are contemplated herein.

[0044] These structures can be used in system-on-chip (SOC) technology. A SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (for example, in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0045] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0046] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: Semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; as well as At least one buried interconnect structure is located in the semiconductor substrate and traverses the trench isolation structure.

2. The structure according to claim 1, wherein: The at least one buried interconnect structure includes a metal interconnect beneath an active device.

3. The structure according to claim 1, wherein: The at least one buried interconnect structure extends through the trench isolation structure.

4. The structure according to claim 3, wherein: The trench isolation structure is located on the side and bottom surfaces of the at least one buried interconnect structure.

5. The structure according to claim 1, wherein: The at least one buried interconnect structure surrounds the trench isolation structure.

6. The structure according to claim 1, wherein: The at least one buried interconnect structure is located below a top surface of the semiconductor substrate.

7. The structure of claim 6 further comprising an epitaxial semiconductor material located above the semiconductor substrate.

8. The structure of claim 1, further comprising a via interconnect structure extending through the trench isolation structure from a top side, the via interconnect structure contacting the at least one buried interconnect structure.

9. The structure of claim 8, further comprising active regions and at least one gate structure located between the active regions, wherein: The at least one buried interconnect structure is perpendicular to the active region and parallel to the gate structure.

10. The structure according to claim 1, wherein: The at least one buried interconnect structure includes a Vss line and a Vdd line electrically tied to the active region.

11. The structure according to claim 1, wherein: The semiconductor substrate includes an N-well and a P-well, and the buried interconnect structure extends within the N-well and the P-well.

12. The structure according to claim 11, wherein: The semiconductor substrate includes a fully depleted semiconductor-on-insulator material.

13. The structure according to claim 1, wherein: The semiconductor substrate includes a bulk semiconductor material.

14. A structure comprising: Semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; a buried interconnect structure comprising a metal material, the buried interconnect structure being located below a top surface of the semiconductor substrate and adjacent to the trench isolation structure; as well as A via interconnect structure contacts the buried interconnect structure and extends through the trench isolation structure.

15. The structure according to claim 14, wherein: The metal material includes a refractory metal.

16. The structure of claim 14, wherein: The buried interconnect structure extends through the trench isolation structure.

17. The structure of claim 14, wherein: The buried interconnect structure surrounds the trench isolation structure.

18. The structure of claim 14, further comprising an epitaxial semiconductor material overlying the semiconductor substrate, the trench isolation structure extending through the epitaxial semiconductor material and the semiconductor substrate.

19. The structure of claim 14, wherein: The buried interconnect structure is disposed at a bottom of the trench isolation structure.

20. A method comprising: forming a trench isolation structure extending into the semiconductor substrate; as well as At least one buried interconnect structure is formed in the semiconductor substrate traversing the trench isolation structure.

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