Buck converter based on conduction time control

Abstract

The invention belongs to the technical field of step-down circuits, and discloses a step-down converter based on turn-on time control, which comprises a logic control module used for generating a first driving signal and a second driving signal based on a received turn-off signal, a start signal and a bias comparison signal, and sending the first driving signal and the second driving signal to a dead time control module and a sleep time detection module; the sleep time detection module is used for generating a mode control signal based on the first driving signal and the second driving signal; the mode control signal is respectively sent to a bias loop comparison module and an error amplification module; the bias loop comparison module is used for generating a bias comparison signal based on a first bias current and sending the bias comparison signal to the logic control module when the mode control signal is at a high level, and generating a bias comparison signal based on a second bias current and sending the bias comparison signal to the logic control module when the mode control signal is at a low level; the second bias current is less than the first bias current. According to the invention, the quiescent current consumption under the ultra-light load can be reduced and the efficiency of the ultra-light load can be improved on the basis of keeping the high response speed under the conventional load.

Description

Technical Field

[0001] The present application relates to the technical field of buck circuits, and in particular to a buck converter based on on-time control. Background Art

[0002] With the rapid growth of Internet of Things (IoT) devices, for devices that rely on random and sparse events, when no critical events are detected, their operating current can be reduced to the microampere (uA) level. On the contrary, once an important event is captured, the current demand may soar to tens or even hundreds of milliamperes (mA). A buck converter is a circuit that converts a larger input voltage into a smaller output voltage. The control circuit generates a control square wave with a specific duty cycle to control the switching of the power switch tube to ensure that the output voltage remains constant while meeting the current demand of the load. Therefore, the demand for buck converters that can provide long battery life is becoming increasingly urgent.

[0003] Adaptive on-time control has many advantages, such as high efficiency, good transient response, and frequency stability. However, conventional adaptive on-time control still cannot achieve low quiescent current consumption at the uA level of load current. Summary of the invention

[0004] The present application provides a buck converter based on on-time control, which can reduce the static current consumption under ultra-light load and improve the efficiency of ultra-light load while retaining the fast response speed under normal load.

[0005] In a first aspect, an embodiment of the present application provides a buck converter based on on-time control, comprising:

[0006] The shortest time shutdown module is used to receive the first conduction signal of the first switch tube, generate a shutdown signal when the first conduction signal is at a high level, and send it to the logic control module;

[0007] A conduction time generating module, used for receiving a second conduction signal of the second switch tube, generating a start signal when the second conduction signal is at a high level, and sending the start signal to the logic control module;

[0008] A logic control module, configured to generate a first drive signal and a second drive signal based on the received shutdown signal, the startup signal and the bias comparison signal, and send the signals to the dead time control module and the sleep time detection module;

[0009] A dead time control module, used to generate a first conduction signal and a second conduction signal according to the first drive signal and the second drive signal, send the first conduction signal to the gate of the first switch tube and the shortest time shutdown module, and send the second conduction signal to the gate of the second switch tube and the conduction time generation module;

[0010] A sleep time detection module, used for generating a mode control signal based on the first drive signal and the second drive signal; and sending the mode control signal to the bias loop comparison module and the error amplification module respectively;

[0011] The bias loop comparison module is used to generate a bias comparison signal based on a first bias current and send it to a logic control module when the mode control signal is at a high level, and to generate a bias comparison signal based on a second bias current and send it to the logic control module when the mode control signal is at a low level; the second bias current is smaller than the first bias current.

[0012] Furthermore, it also includes an error amplification module, a soft start module, a feedback resistor array, a loop compensation module and a selection module;

[0013] The output end of the error amplification module and the output end of the loop compensation module are both connected to the input end of the selection module; the output end of the selection module is connected to the negative input end of the bias loop comparison module;

[0014] The soft start module is used to amplify the reference voltage selection signal according to the received first enable signal, and send it to the error amplification module until the voltage of the reference voltage selection signal is equal to the preset reference voltage;

[0015] The feedback resistor array is used to generate a feedback voltage signal according to the input voltage signal and send it to the error amplification module;

[0016] The sleep time detection module is also used to send the mode control signal to the selection module and the error amplification module;

[0017] The error amplification module is used to generate an error amplification signal according to the feedback voltage signal and the reference voltage selection signal when the mode control signal is at a high level, and send it to the selection module; it is turned off when the mode control signal is at a low level;

[0018] The selection module is used to send the error amplification signal to the bias loop comparison module when the mode control signal is at a high level, and to send the second enable signal to the bias loop comparison module when the mode control signal is at a low level.

[0019] Furthermore, the sleep time detection module is also used to send a mode control signal to the loop compensation module;

[0020] The loop compensation module is turned off when the mode control signal is low.

[0021] Furthermore, the soft start module is also used to perform a shutdown operation when the voltage of the reference voltage selection signal is equal to a preset reference voltage.

[0022] Furthermore, the buck converter also includes an inductor current sampling module;

[0023] The inductor current sampling module is connected in parallel with the inductor in the buck converter, and is used to generate an inductor sensing signal according to the sampled inductor current value, and input the signal into the positive input terminal of the bias loop comparison module;

[0024] The bias loop comparison module is specifically used to generate a bias comparison signal according to the inductance sensing signal, the error amplification signal and the first bias current, or to generate a bias comparison signal according to the inductance sensing signal, the second enable signal and the second bias current.

[0025] Furthermore, the buck converter also includes a current zero-crossing detection module;

[0026] The dead time control module is also used to send the first conduction signal to the current zero-crossing detection module;

[0027] The current zero-crossing detection module is used to receive the inductor voltage signal, generate a current detection signal according to the first conduction signal and the inductor voltage signal, and send the current detection signal to the logic control module;

[0028] The logic control module is specifically used to generate a first drive signal and a second drive signal according to a shutdown signal, a start signal, a current detection signal and a bias comparison signal.

[0029] Further, the current zero-crossing detection module includes a delay unit and a detection unit connected to each other;

[0030] The delay unit is used to delay the first conduction signal and send it to the detection unit;

[0031] The detection unit is used to determine whether the inductor voltage signal is lower than a preset detection threshold when the first conduction signal after the delay is at a high level. If so, a high-level current detection signal is output, otherwise a low-level current detection signal is output.

[0032] Further, the sleep time detection module includes a counting unit, an oscillation control unit, an RC oscillation unit and a mode selection unit; the counting unit is used to generate a sleep signal according to the first drive signal and the second drive signal; the received clock signal is counted according to the sleep signal to obtain a first count value, a second count value and a third count value;

[0033] The oscillation control unit is used to generate an initial control signal according to the first count value, the second count value and the third count value, and send it to the mode selection unit; and, generate an oscillation control signal according to the initial control signal and the sleep signal of the counting unit, and send it to the RC oscillation unit; the RC oscillation unit is used to generate a clock signal according to the oscillation control signal, and send it to the counting unit;

[0034] The mode selection unit is used for generating a mode control signal according to the sleep signal and the initial control signal.

[0035] Further, the counting unit includes an XOR gate, a first inverter, a second inverter, a first counter, a second counter and a third counter; the input end of the XOR gate is used to receive the first drive signal and the second drive signal;

[0036] The XOR gate, the first inverter and the second inverter are connected in sequence; the second inverter is used to output a sleep signal and send it to the reset ports of the first counter, the second counter and the third counter;

[0037] The clock input terminal of the first counter is used to receive a clock signal, the data input terminal and the second output terminal are both connected to the clock input terminal of the second counter, and the first output terminal is used to output a first count value; the data input terminal and the second output terminal of the second counter are both connected to the clock input terminal of the third counter, and the first output terminal is used to output a second count value; the data input terminal and the second output terminal of the third counter are connected, and the first output terminal is used to output a third count value.

[0038] Furthermore, the oscillation control unit is specifically used to perform an AND operation on the first count value and the third count value to obtain a fourth count value; perform an AND operation on the second count value and the third count value to obtain a fifth count value; perform an OR operation on the third count value, the fourth count value and the fifth count value to obtain an initial control signal; and perform an AND operation on the initial control signal and the sleep signal to obtain an oscillation control signal.

[0039] Furthermore, the mode selection unit is specifically used to input the inverted sleep signal and the initial control signal into the D flip-flop to obtain the mode control signal.

[0040] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0041] An embodiment of the present application provides a buck converter based on on-time control, in which an added sleep time detection module utilizes the characteristics that the first drive signal and the second drive signal change with the load, and determines whether the buck converter is operating in a normal load mode or an ultra-light load mode according to the two drive signals. If it is the former, a high-level mode control signal is output, and if it is the latter, a low-level mode control signal is output. At the same time, the bias loop comparison module in the buck converter switches the corresponding operating mode according to the mode control signal, reduces the bias current, and thus reduces the static current consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A circuit diagram of a buck converter based on on-time control is provided in accordance with an embodiment of the present application.

[0043] Figure 2 This is a diagram of the key nodes and waveforms of various signals in the CCM mode provided by one embodiment of the present application.

[0044] Figure 3 A circuit diagram of a counting unit, an oscillation control unit and a mode selection unit provided in one embodiment of the present application.

[0045] Figure 4 A circuit structure diagram of an RC oscillation unit provided in accordance with an embodiment of the present application.

[0046] Figure 5 This is a working waveform diagram of a sleep time detection module provided in one embodiment of the present application.

[0047] Figure 6 An internal circuit structure diagram of a bias loop comparison module provided in one embodiment of the present application.

[0048] Figure 7 This is a diagram of the internal circuit structure of a current zero-crossing detection module provided in one embodiment of the present application.

[0049] Figure 8 An internal circuit structure diagram of a soft start module provided in one embodiment of the present application.

[0050] Fig. 9 This is a working waveform diagram of a soft start module provided in one embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0052] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0053] See also Figure 1 , an embodiment of the present application provides a buck converter based on on-time control, comprising:

[0054] The shortest time shutdown module is used to receive the first conduction signal of the first switch tube, generate a shutdown signal when the first conduction signal is at a high level, and send the shutdown signal to the logic control module.

[0055] The conduction time generating module is used to receive the second conduction signal of the second switch tube, generate a start signal when the second conduction signal is at a high level, and send the start signal to the logic control module.

[0056] It can be considered that the shortest time shutdown module only works when the first switch tube is turned on, and the on-time generation module only works when the second switch tube is turned on, thereby reducing the static current consumption of the two circuits.

[0057] The logic control module is used to generate a first driving signal and a second driving signal based on the received shutdown signal, the start signal and the bias comparison signal, and send the signals to the dead time control module and the sleep time detection module.

[0058] The dead time control module is used to generate a first conduction signal and a second conduction signal according to the first drive signal and the second drive signal, send the first conduction signal to the gate of the first switch tube and the shortest time shutdown module, and send the second conduction signal to the gate of the second switch tube and the conduction time generation module.

[0059] The sleep time detection module is used to generate a mode control signal based on the first drive signal and the second drive signal; and send the mode control signal to the bias loop comparison module and the error amplification module respectively.

[0060] The bias loop comparison module is used to generate a bias comparison signal based on a first bias current and send it to a logic control module when the mode control signal is at a high level, and to generate a bias comparison signal based on a second bias current and send it to the logic control module when the mode control signal is at a low level; the second bias current is smaller than the first bias current.

[0061] Among them, the first switch tube is Figure 1 The high-side switch power tube SP in the second switch tube is Figure 1 The low-side switch power tube SN in the embodiment has a first conduction signal of signal N, a second conduction signal of signal P, and a shutdown signal of signal T. OFF.MIN , the start signal is T ON , the first drive signal is PWM_N, the second drive signal is PWM_P; the mode control signal is Mode, and the bias loop comparison module is Figure 1 The output bias comparison signal is V C .

[0062] Furthermore, the buck converter also includes a current zero-crossing detection module ZCD.

[0063] The dead time control module is further used to send the first conduction signal to the current zero-crossing detection module.

[0064] The current zero-crossing detection module is used to receive the inductor voltage signal V SW , according to the first conduction signal N and the inductor voltage signal V SW Generates current detection signal V ZCD , and sent to the logic control module; the logic control module is specifically used to detect the current according to the shutdown signal, the start signal, and the current detection signal V ZCD and the offset comparison signal V C A first drive signal and a second drive signal are generated.

[0065] It can be understood that the above-mentioned minimum time shutdown module, on-time generation module, logic control module, dead time control module, bias loop comparison module and current zero-crossing detection module are all inherent modules in the existing buck converter.

[0066] The change of each signal waveform in the circuit in continuous conduction mode (CCM) is as follows Figure 2 As shown, the working principles are the working principles of the buck converter in the prior art, and will not be elaborated here.

[0067] The improvement of the present application lies in the addition of a sleep time detection module, generating a mode control signal according to the first drive signal and the second drive signal, and improving the internal part of the bias loop comparison module so that it switches the working mode according to the mode control signal.

[0068] First, for the newly added sleep time detection module in this application, its internal circuit structure can be found in Figure 3 and Figure 4 The sleep time detection module includes a counting unit (3_bit_counter), an oscillation control unit (RC_OSC_Control), an RC oscillation unit (RC_OSC) and a mode selection unit (MODE Selector).

[0069] The counting unit is used to generate a sleep signal according to the first driving signal and the second driving signal; and count the received clock signal according to the sleep signal to obtain a first count value CNT1, a second count value CNT2 and a third count value CNT4.

[0070] Depend on Figure 3 It can be seen that the counting unit includes an XOR gate, a first inverter, a second inverter, a first counter, a second counter and a third counter; the input end of the XOR gate is used to receive the first drive signal and the second drive signal.

[0071] The XOR gate, the first inverter and the second inverter are connected in sequence; the second inverter is used to output the sleep signal T SLEEP , and sent to the reset port RDN of the first counter, the second counter and the third counter.

[0072] The clock input terminal of the first counter is used to receive the clock signal CLK_OSC, the data input terminal and the second output terminal are both connected to the clock input terminal of the second counter, and the first output terminal is used to output the first count value CNT1; the data input terminal and the second output terminal of the second counter are both connected to the clock input terminal of the third counter, and the first output terminal is used to output the second count value CNT2; the data input terminal and the second output terminal of the third counter are connected, and the first output terminal is used to output the third count value CNT4.

[0073] The oscillation control unit is used to generate an initial control signal according to the first count value, the second count value and the third count value, and send it to the mode selection unit; and generate an oscillation control signal according to the initial control signal and the sleep signal of the counting unit, and send it to the RC oscillation unit; specifically, see Figure 3 In the oscillation control unit, the first count value and the third count value are ANDed to obtain the fourth count value S5, the second count value and the third count value are ANDed to obtain the fifth count value S6, and then the third count value, the fourth count value and the fifth count value are NORed to obtain the initial control signal SUMR. Then the initial control signal SUMR and the sleep signal T SLEEP An AND operation is performed to obtain the oscillation control signal EN_OSC.

[0074] See also Figure 4 The RC oscillation unit is used to generate a clock signal CLK_OSC according to the oscillation control signal EN_OSC and send it to the counting unit. The mode selection unit is used to generate a mode control signal according to the sleep signal and the initial control signal.

[0075] Specifically, the mode selection unit is specifically used to convert the sleep signal T SLEEP After being inverted by the input inverter, the input signal and the initial control signal SUMR are input into the D flip-flop to obtain a mode control signal.

[0076] It can be understood that the sleep time detection module obtains the corresponding sleep time length based on the driving signals of the two switching power tubes, thereby judging the current load condition of the buck converter and further adjusting the working mode of the buck converter control loop.

[0077] See also Figure 5 When a switching cycle starts, PWM_P and PWM_N are low level, the high-side switch power tube SP is turned on, and the low-side switch power tube SN is turned off. At this time, the sleep signal T SLEEP After the high-side switch power tube SP is turned on for a period of time, PWM_P and PWM_N become high level, after which the high-side switch power tube SP is turned off and the low-side switch power tube SN is turned on. At this time, the sleep signal T SLEEP Still at low level, the counting unit is still in the reset stage.

[0078] Then, two situations are discussed, namely, continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In CCM, the current zero-crossing detection module fails to detect the inductor current zero-crossing. In one switching cycle, the sleep signal T SLEEPis 0, the RC oscillator unit does not work, and the three counters are in the reset stage; in DCM, when the current zero-crossing detection module detects that the inductor current crosses zero, PWM_N becomes a low level, and then in the remaining time of a switching cycle, PWM_P is a high level, PWM_N is a low level, T SLEEP becomes high level, the counting unit starts to count the rising edge of CLK_OSC output by the RC oscillator unit; in CCM, the sleep signal T SLEEP is always low, so EN_OSC is also low, the RC oscillator unit does not work, at this time only a few gate circuits and D flip-flops work, almost zero power consumption; in DCM, when the sleep signal T SLEEP When the rising edge of CLK_OSC output by the RC oscillator unit does not reach 4, CNT4, S5 and S6 are all low, and the SUMR output after the NAND gate is high. Therefore, the enable signal EN_OSC of the RC oscillator unit is high, and the RC oscillator unit continues to output the clock signal CLK_OSC. If the rising edge of CLK_OSC does not reach 4 within a switching cycle, the RC oscillator unit is shut down by the sleep signal T SLEEP Reset, if the rising edge of CLK_OSC can reach 4 in one switching cycle, then after the counting unit output reaches 4 (CNT4=1), SUMR becomes low level, and in the following time in one switching cycle, EN_OSC is 0, the RC oscillation unit remains closed, and then only a few gate circuits and D flip-flops work, with almost zero power consumption; the mode selection unit only includes 1 inverter and 1 D flip-flop; in normal load mode, whether in CCM or DCM, when the counting unit count does not reach 4, SUMR is always high level, and the mode control signal remains high level; when the circuit enters ultra-light load, in one switching cycle, when the counting unit counts to 4, CNT4 remains high level, SUMR becomes low level, T SLEEP After passing through the inverter, it serves as the input clock signal of the D flip-flop. When the next switching cycle comes, T SLEEP After the inverter is high in the initial stage, the output mode control signal is low at the end of the previous switching cycle.

[0079] Load current at Figure 1 Yes V OUT / R LOAO; Whether the load current is reduced to the ultra-light load threshold is determined by whether the third count value reaches 4 within a switching cycle; within a cycle, when PWM_P=0 / PWM_N=0, the high-side switch tube is turned on and the low-side switch tube is turned off. This is the charging stage, and the charging time is counted as t1; when PWM_P=1 / PWM_N=1, the high-side switch tube is turned off and the low-side switch tube is turned on. This is the discharging stage, and the discharging time is counted as t2; when PWM_P=1 / PWM_N=0, the high-side switch tube is turned off and the low-side switch tube is also turned off. This is the neither charging nor discharging stage, and the neither charging nor discharging time is counted as t3; in CCM mode (i.e., heavier load), t3=0; in DCM mode (i.e., lighter load / ultra-light load), t3>0; duty cycle D=t1 / (t1+t2+t3), and the duty cycle is proportional to the load current.

[0080] Therefore, the present application can be based on the sleep signal T SLEEP The characteristic of changing with load changes can switch the circuit working mode by detecting the sleep time. Once the load current decreases to the threshold of the ultra-light load mode, the buck converter control loop enters the ultra-light load mode to control the system static current consumption to the minimum.

[0081] Secondly, for improvements to the bias loop comparison module, see Figure 6 The shaded part in the figure, the present application adopts self-bias current technology in the bias loop comparison module. Since the bias loop comparison module is a circuit that needs to work all the time and cannot be set as a switch, when MODE=0, MPS1 is turned on, MPS2 is turned off, and the bias current of the bias loop comparison module is S_IB_COMP, which is relatively small; when MODE=1, MPS1 is turned off, MPS2 is turned on, and the bias current is L_IB_COMP, which is relatively large, so that when the load current is a normal value, a larger first bias current L_IB_COMP is used for biasing to obtain better comparator performance; when the load current is less than the threshold for entering the ultra-light load mode, a smaller second bias current S_IB_COMP is used for biasing, thereby reducing the static current consumption of the bias loop comparison module.

[0082] Finally, see Figure 7 As for the shaded part thereof, the present application also improves the current zero-crossing detection module. The current zero-crossing detection module of the present application includes a delay unit and a detection unit connected to each other.

[0083] The delay unit is used to delay the first conduction signal and send it to the detection unit.

[0084] The delay unit is Figure 7 The leftmost shaded part in the figure, the detection unit is the analog circuit on the right.

[0085] The detection unit is used to determine whether the inductor voltage signal is lower than a preset detection threshold when the first conduction signal after the delay is at a high level. If so, a high-level current detection signal is output, otherwise a low-level current detection signal is output. It can be understood that the current zero-crossing detection module of the present application has three functions: a switch function, an output mis-flipping prevention function, and an early flipping function.

[0086] For the switching function, the current zero-crossing detection module only works in the inductor current discharge phase, that is, it determines whether the inductor current is discharged based on the first conduction signal. If the first conduction signal is at a high level, the inductor current is detected. It remains closed and does not perform detection work at other times to minimize the circuit static current consumption.

[0087] Regarding the function of preventing output from being turned over incorrectly, since the existing circuit structure has already designed a low-power design for the current zero-crossing detection module, a false turning phenomenon caused by ringing may occur. In order to avoid this situation, the present application uses 1 inverter, 1 delay circuit and 1 OR gate to design a delay unit that can realize the function of preventing false turning over. At the initial stage of inductor current discharge, that is, when the first conduction signal becomes a high level, the delay circuit is used to shield the high level of the first conduction signal N of the low-side switch power tube, and delay the opening of the detection circuit. The circuit only works when NA and NB are both at a low level.

[0088] For the early flip function, since there is a certain delay in the control loop, in order to minimize the efficiency loss caused by the inductor current backflow, the present application uses two NMOS tubes MN1 and MN2 as pseudo resistors in the detection unit to set the output flip threshold in advance, increase the mismatch of the input end of the current zero-crossing detection module, so that before the inductor current discharges to zero, the V output by the current zero-crossing detection module ZCD The signal is flipped from low level to high level in advance, thereby turning off the low-side switch tube. These three functional designs can minimize the circuit static current consumption, improve circuit robustness and minimize efficiency loss.

[0089] In the above embodiment, a buck converter based on on-time control is provided. First, the added sleep time detection module utilizes the characteristics that the first drive signal and the second drive signal change with the load, and judges whether the buck converter is working in the normal load mode or the ultra-light load mode according to the two drive signals. The sleep signal T when both the high-side switch power tube and the low-side switch power tube are turned off in a switching cycle is SLEEP As the load current decreases, the sleep time is prolonged. Therefore, the sleep time detection module detects the sleep signal T SLEEP In CCM, the sleep signal T SLEEPThe RC oscillator does not work and the circuit consumes almost zero power. SLEEP When it becomes a high level, the RC oscillator unit starts working and the counting unit starts counting. If the rising edge of the output clock of the RC oscillator unit does not reach 4, a high-level mode control signal is output, that is, MODE=1, so that the control loop is in normal load mode. If the rising edge of the output clock of the RC oscillator unit reaches 4, then after the clock reaches 4, the RC oscillator unit is turned off, and a low-level mode control signal is output, that is, MODE=0, so that the control loop enters the ultra-light load mode, and then the sleep time detection module has near zero power consumption.

[0090] Secondly, the adaptive bias design of the bias loop comparison module, when in normal load mode, the bias loop comparison module uses a larger bias current to obtain a better response speed. When in ultra-light load mode, the bias loop comparison module uses a smaller bias current to obtain the lowest possible quiescent current consumption.

[0091] Finally, the inductor current is detected through the current zero-crossing detection module. In order to solve the problem of false reversal in the initial stage of inductor current discharge, the delay unit is used to shield the high-level first conduction signal in the initial stage of inductor current discharge, and the detection function of the circuit is delayed to start. An OR gate prevents the false reversal caused by VSW ringing from causing oscillation problems. The resistance value of the pseudo-resistor MN2 is set to be greater than the resistance value of MN1, forming a preset detection threshold greater than 0 to achieve early reversal and reduce the backflow of inductor current.

[0092] See also Figure 1 In some embodiments, the buck converter further includes an error amplification module, a soft start module, a feedback resistor array, a loop compensation module and a selection module; the output end of the error amplification module and the output end of the loop compensation module are both connected to the input end of the selection module; the output end of the selection module is connected to the negative input end of the bias loop comparison module.

[0093] Furthermore, the sleep time detection module is also used to send a mode control signal to the loop compensation module.

[0094] The loop compensation module is turned off when the mode control signal is low.

[0095] The soft start module is used to amplify the reference voltage selection signal according to the received first enable signal, and send the amplified reference voltage selection signal to the error amplification module until the voltage of the reference voltage selection signal is equal to the preset reference voltage.

[0096] The first enable signal EN_SS is provided externally. When the circuit is required to work, the external device will provide a signal EN_SS that changes from a high level to a low level.

[0097] The feedback resistor array is used to generate a feedback voltage signal according to the input voltage signal and send it to the error amplifier module.

[0098] The sleep time detection module is also used to send a mode control signal to the selection module and the error amplification module.

[0099] The error amplification module is used to generate an error amplification signal according to the feedback voltage signal and the reference voltage selection signal when the mode control signal is at a high level, and send it to the selection module; and is closed when the mode control signal is at a low level.

[0100] Among them, the feedback voltage signal is Figure 1 V FB , the reference voltage selection signal is Figure 1 V REF_SEL .

[0101] Specifically, the input signal of the error amplifier module EA is V FB and V REF_SEL , MODE is the mode control signal, I REF_EA is the bias current; when the circuit enters the ultra-light load mode, MODE=0, thereby turning off the error amplifier module EA.

[0102] The selection module is used to send the error amplification signal to the bias loop comparison module when the mode control signal is at a high level, and to send the second enable signal to the bias loop comparison module when the mode control signal is at a low level.

[0103] The error amplified signal here is the error amplified signal V after compensation by the loop compensation module. EA .

[0104] The selection module consists of an inverter and two gate circuits TG. The mode control signal is inverted twice and input into the first gate circuit, and is inverted once and output into the second gate circuit. The first gate circuit receives the error amplification signal and works when the mode control signal is at a high level. The error amplification signal is sent to the bias loop comparison module. The second gate circuit receives the second enable signal V REF2 When the mode control signal is at a low level, that is, when the loop compensation module and the error amplification module are both in a closed state, the second enable signal is sent to the bias loop comparison module to ensure the normal operation of the bias loop comparison module.

[0105] Furthermore, the buck converter also includes an inductor current sampling module.

[0106] The inductor current sampling module is connected in parallel with the inductor in the buck converter to generate an inductor sensing signal V according to the sampled inductor current value. SEN , and inputs the positive input of the bias loop comparison module.

[0107] The bias loop comparison module is specifically used to generate a bias comparison signal according to the inductance sensing signal, the error amplification signal and the first bias current, or to generate a bias comparison signal according to the inductance sensing signal, the second enable signal and the second bias current.

[0108] It is understandable that the above-mentioned error amplification module, soft start module, feedback resistor array, loop compensation module and inductor current sampling module are all inherent modules in the existing buck converter. The difference is that the present application adds circuit switching technology to the error amplification module and the loop compensation module, that is, in the ultra-light load mode, the error amplification module and the loop compensation module are turned off, effectively reducing the static current consumption of the buck converter under ultra-clear load.

[0109] At the same time, considering that the bias loop comparison module cannot be turned off, a selection module is added to ensure that the bias loop comparison module has normal input and output when the circuit enters the ultra-light load mode.

[0110] The circuit switching technology introduced in the modules of the existing buck converter in the above embodiment can realize the shutdown of some circuit modules in the ultra-light load mode without affecting the modules that need to work, thereby reducing the static current consumption.

[0111] See also Figure 8 and Fig. 9 In some embodiments, the present application also makes some improvements to the soft start module: the soft start module is also used to perform a shutdown operation when the voltage of the reference voltage selection signal is equal to a preset reference voltage.

[0112] The soft start module of the present application comprises a ramp voltage generating circuit, a self-closing soft start circuit and a reference voltage selector; the self-closing soft start circuit is Figure 8 The shaded part in the figure can be automatically closed after the buck converter system soft start is completed. The soft start module can be divided into three working stages: initial stage, ramp voltage generation stage, and completion stage.

[0113] In the initial stage, the first enable signal EN_SS of the soft start module is high, ENB is low, and ENA is high. Therefore, ENP_RAMP is low, and ENN_RAMP is high. At this time, the capacitor C_SS is discharged to zero potential through the MOS tube MN0. When the comparator enables ENP_RAMP at a low level, V_SS is zero potential and is less than the preset reference voltage V REF1 , so the comparator output B1 is low level, so the D flip-flop output A is high level, B is low level, at this time the reference voltage selection signal V REF_SEL=V_SS. In the ramp voltage generation stage, the first enable signal EN_SS becomes low level, then ENB is high level, ENA is low level, and the capacitor voltage V_SS is still less than the preset reference voltage V REF1 , so the comparator output B1 is still low, so the D flip-flop output A is high and B is low, therefore, ENP_RAMP becomes high and ENN_RAMP becomes low. At this time, the current IB_SS is proportionally reduced to charge the capacitor C_SS to generate a ramp voltage. At this time, the reference voltage selection signal is still V REF_SEL = V_SS. In the completion phase, when the capacitor voltage V_SS reaches the preset reference voltage V REF1 When the comparator output B1 turns to high level, then A turns to low level and B turns to high level. Therefore, ENP_RAMP is low level and ENN_RAMP is high level. After that, the comparator is turned off, MOS tube MN0 discharges the capacitor C_SS, and there is no current to charge the capacitor C_SS. The reference voltage selection signal V REF_SEL =V REF1 .

[0114] After the buck converter system soft-start is completed, the circuit can automatically control shutdown to minimize the power consumption of the soft-start circuit.

[0115] Specifically, when V_SS increases from zero to greater than or equal to VREF1, the comparator output B1 flips from a low level to a high level, and the rising edge of B1 causes the D flip-flop output Q to change from a low level to a high level, thereby shutting down the soft start module.

[0116] The soft start module in the above embodiment automatically controls to turn off the soft start circuit after the buck converter completes the soft start, so as to eliminate the static current consumption of the soft start circuit and further improve the conversion efficiency of the buck converter.

[0117] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A buck converter based on on-time control, characterized in that: include: A shortest time shutdown module, used for receiving a first conduction signal of a first switch tube, generating a shutdown signal when the first conduction signal is at a high level, and sending the shutdown signal to a logic control module; A conduction time generating module, used for receiving a second conduction signal of a second switch tube, generating a start signal when the second conduction signal is at a high level, and sending the start signal to a logic control module; A logic control module, configured to generate a first drive signal and a second drive signal based on the received shutdown signal, the startup signal and the bias comparison signal, and send the signals to the dead time control module and the sleep time detection module; a dead time control module, configured to generate a first conduction signal and a second conduction signal according to the first drive signal and the second drive signal, send the first conduction signal to the gate of the first switch tube and the shortest time shutdown module, and send the second conduction signal to the gate of the second switch tube and the conduction time generation module; a sleep time detection module, configured to generate a mode control signal based on the first drive signal and the second drive signal; Sending the mode control signal to the bias loop comparison module and the error amplification module respectively; A bias loop comparison module, configured to generate a bias comparison signal based on a first bias current and send the bias comparison signal to the logic control module when the mode control signal is at a high level, and to generate a bias comparison signal based on a second bias current and send the bias comparison signal to the logic control module when the mode control signal is at a low level; The second bias current is smaller than the first bias current.

2. The buck converter based on on-time control according to claim 1, characterized in that: It also includes an error amplification module, a soft start module, a feedback resistor array, a loop compensation module and a selection module; The output end of the error amplification module and the output end of the loop compensation module are both connected to the input end of the selection module; the output end of the selection module is connected to the negative input end of the bias loop comparison module; The soft start module is used to amplify the reference voltage selection signal according to the received first enable signal, and send it to the error amplification module until the voltage of the reference voltage selection signal is equal to the preset reference voltage; The feedback resistor array is used to generate a feedback voltage signal according to the input voltage signal and send it to the error amplification module; The sleep time detection module is also used to send a mode control signal to the selection module and the error amplification module; The error amplification module is used to generate an error amplification signal according to the feedback voltage signal and the reference voltage selection signal when the mode control signal is at a high level, and send the error amplification signal to the selection module; and is turned off when the mode control signal is at a low level; The selection module is used to send the error amplification signal to the bias loop comparison module when the mode control signal is at a high level, and to send the second enable signal to the bias loop comparison module when the mode control signal is at a low level.

3. The buck converter based on on-time control according to claim 2, characterized in that: The sleep time detection module is also used to send the mode control signal to the loop compensation module; The loop compensation module is used to be turned off when the mode control signal is at a low level.

4. The buck converter based on on-time control according to claim 2, characterized in that: The soft start module is further configured to perform a shutdown operation when the voltage of the reference voltage selection signal is equal to a preset reference voltage.

5. The buck converter based on on-time control according to claim 1, characterized in that: It also includes an inductor current sampling module; the inductor current sampling module is connected in parallel with the inductor in the buck converter, and is used to generate an inductor sensing signal according to the sampled inductor current value, and input the signal into the positive input terminal of the bias loop comparison module; The bias loop comparison module is specifically used to generate a bias comparison signal according to the inductance sensing signal, the error amplification signal and the first bias current, or to generate a bias comparison signal according to the inductance sensing signal, the second enable signal and the second bias current.

6. The buck converter based on on-time control according to claim 1, characterized in that: It also includes a current zero-crossing detection module; the dead time control module is also used to send the first conduction signal to the current zero-crossing detection module; The current zero-crossing detection module is used to receive the inductor voltage signal, generate a current detection signal according to the first conduction signal and the inductor voltage signal, and send the current detection signal to the logic control module; The logic control module is specifically configured to generate the first drive signal and the second drive signal according to the shutdown signal, the start signal, the current detection signal, and the offset comparison signal.

7. The buck converter based on on-time control according to claim 6, characterized in that: The current zero-crossing detection module includes a delay unit and a detection unit connected to each other; The delay unit is used to delay the first conduction signal and send it to the detection unit; The detection unit is used to determine whether the inductor voltage signal is lower than a preset detection threshold when the first conduction signal after delay is at a high level, and if so, output a high-level current detection signal, otherwise output a low-level current detection signal.

8. The buck converter based on on-time control according to claim 1, characterized in that: The sleep time detection module includes a counting unit, an oscillation control unit, an RC oscillation unit and a mode selection unit; The counting unit is used to generate a sleep signal according to the first drive signal and the second drive signal; count the received clock signal according to the sleep signal to obtain a first count value, a second count value and a third count value; The oscillation control unit is used to generate an initial control signal according to the first count value, the second count value and the third count value, and send it to the mode selection unit; and generate an oscillation control signal according to the initial control signal and the sleep signal of the counting unit, and send it to the RC oscillation unit; The RC oscillation unit is used to generate a clock signal according to the oscillation control signal and send it to the counting unit; The mode selection unit is configured to generate the mode control signal according to the sleep signal and the initial control signal.

9. The buck converter based on on-time control according to claim 8, characterized in that: The counting unit includes an XOR gate, a first inverter, a second inverter, a first counter, a second counter and a third counter; The input end of the XOR gate is used to receive the first drive signal and the second drive signal; The XOR gate, the first inverter and the second inverter are connected in sequence; the second inverter is used to output the sleep signal and send it to the reset ports of the first counter, the second counter and the third counter; The clock input terminal of the first counter is used to receive the clock signal, the data input terminal and the second output terminal are both connected to the clock input terminal of the second counter, and the first output terminal is used to output the first count value; The data input terminal and the second output terminal of the second counter are both connected to the clock input terminal of the third counter, and the first output terminal is used to output the second count value; the data input terminal and the second output terminal of the third counter are connected, and the first output terminal is used to output the third count value.

10. The buck converter based on on-time control according to claim 9, characterized in that: The oscillation control unit is specifically used to perform an AND operation on the first count value and the third count value to obtain a fourth count value; perform an AND operation on the second count value and the third count value to obtain a fifth count value; perform an OR operation on the third count value, the fourth count value and the fifth count value to obtain the initial control signal; and perform an AND operation on the initial control signal and the sleep signal to obtain the oscillation control signal.

11. The buck converter based on on-time control according to claim 9, characterized in that: The mode selection unit is specifically used to input the inverted sleep signal and the initial control signal into a D flip-flop to obtain a mode control signal.

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