Adaptive ripple compensation circuit of DC-DC converter applied to V2COT control

By introducing the DC component of the virtual inductor current and adaptively adjusting the ripple compensation signal in the COT mode DC-DC converter, the problem of insufficient system stability under low ESR capacitance load conditions is solved, and higher stability and transient response performance are achieved.

CN119906273APending Publication Date: 2025-04-29NANTONG UNIV
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Patent Information

Application Number
CN202510100120.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-01-22
Publication Date
2025-04-29

AI Technical Summary

Technical Problem

The COT mode DC-DC converter has the problem of insufficient system stability under low ESR capacitance load conditions, and the existing ripple compensation technology has limited effect under different input and output voltages and load conditions.

Method used

Adaptive ripple compensation circuit is adopted to optimize the ripple compensation effect by introducing the DC component of the virtual inductor current and adjusting the slope of the ripple compensation signal in real time, and combining the feedback information of the input voltage.

Benefits of technology

It significantly improves the stability and transient response performance of the system under different input and output voltages and load conditions, and enhances anti-interference ability and load adaptability.

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Abstract

The invention discloses a self-adaptive ripple compensation circuit of a DC-DC converter applied to V2COT control. The circuit comprises a power stage and a control loop, the power stage comprises an input voltage Vin, a switching tube MN1, a follow current tube MN2, an energy storage inductor L, a feedback capacitor Cf, an output capacitor Cout, resistors R11 and R12 and a load resistor RL; the control loop comprises a logic and driving module Logicamp; the circuit comprises a Driver, a constant on-time module OnTimer, a comparator CMP, a low-pass filter LPF, an error amplifier EA and a compensation circuit Compentation. According to the invention, under the condition that a low equivalent series resistance (ESR) capacitor is selected, the stability and transient response performance of the system under different input and output voltages and load jump conditions can be obviously improved.
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Description

Technical Field

[0001] The present invention belongs to the technical field of power supply management and voltage stabilization control, and more particularly to a method for applying V 2 Adaptive ripple compensation circuit for COT controlled DC-DC converter. Background Art

[0002] COT (constant on-time) mode DC-DC converters have been widely used in electronic systems due to their simple structure and fast transient response capability, especially in scenarios where the load changes rapidly. However, since the COT control mode usually relies on the ripple signal in the output voltage for control, when using ceramic capacitors with low equivalent series resistance (ESR), the ripple signal of the output voltage will be significantly reduced, making it difficult for the controller to maintain stable operation. This limitation makes the COT mode face the problem of insufficient system stability in applications with low ESR capacitor loads. Therefore, ripple compensation technology is particularly critical in COT mode DC-DC converters.

[0003] At present, common ripple compensation methods include feedforward capacitor compensation and virtual inductor current ripple injection. Feedforward capacitor compensation is a simple and practical method, and its circuit consists of only one capacitor. By reasonably setting the capacitance of the feedforward capacitor, the converter's noise resistance can be effectively improved, the edge jitter of the control signal can be reduced, and the requirements for the output capacitor ESR can be reduced, making the loop easier to achieve stability. Virtual inductor current ripple injection is a compensation technology commonly used in COT control mode. Its principle is to introduce a ripple signal of the virtual inductor current into the control loop to generate additional ripples, thereby enhancing the stability and dynamic response performance of the system and ensuring that the system can operate stably under low ESR conditions.

[0004] Although feedforward capacitors and virtual inductor current compensation can improve the ripple signal in COT mode, they still have certain limitations in terms of stability and transient response. The compensation effect of feedforward capacitor compensation may be significantly weakened when the input voltage, output voltage or load changes, so its improvement on system stability is relatively limited. Although virtual inductor current ripple injection optimizes the ripple compensation effect to a certain extent, its design is relatively complex, and when the load changes dynamically, the change trend of the virtual inductor current ripple is opposite to the change trend of the output voltage. This reverse change will cause part of the output voltage change to be offset by the ripple signal and cannot be fully sensed by the control loop, thus affecting the dynamic response performance of the system. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide an adaptive ripple compensation technology suitable for constant on-time (COT) control mode. The technology can significantly improve the stability and transient response performance of the system under different input and output voltages and load jump conditions when low equivalent series resistance (ESR) capacitors are selected.

[0006] Technical solution: A method of applying the present invention to V 2 The adaptive ripple compensation circuit of the DC-DC converter controlled by COT includes a power stage and a control loop; the power stage includes an input voltage V in 、Switch tube MN 1 、Freewheeling tube MN 2 , energy storage inductor L, feedback capacitor C f , output capacitor C out , resistor R 11 and R 12 And the load resistance R L The control loop includes a logic and driver module Logic&Driver, a constant on-time module On_Timer, a comparator CMP, a low-pass filter LPF, an error amplifier EA and a compensation circuit Compensation.

[0007] Furthermore, the input voltage V in The positive electrode and the switch tube MN 1 The drain of MN 1 The source and switch tube MN 2 The drains of the switches are connected to form a switch node LX, which is connected to the output node V through the energy storage inductor L. out ; Switching tube MN 1 The gate of the switch is connected to the output terminal VG_UP of the logic and driver module Logic&Driver, and the switch tube MN 2 The gate of MN is connected to the other output terminal VG_DN of the logic and driver module Logic&Driver; 2 The source is grounded, the input voltage V in The negative pole of is also grounded; the switch node LX is connected to the input terminal of the low-pass filter LPF to generate the output signal SW_AVG; the output node V out At the same time, connect the output capacitor C out and load resistance R L The output node feeds back the voltage to the feedback node V through the feedback resistor network. FB ; The feedback network consists of resistor R 11 and R 12 And the parallel feedback capacitor C f Composition, of which R 11 Connect the output node and the feedback node V FB, R 12 Connect the feedback node V FB and ground; feedback node voltage V FB Connect the inverting input of the error amplifier EA, the reference voltage V REF Connect to the non-inverting input of the error amplifier to generate the output signal V ea ; V FB Connect the inverting input of comparator CMP, V ea Connect the compensation circuit input terminal to generate the output signal V COMP , V COMP Connect to the non-inverting input of the comparator CMP, and the output of the comparator CMP generates T ON Signal, connected to the input end of the constant on-time module On_Timer, and the output end of the constant on-time module On_Timer is connected to the output end of the logic and driver module Logic&Driver.

[0008] Furthermore, the compensation circuit Compensation includes a resistor R, a capacitor C, an operational amplifier AMP, an inverter INV, a MOS tube and a trigger DFF.

[0009] Furthermore, the compensation circuit Compensation includes: a resistor R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 , R 8 ; Capacitor C 1 , C 2 , C 3 ; Operational amplifiers AMP1, AMP2, AMP 3 ; Inverters INV1, INV2; MOS tube M 1 、M 2 、M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 、M 11 、M 12 、M 13 、M 14 ; and trigger DFF; wherein the feedback node voltage VLX is connected to the resistor divider network R 1 and R 2 After voltage division, connect to resistor R 3 One end of the resistor R3 The other end is connected to the series resistor R 4 and R 5 , resistor R 3 , R 4 , R 5 The other end of the capacitor C 1 , C 2 , C 3 In parallel, capacitor C 1 , C 2 , C 3 The other end is grounded for filtering. The filtered signal V LX (dc) is connected to the positive input terminal of the operational amplifier AMP1, and the negative input terminal of AMP1 is connected to its output terminal to form negative feedback; the output terminal of AMP1 is connected to M 3 The gate, M 3 The drain is connected to the positive power supply V IN , whose source is connected through the resistor R 6 ground, while generating a current I 2 ; Positive power supply V IN Connect M 1 、M 2 The source, M 1 The gate connection M 2 The gate and drain of 3 The drain, M 2 The drain connection M 4 The source, M 4 The gate of DFF is connected to the output terminal Q, M 4 The source is connected through the resistor R 8 Ground, forming a compensation signal V COMP ; The positive input of AMP2 is connected to V O1 The negative input terminal is connected to the output terminal of AMP2 to form negative feedback. The output terminal of AMP2 is connected to M 9 The gate, M 9 The drain connection M 6 The drain of the 7 Grounded to form a voltage feedback signal; M 6 、M 7 、M 8 The source is connected to V IN , M 6 Gate connection M 7 、M 8 The gate, M 7 The drain connection M 10 The source, M 10 The gate is connected to VSS, the drain is grounded, and M 8 Missing connection M 12 、M 13 The gate and M12 The drain, M 12 、M 13 The source of M is grounded. 13 The drain connection M 11 、M 14 The drain of 11 The gate of the amplifier is connected to the input signal S, the source is connected to the output of the amplifier AMP3, and the positive input of the amplifier AMP3 is connected to V COMP , the negative input terminal is connected to the output terminal of AMP3; M 14 The source connection M 4 The drain, M 14 The gate of M is connected to the output end of the inverter INV2, and the input end of INV2 is connected to the input signal S; 5 The gate connection input signal V COMPLOCK , drain connected to V COMP , the source is grounded.

[0010] Furthermore, the enable terminal of the flip-flop DFF is connected to the input signal ENP, the set terminal is connected to the input signal S, and the input terminal is connected to the output terminal CP of the inverter INV1; the input terminal of the inverter is connected to the zero-crossing detection signal zcd.

[0011] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0012] The present invention is applicable to a DC-DC switching converter adopting a COT control mode, and is particularly applicable to scenarios with high requirements on stability and transient response performance, such as processor power supply modules, battery management systems, and power management of portable electronic devices, and other applications where dynamic loads change rapidly.

[0013] The present invention introduces a DC component of the virtual inductor current, which is insensitive to load changes and can provide a relatively stable signal, thereby helping to maintain the stability of the output voltage when the load jumps. Compared with the traditional method of directly introducing the inductor current ripple, the invention is less dependent on load changes, thereby maintaining a more consistent compensation effect under different load conditions.

[0014] The present invention makes full use of the real-time change information of the input voltage and adaptively adjusts the slope of the ripple compensation signal according to the fluctuation of the input voltage to dynamically optimize the compensation effect, thereby significantly enhancing the stability and transient response capability of the system. This compensation method based on dynamic adjustment of the input voltage enables the system to maintain excellent performance under various input and output conditions.

[0015] The present invention adds feedback to the input voltage: on the basis of the traditional feedback signal, the information of the input voltage is introduced to enhance the ripple compensation effect. By sensing the change of the input voltage in real time and dynamically adjusting the compensation signal, the system can maintain good ripple compensation performance under different input voltage conditions, thereby overcoming the compensation limitations of the traditional method under the condition of input voltage changes.

[0016] The present invention enhances the load adaptability of the system by introducing a DC component in the virtual inductor current, which is insensitive to load changes. When the load changes, the DC component can help maintain the stability of the output voltage and improve the ripple compensation effect under different output voltages. Even in the case of sudden load changes or different output voltages, the system can still remain stable and avoid large voltage fluctuations.

[0017] The compensation method of the present invention overcomes the limitation of the effect of traditional ripple compensation under different input and output voltage and load conditions, and significantly improves the anti-interference ability and dynamic response performance of the system. By optimizing the ripple compensation signal in the control loop, the present invention enables the COT mode to operate stably under complex input and output voltage and load environments. Furthermore, the technology allows the selection of low ESR capacitors to reduce the output voltage ripple, thereby optimizing the overall performance and cost-effectiveness of the system while ensuring stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a diagram of the overall circuit architecture of the present invention.

[0019] Figure 2 A practical circuit for ripple compensation.

[0020] Figure 3 This is the ripple compensation simulation diagram.

[0021] Figure 4 Figure 2 shows the graphs with and without ripple compensation, where (a) shows the graph with ripple compensation added and (b) shows the graph without ripple compensation added. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0023] The main object of the present invention is to provide a ripple compensation circuit method suitable for a constant on-time (COT) control mode.

[0024] It aims to solve the instability problem caused by insufficient ripple compensation effect in the traditional COT control mode when the load or input and output voltage changes.

[0025] To achieve the above objectives, the present invention constructs a stable ripple compensation mechanism by introducing the voltage DC component of the virtual inductor current and the input voltage information. This method can maintain high accuracy and system stability under different input and output voltages and load conditions, thereby significantly improving the dynamic response performance and anti-interference ability of the COT control mode.

[0026] Specific measures and technical features:

[0027] A V 2 COT controlled BUCK converter architecture, such as Figure 1 As shown in the V 2 The COT controlled BUCK converter architecture consists of two parts: the power stage and the control loop. The power stage includes the input voltage V in 、Switch tube MN 1 、Freewheeling tube MN 2 , energy storage inductor L, feedback capacitor C f , output capacitor C out , resistor R 11 and R 12 And the load resistance R L The control loop includes a logic and driver module Logic&Driver, a constant on-time module On_Timer, a comparator CMP, a low-pass filter LPF, an error amplifier EA and a compensation circuit Compensation;

[0028] Input voltage V in The positive electrode and the switch tube MN 1 The drain of MN 1 The source and switch tube MN 2 The drains of the switches are connected to form a switch node LX, which is connected to the output node V through the energy storage inductor L. out ; Switching tube MN 1 The gate of the switch is connected to the output terminal VG_UP of the logic and driver module Logic&Driver, and the switch tube MN 2 The gate of MN is connected to the other output terminal VG_DN of the logic and driver module Logic&Driver; 2 The source is grounded, the input voltage V in The negative pole of is also grounded; the switch node LX is connected to the input terminal of the low-pass filter LPF to generate the output signal SW_AVG; the output node V out At the same time, connect the output capacitor C out and load resistance R L The output node feeds back the voltage to the feedback node V through the feedback resistor network. FB ; The feedback network consists of resistor R 11 and R 12 And the parallel feedback capacitor Cf Composition, of which R 11 Connect the output node and the feedback node V FB , R 12 Connect the feedback node V FB and ground; feedback node voltage V FB Connect the inverting input of the error amplifier EA, the reference voltage V REF Connect to the non-inverting input of the error amplifier to generate the output signal V ea ; V FB Connect the inverting input of comparator CMP, V ea Connect the compensation circuit input terminal to generate the output signal V COMP , V COMP Connect to the non-inverting input of the comparator CMP, and the output of the comparator CMP generates T ON The signal is connected to the input end of the constant on-time module On_Timer, and the output end of the constant on-time module On_Timer is connected to the output end of the logic and driver module Logic&Driver.

[0029] The actual circuit diagram of the ripple compensation of the present invention is as follows: Figure 2 As shown, the circuit includes the following main components: resistor R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 , R 8 ; Capacitor C 1 , C 2 , C 3 ; Operational amplifiers AMP1, AMP2, AMP 3 ; Inverters INV1, INV2; MOS tube M 1 、M 2 、M 3 、M 4 、M 5 、M 6 、M 7 、M 8 、M 9 、M 10 、M 11 、M 12 、M 13 、M 14 ; and trigger DFF; wherein the feedback node voltage VLX is connected to the resistor divider network R 1 and R 2 After voltage division, connect to resistor R 3 One end of the resistor R 3The other end is connected to the series resistor R 4 and R 5 , resistor R 3 , R 4 , R 5 The other end of the capacitor C 1 , C 2 , C 3 In parallel, capacitor C 1 , C 2 , C 3 The other end is grounded for filtering. The filtered signal V LX (dc) is connected to the positive input terminal of the operational amplifier AMP1, and the negative input terminal of AMP1 is connected to its output terminal to form negative feedback; the output terminal of AMP1 is connected to M 3 The gate, M 3 The drain is connected to the positive power supply V IN , whose source is connected through the resistor R 6 ground, while generating a current I 2 ; Positive power supply V IN Connect M 1 、M 2 The source, M 1 The gate connection M 2 The gate and drain of 3 The drain, M 2 The drain connection M 4 The source, M 4 The gate of DFF is connected to the output terminal Q, M 4 The source is connected through the resistor R 8 Ground, forming a compensation signal V COMP ; The positive input of AMP2 is connected to V O1 The negative input terminal is connected to the output terminal of AMP2 to form negative feedback. The output terminal of AMP2 is connected to M 9 The gate, M 9 The drain connection M 6 The drain of the 7 Grounded to form a voltage feedback signal; M 6 、M 7 、M 8 The source is connected to V IN , M 6 Gate connection M 7 、M 8 The gate, M 7 The drain connection M 10 The source, M 10 The gate is connected to VSS, the drain is grounded, and M 8 Missing connection M 12 、M 13 The gate and M 12The drain, M 12 、M 13 The source of M is grounded. 13 The drain connection M 11 、M 14 The drain of 11 The gate of the amplifier is connected to the input signal S, the source is connected to the output of the amplifier AMP3, and the positive input of the amplifier AMP3 is connected to V COMP , the negative input terminal is connected to the output terminal of AMP3; M 14 The source connection M 4 The drain, M 14 The gate of M is connected to the output end of the inverter INV2, and the input end of INV2 is connected to the input signal S; 5 The gate connection input signal V COMPLOCK , drain connected to V COMP , the source is grounded.

[0030] Furthermore, the enable terminal of the flip-flop DFF is connected to the input signal ENP, the set terminal is connected to the input signal S, and the input terminal is connected to the output terminal CP of the inverter INV1; the input terminal of the inverter is connected to the zero-crossing detection signal zcd.

[0031] Through the error amplifier, the feedforward capacitor feedback voltage V FB and reference voltage V REF The difference is amplified to generate a signal Vea that is opposite to the inductor current phase. Subsequently, Vea is processed by the ripple compensation circuit to obtain a compensation signal V COMP , the compensation signal is compared with the feedback voltage. The constant on-time (COT) circuit generates a square wave signal that controls the on and off of the switch tube, thereby adjusting the output voltage to stabilize it at the target value. For the output voltage ripple, the transfer function from the output terminal to the feedback voltage terminal after passing through the feedforward capacitor can be expressed as:

[0032]

[0033] Feedforward capacitor C f The feedback voltage V FB An additional high-frequency path is introduced in the circuit, making the feedback network more sensitive to high-frequency ripple. Since the gain factor depends on the voltage divider ratio between the reference voltage and the output voltage, the feedforward capacitor compensation can only provide a very limited effect. Therefore, the present invention further adds a new compensation circuit based on the compensation mechanism, significantly enhancing the system's responsiveness and loop stability, so that it can work reliably under different input and output voltages and load conditions.

Claims

1. One type is applied to V 2 The adaptive ripple compensation circuit of the COT controlled DC-DC converter is characterized in that: The circuit includes a power stage and a control loop; the power stage includes an input voltage V in , switch tube MN1, freewheeling tube MN2, energy storage inductor L, feedback capacitor C f , output capacitor C out , resistor R 11 and R 12 And the load resistance R L The control loop includes a logic and driver module Logic&Driver, a constant on-time module On_Timer, a comparator CMP, a low-pass filter LPF, an error amplifier EA and a compensation circuit Compensation.

2. A method for applying V according to claim 1 2 The adaptive ripple compensation circuit of the COT controlled DC-DC converter is characterized in that: The input voltage V in The positive electrode of is connected to the drain of the switch tube MN1, the source of MN1 is connected to the drain of the switch tube MN2, and together they form a switch node LX, which is connected to the output node V through the energy storage inductor L. out The gate of the switch tube MN1 is connected to the output terminal VG_UP of the logic and driver module Logic&Driver, and the gate of the switch tube MN2 is connected to the other output terminal VG_DN of the logic and driver module Logic&Driver; the source of MN2 is grounded, and the input voltage V in The negative pole of is also grounded; the switch node LX is connected to the input terminal of the low-pass filter LPF to generate the output signal SW_AVG; the output node V out At the same time, connect the output capacitor C out and load resistance R L The output node feeds back the voltage to the feedback node V through the feedback resistor network. FB ; The feedback network consists of resistor R 11 and R 12 And the parallel feedback capacitor C f Composition, of which R 11 Connect the output node and the feedback node V FB , R 12 Connect the feedback node V FB and ground; feedback node voltage V FB Connect the inverting input of the error amplifier EA, the reference voltage V REF Connect to the non-inverting input of the error amplifier to generate the output signal V ea ; V FB Connect the inverting input of comparator CMP, V ea Connect the compensation circuit input terminal to generate the output signal V COMP , V COMP Connect to the non-inverting input of the comparator CMP, and the output of the comparator CMP generates T ON The signal is connected to the input end of the constant on-time module On_Timer, and the output end of the constant on-time module On_Timer is connected to the output end of the logic and driver module Logic&Driver.

3. A method for applying V according to claim 1. 2 The adaptive ripple compensation circuit of the COT controlled DC-DC converter is characterized in that: The compensation circuit Compensation includes a resistor R, a capacitor C, an operational amplifier AMP, an inverter INV, a MOS tube and a trigger DFF.

4. A method for applying V according to claim 3 2 The adaptive ripple compensation circuit of the COT controlled DC-DC converter is characterized in that: The compensation circuit Compensation includes: resistors R1, R2, R3, R4, R5, R6, R7, R8; capacitors C1, C2, C3; operational amplifiers AMP1, AMP2, AMP3; inverters INV1, INV2; MOS tubes M1, M2, M3, M4, M5, M6, M7, M8, M9, M 10 、M 11 、M 12 、M 13 、M 14 ; and trigger DFF; wherein the feedback node voltage VLX is connected to one end of the resistor R3 after being divided by the resistor divider network R1 and R2, the other end of the resistor R3 is connected to the series resistors R4 and R5, the other ends of the resistors R3, R4, and R5 are connected in parallel with the capacitors C1, C2, and C3, the other ends of the capacitors C1, C2, and C3 are grounded for filtering, and the filtered signal V LX (dc) is connected to the positive input of the operational amplifier AMP1, and the negative input of AMP1 is connected to its output to form a negative feedback; the output of AMP1 is connected to the gate of M3, and the drain of M3 is connected to the positive power supply V IN , its source is grounded through resistor R6, and current I2 is generated at the same time; the positive electrode of the power supply V IN Connect the sources of M1 and M2, the gate of M1 is connected to the gate of M2, the drain is connected to the drain of M3, the drain of M2 is connected to the source of M4, the gate of M4 is connected to the output terminal Q of DFF, and the source of M4 is grounded through resistor R8 to form a compensation signal V COMP ; The positive input of AMP2 is connected to V O1 The negative input terminal is connected to the output terminal of AMP2 to form a negative feedback. The output terminal of AMP2 is connected to the gate of M9. The drain of M9 is connected to the drain of M6. Its source is grounded through the resistor R7 to form a voltage feedback signal. The source of M6, M7, and M8 is connected to V IN , the gate of M6 is connected to the gates of M7 and M8, and the drain of M7 is connected to M 10 The source, M 10 The gate of M8 is connected to VSS, the drain is grounded, and the drain of M8 is connected to M 12 、M 13 The gate and M 12 The drain, M 12 、M 13 The source of M is grounded. 13 The drain connection M 11 、M 14 The drain of 11 The gate of the amplifier is connected to the input signal S, the source is connected to the output of the amplifier AMP3, and the positive input of the amplifier AMP3 is connected to V COMP , the negative input terminal is connected to the output terminal of AMP3; M 14 The source of M4 is connected to the drain of M4. 14 The gate of M5 is connected to the output of inverter INV2, and the input of INV2 is connected to the input signal S; the gate of M5 is connected to the input signal V COMPLOCK , drain connected to V COMP , the source is grounded.

5. A method for applying V according to claim 4 2 The adaptive ripple compensation circuit of the COT controlled DC-DC converter is characterized in that: The enable terminal of the flip-flop DFF is connected to the input signal ENP, the set terminal is connected to the input signal S, and the input terminal is connected to the output terminal CP of the inverter INV1; the input terminal of the inverter is connected to the zero-crossing detection signal zcd.