Delay chain circuit, voltage drop detection circuit, chip and electronic equipment

Abstract

The invention provides a delay chain circuit, a voltage drop detection circuit, a chip and electronic equipment, and belongs to the field of electronic circuits. The delay chain circuit comprises m stages of delay units, each stage of delay unit comprises an output end and n input ends, m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2; at least one input end of the ith-level delay unit is connected with the output end of the (i-1) th-level delay unit, and i is an integer greater than or equal to 2; the sensitivity of each stage of delay unit is adjustable, and each stage of delay unit comprises n delay branches which are connected in parallel; the n delay branches comprise at least one controllable delay branch, and the state of each controllable delay branch comprises an on state or an off state. By adjusting the sensitivity of the delay chain circuit, different load changes can be adapted, and the maximum voltage gain of a chip can be supported when a dynamic frequency reduction technology is used.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to a delay chain circuit, a voltage drop detection circuit, a chip and an electronic device. Background Art

[0002] The power supply voltage in the chip usually has a ripple characteristic: the voltage value fluctuates as the load changes. When the voltage value is less than the target voltage value, the transmission delay of the digital logic circuit in the chip will increase. If the voltage drop is too large, the timing of the digital logic circuit may not meet the requirements. In special cases, excessive voltage drop may also cause chip function errors. In order to avoid this situation, dynamic frequency reduction technology can be introduced. When the power supply voltage encounters a sudden voltage drop, if the voltage drop value exceeds the sensitivity of the voltage drop detection circuit, the voltage drop detection circuit outputs a droop signal and starts the dynamic frequency reduction technology to reduce the operating frequency of the digital logic circuit.

[0003] The voltage drop value in the chip is usually correlated with the load and has an unfixed characteristic, which makes the chip often unable to achieve the maximum voltage gain when using dynamic frequency reduction technology. Among them, the voltage gain refers to the difference between the lowest power supply voltage when dynamic frequency reduction technology is not enabled and when dynamic frequency reduction technology is enabled. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a delay chain circuit, a voltage drop detection circuit, a chip and an electronic device, which can adapt to different load changes by adjusting the sensitivity of the delay chain circuit and support the maximum voltage gain of the chip when using dynamic frequency reduction technology.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a delay chain circuit, comprising: n levels of delay units, each level of delay unit comprising an output terminal and k input terminals, n is an integer greater than or equal to 2, and k is an integer greater than or equal to 2; at least one input terminal of the i-th level delay unit is connected to the output terminal of the i-1-th level delay unit, and i is an integer greater than or equal to 2 and less than or equal to n; the sensitivity of each level of delay unit is adjustable, and each level of delay unit comprises k delay branches in parallel; the k delay branches comprise at least one controllable delay branch, and the state of each controllable delay branch comprises an on state or an off state.

[0007] In the above embodiment, the delay chain circuit of the above structure is adopted, so that the sensitivity of each level of delay unit is adjustable, and the sensitivity of the delay unit can be adjusted by changing the state of the controllable delay branch in each level of delay unit. By adjusting the sensitivity of the delay chain circuit, it is possible to adapt to different load changes and support the maximum voltage gain of the chip when using dynamic frequency reduction technology. At the same time, at least one input end of the i-th level delay unit is connected to the output end of the i-1-th level delay unit, so that the input signals of the k input ends of the 2nd to nth level delay units can include one of all the same, partially the same, and all different, so as to adapt to different scene needs.

[0008] In combination with a possible implementation manner of the embodiment of the first aspect, the k delay branches further include a fixed delay branch, and the fixed delay branch is connected in parallel with the at least one controllable delay branch.

[0009] In the above embodiment, by adopting two types of delay branches including a fixed delay branch and at least one controllable delay branch, the control difficulty can be reduced or the number of adjustments can be reduced under the premise of adjustable sensitivity.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, each controllable delay branch includes: a controllable device and a delay device; the controllable device and the delay device are connected in series; and the controllable device is used to control the state of the controllable delay branch.

[0011] In the above embodiment, the controllable device and the delay device are connected in series, so that the state of the controllable delay branch can be controlled by controlling the controllable device, which can reduce the complexity of the circuit and facilitate production.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the delay device includes: an inverter and an adjustable capacitor circuit; the output end of the inverter is connected to the first end of the adjustable capacitor circuit, the second end of the adjustable capacitor circuit is grounded, and the capacitance of the adjustable capacitor circuit is adjustable; the adjustable capacitor circuit is used to adjust the delay of the delay device.

[0013] In the above embodiment, by connecting the output side of the inverter to an adjustable capacitor circuit with adjustable capacitance, the delay of the delay device can be adjusted by adjusting the capacitance of the adjustable capacitor circuit, thereby reducing the complexity of the circuit and facilitating production and manufacturing.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, the controllable device includes a selector, and multiple controllable delay branches multiplex the same selector.

[0015] In the above embodiment, a selector can be selected to control the state of the controllable delay branch, and the effect of multiple inputs and a single output can be achieved by multiplexing the same selector, so as to achieve the effect of cost saving. In combination with a possible implementation of the first aspect, the input signals of the k input terminals of the first-stage delay unit are all the same, and the input signals of the k input terminals of the second to nth-stage delay units include some that are the same or all that are different.

[0016] In the above embodiment, the input signals of the k input terminals of the 2nd to nth delay units are partially the same or completely different, so that phase feedforward technology can be supported. For example, taking k=3 as an example, the first input signal of the three input signals can be the output signal of the previous delay unit, the second input signal can be the output signal of the previous 2-stage delay unit, and the third input signal can be the output signal of the previous 3-stage delay unit. By introducing the phase of the previous 2-stage or 3-stage delay unit (i.e., phase feedforward), the delay of the delay unit can be reduced, thereby increasing the operating frequency of the delay chain circuit.

[0017] In combination with a possible implementation manner of the first aspect embodiment, if k=3, i is greater than or equal to 4, the three input signals of the i-th delay unit include one of the following: the three input signals are all output signals of the i-1th delay unit; the first input signal of the three input signals is the output signal of the i-1th delay unit, the second input signal is the output signal of the i-1th delay unit, and the third input signal is the output signal of the i-2th delay unit; the first input signal of the three input signals is the output signal of the i-1th delay unit, the second input signal is the output signal of the i-2nd delay unit, and the third input signal is the output signal of the i-2nd delay unit; the first input signal of the three input signals is the output signal of the i-1th delay unit, the second input signal is the output signal of the i-2nd delay unit, and the third input signal is the output signal of the i-3rd delay unit.

[0018] In the above embodiment, if k=3 and i is greater than or equal to 4, the three input signals of the i-th delay unit may include one of the above four types, so that the delay of the delay unit can be adjusted by switching different connection methods according to the delay requirements to adapt to various scenarios.

[0019] In the second aspect, an embodiment of the present application also provides a voltage drop detection circuit, comprising: a delay chain circuit, m phase-detection circuits and a logic circuit as provided in any possible implementation manner of the embodiment of the first aspect above; the delay chain circuit is used to delay the clock input signal and output m delayed signals, where m is an integer greater than or equal to 1; each of the m phase-detection circuits is used to receive a delayed signal and the clock input signal, and compare the phase relationship between the received delayed signal and the clock input signal; the logic circuit is connected to each of the phase-detection circuits and each level of delay unit, and the logic circuit is used to adjust the delay of the delay unit in the delay chain circuit according to the phase relationship output by the m phase-detection circuits.

[0020] In a third aspect, an embodiment of the present application further provides a chip, comprising: a voltage drop detection circuit as provided in the embodiment of the second aspect above.

[0021] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a voltage drop detection circuit as provided in the embodiment of the second aspect above.

[0022] In a fifth aspect, an embodiment of the present application further provides an electronic device, characterized in that it comprises a chip provided in the embodiment of the third aspect mentioned above.

[0023] The technical effects that can be achieved by the embodiments of the second to fifth aspects mentioned above refer to the corresponding technical effects in the first aspect and will not be repeated here.

[0024] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0026] Figure 1 A schematic structural diagram of a delay chain circuit provided in an embodiment of the present application is shown.

[0027] Figure 2 A schematic structural diagram of a delay unit provided in an embodiment of the present application is shown.

[0028] Figure 3 A circuit diagram of a delay device provided in an embodiment of the present application is shown.

[0029] Figure 4a A first circuit schematic diagram of a delay unit provided in an embodiment of the present application is shown.

[0030] Figure 4b A second circuit schematic diagram of a delay unit provided in an embodiment of the present application is shown.

[0031] Figure 4c A third circuit schematic diagram of the delay unit provided in an embodiment of the present application is shown.

[0032] Figure 4d A fourth circuit schematic diagram of the delay unit provided in an embodiment of the present application is shown.

[0033] Figure 5a A first circuit schematic diagram of a delay chain circuit provided in an embodiment of the present application is shown.

[0034] Figure 5b A second circuit schematic diagram of the delay chain circuit provided in an embodiment of the present application is shown.

[0035] Figure 6 A waveform diagram showing the effect of a power supply voltage drop on the delay of a delay unit provided in an embodiment of the present application is shown.

[0036] Figure 7 A schematic diagram of the structure of a voltage drop detection circuit provided in an embodiment of the present application is shown.

[0037] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0039] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device.

[0040] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0041] In order to adapt to different load changes, the embodiment of the present application provides a delay chain circuit with adjustable delay sensitivity, based on which the maximum voltage gain of the chip when using the dynamic frequency reduction technology can be achieved. Among them, achieving the maximum voltage gain of the chip when using the dynamic frequency reduction technology can not only bring energy saving effects, but also extend the life of the chip and improve the stability of the control system.

[0042] The present application embodiment provides a delay chain circuit. Figure 1 The principle is explained. The delay chain circuit comprises: n-stage delay units, each stage of the delay unit comprises an output terminal and k input terminals, wherein n is an integer greater than or equal to 2, and k is an integer greater than or equal to 2. Figure 1 Only the case where the input signals of the k input terminals are the same is shown.

[0043] At least one input terminal of the i-th delay unit is connected to the output terminal of the i-1-th delay unit, where i is an integer greater than or equal to 2 and less than or equal to n. For example, the output terminal of the 1-th delay unit is connected to at least one input terminal of the 2-th delay unit, the output terminal of the 2-th delay unit is connected to at least one input terminal of the 3-th delay unit, and so on, the output terminal of the n-1-th delay unit is connected to at least one input terminal of the n-th delay unit.

[0044] The input signals of the k input terminals of the first-stage delay unit may all be the same, and the input signals of the k input terminals of the second-stage to n-stage delay units may all be the same, partially the same, or completely different. For example, in some scenarios, the input signals of the k input terminals of the second-stage to n-stage delay units may be partially the same or completely different.

[0045] In one possible implementation, for example, the input signals of the k input terminals of the first-level delay unit are all the same, and are all clock input signals (such as represented by clkin), the input signals of the k input terminals of the second-level delay unit may also be all the same, and are all output signals of the first-level delay unit, and so on, the input signals of the k input terminals of the n-th-level delay unit may also be all the same, and are all output signals of the n-1-th-level delay unit.

[0046] Assume that the n output signals corresponding to the n-stage delay unit are represented by ck[1], ck[2], ck[3]...ck[n-2], ck[n-1], ck[n] respectively, and assume that each stage of the delay unit includes 3 input terminals. Then the input signal of the second-stage delay unit may include the output signal ck[1] of the first-stage delay unit and the input signal clkin of the first-stage delay unit. The input signal of the third-stage delay unit may include ck[2], ck[1], clkin. The input signal of the i-th stage delay unit may include ck[i-1], ck[i-2], ck[i-3]. The input signal of the n-th stage delay unit may include ck[n-1], ck[n-2], ck[n-3].

[0047] The sensitivity of each delay unit is adjustable to adapt to different load changes and to support the maximum voltage gain of the chip when using dynamic frequency reduction technology.

[0048] The structure of each delay unit can be the same, such as Figure 2 As shown, each level of delay unit includes k delay branches connected in parallel, and the k delay branches include at least one controllable delay branch. The state of each controllable delay branch includes an on state or an off state. The sensitivity of the delay unit can be adjusted by controlling the state of the controllable delay branch in the delay unit, such as controlling it to be on state or off state.

[0049] In some implementations, all of the k delay branches are controllable delay branches; in other implementations, the k delay branches also include fixed delay branches. In this implementation, the k delay branches include two types of delay branches, namely, fixed delay branches and at least one controllable delay branch, and the fixed delay branch is connected in parallel with the at least one controllable delay branch. The fixed delay branch can only be in the on state relative to the controllable delay branch.

[0050] Each controllable delay branch includes: a controllable device and a delay device, and the controllable device and the delay device are connected in series. The fixed delay branch may only include a delay device. The controllable device is used to control the state of the controllable delay branch, and the state of the controllable delay branch can be turned on or off by controlling the controllable device.

[0051] In some possible implementations, the thresholds of the delay devices in each delay branch are different, so that different delays can be selected by simply selecting different delay branches, thereby reducing the difficulty of control. In some possible implementations, the thresholds of the delay devices in some delay branches may be different, and different delays can be selected by matching different delay branches.

[0052] The delay device may include an inverter. Optionally, the delay device may include an inverter with adjustable delay. In a possible implementation, Figure 3 As shown, the delay device may include: an inverter and an adjustable capacitor circuit; the output end of the inverter is connected to the first end of the adjustable capacitor circuit, the second end of the adjustable capacitor circuit is grounded, and the capacitance of the adjustable capacitor circuit is adjustable. The inverter includes a first transistor (which can be represented by P1) and a second transistor (which can be represented by N1). The adjustable capacitor circuit is used to adjust the delay of the delay device, and the adjustable capacitor circuit includes a plurality of parallel capacitor branches, each capacitor branch including a switch and a capacitor connected in series. The capacitance of the capacitor can be adjusted by controlling the on or off of the switch, that is, the delay of the adjustable delay unit. The capacitance of the capacitor contained in each capacitor branch can be different.

[0053] The adjustable capacitance circuits in different stages of delay units can be controlled by the same control signal (such as ctrl), so that the control principle of the adjustable capacitance circuit in each stage of delay unit is the same.

[0054] In some possible implementations, the schematic diagram of the adjustable capacitor circuit may not be limited to Figure 3 As shown, for example, the capacitance of the adjustable capacitor circuit can be selected by a selector, in which case the adjustable capacitor circuit includes a plurality of capacitor branches connected in parallel, each capacitor branch shares a selector, and each capacitor branch can only include a capacitor. The capacitance of the capacitor included in each capacitor branch can be different.

[0055] In some possible implementations, the controllable device may include a switch. In this case, each controllable delay branch includes: a switch and a delay device. The corresponding principle example diagram may be as shown in FIG. Figure 4a shown. Figure 4a In the figure, inv1, inv2, and inv3 can be delay-adjustable inverters with three different threshold voltages. s1, s2, and s3 are switches that control inv1, inv2, and inv3, respectively. When s1 = 1, it indicates that switch s1 is closed; when s1 = 0, it indicates that switch s1 is open. Assume that the threshold of inv1 is V th1 , the threshold of inv2 is V th2 , the threshold of inv3 is V th3 . And satisfy the following relationship: V th1 <V th2 <V th3If s3=0, s2=0, s1=1, the equivalent threshold value V th Approximately equal to V th1 If s3=0, s2=1, s1=1, the equivalent threshold value V th Between V th1 and V th2 If s3=1, s2=1, s1=0, the equivalent threshold value V th Between V th2 and V th3 In this way, by controlling the switch, the threshold of the delay unit can be adjusted, and then the delay sensitivity of the delay unit can be adjusted.

[0056] In some possible implementations, when the k-way delay branch includes a fixed delay branch and a controllable delay branch, the corresponding schematic diagram may be as follows: Figure 4b shown.

[0057] In some possible implementations, the controllable device may include a selector (which may be a multiple-input single-output selector), and multiple controllable delay branches multiplex the same selector. The corresponding schematic diagram is as follows: Figure 4c In some possible implementations, Figure 4c The schematic diagram shown can also be transformed into Figure 4d shown.

[0058] in, Figure 4a , Figure 4b , Figure 4c In the example, inv0, inv1, inv2, and inv3 all represent inverters with adjustable delay. In some possible implementations, Figure 4a , Figure 4b , Figure 4c inv0 in. Figure 4a , Figure 4b , Figure 4c Only the case where the delay unit includes three delay branches is shown, and the number of delay branches may be greater than three.

[0059] The control of the controllable device and the adjustable capacitor circuit in the delay unit can be controlled by the same control device or by different control devices. For example, in some embodiments, the controllable device in the delay unit is controlled by a first control device, and the control of the adjustable capacitor circuit in the delay unit is controlled by a second control device.

[0060] In one possible implementation, the schematic diagram of the delay chain circuit can be as follows: Figure 5a , Figure 5b shown. Figure 5aThe circuit shown has six working modes: Mode 1: s1=0, s2=0, s3=1; Mode 2: s1=0, s2=1, s3=0; Mode 3: s1=0, s2=1, s3=1; Mode 4: s1=1, s2=0, s3=0; Mode 5: s1=1, s2=0, s3=1; Mode 6: s1=1, s2=1, s3=1. Figure 5b In the circuit shown, there are three working modes of the circuit: Mode 1: s2 = 0, s3 = 0; Mode 2: s2 = 1, s3 = 0; Mode 3: s2 = 1, s3 = 1. Due to different application scenarios, the required delay is also different. The sensitivity of the delay unit can be adjusted by switching different delay branches to adapt to various scenarios.

[0061] When controlling the delay circuits in different stages of delay units, the control signals can be the same. For example, when controlling switches in delay units, such as s1, s2, and s3, the switches controlled by each stage of delay units are the same, so that the delay units present the same structure. For example, the switches in different stages of delay units can be controlled by the same control signal (such as ctrl2).

[0062] exist Figure 5a , Figure 5b In the example shown, if k=3 and i is greater than or equal to 4, the three input signals of the i-th delay unit include one of the following:

[0063] i. The three input signals are all the output signals ck[i-1] of the i-1th delay unit;

[0064] ii. The first input signal (in1) of the three input signals is the output signal ck[i-1] of the i-1th delay unit, the second input signal (in2) is the output signal ck[i-1] of the i-1th delay unit, and the third input signal (in3) is the output signal ck[i-2] of the i-2th delay unit;

[0065] iii. The first input signal of the three input signals is the output signal ck[i-1] of the i-1th delay unit, the second input signal is the output signal ck[i-2] of the i-2th delay unit, and the third input signal is the output signal ck[i-2] of the i-2th delay unit;

[0066] iv. The first input signal of the three input signals is the output signal ck[i-1] of the i-1th delay unit, the second input signal is the output signal ck[i-2] of the i-2nd delay unit, and the third input signal is the output signal ck[i-3] of the i-3rd delay unit.

[0067] By introducing the phase of the first 2 or 3 delay units (i.e., phase feedforward), the delay of the delay unit can be reduced, thereby increasing the operating frequency of the delay chain circuit. Figure 5a , Figure 5b Only case iv among the above four cases is shown. In practical applications, the connection method of in1, in2, and in3 can be adjusted according to system indicators. The connection methods include but are not limited to:

[0068] Connection method ①: The three inputs in1, in2, and in3 of the i+1th level delay unit are connected to clk[i], clk[i], and clk[i] respectively.

[0069] Connection method ②: The three inputs in1, in2, and in3 of the i+1th level delay unit are connected to clk[i], clk[i], and clk[k-1] respectively.

[0070] Connection method ③: The three inputs in1, in2, and in3 of the i+1th level delay unit are connected to clk[i], clk[k-1], and clk[k-1] respectively.

[0071] Connection method ④: The three inputs in1, in2, and in3 of the i+1th level delay unit are connected to clk[i], clk[k-1], and clk[k-2] respectively.

[0072] In one implementation, when designing the delay chain circuit, one of the above four connection modes can be selected as needed, and the connection mode will not change after the connection. In order to support flexible connection modes, switches or selectors can be added before the k-1 input terminals of the second to nth delay units to select the desired connection mode. For example, taking k=3, a switch is added before the second input terminal in2 and the third input terminal in3 of the second-stage delay unit. Since the input signals of in2 and in3 can be ck[1] and clkin, in2 and in3 can be connected to both the output of the first-stage delay unit (i.e., ck[1]) and the input of the first-stage delay unit (i.e., clkin). Switches can be set on these two lines to select the input signal by controlling the switches.

[0073] by Figure 5a As an example, assume that the circuit operates in mode 4: s1 = 1, s2 = 0, s3 = 0. The circuit schematic diagram at this time can be as follows Figure 5b As shown. When the delay chain circuit is stable (no need to adjust the capacitor), the delay of the delay unit is proportional to the clock period. If the number of delay units is n, then the delay of each level of delay unit is: for Figure 3 The delay device shown, Where C L is the load capacitance, VDD is the supply voltage, μ is the electron mobility, Cox is the device gate capacitance, and Vth is the threshold voltage of the transistor.

[0074] Differentiate VDD in the above formula (2):

[0075]

[0076] Simplifying formula (3) we can get According to formula (4), the sensitivity coefficient It can be seen from the sensitivity coefficient formula that reducing VDD or increasing Vth can improve the sensitivity of the delay unit.

[0077] When the power supply voltage drops by ΔVDD, the impact on the delay unit can be seen in Figure 6 As shown in the figure, it can be seen that when the power supply voltage decreases, the sensitivity of the delay unit decreases, and the delay time increases accordingly, where td1 is the delay of the delay unit corresponding to VDD, and td2 is the delay of the delay unit corresponding to VDD-ΔVDD. Therefore, by switching different delay circuits, the sensitivity of the delay unit can be adjusted, and then the delay can be adjusted.

[0078] The delay chain circuit provided in the embodiment of the present application can be used in digital circuit design to accurately control the delay of the circuit, can also be used in clock synchronization circuits, and can also be used in scenarios such as voltage drop detection circuits.

[0079] The present application also provides a voltage drop detection circuit. Figure 7 As shown, the voltage drop detection circuit includes the above-mentioned delay chain circuit, m phase detection circuits and a logic circuit.

[0080] The delay chain circuit is used to delay the clock input signal clkin and output m delayed signals, where m is an integer greater than or equal to 1. Theoretically, the delay chain circuit can output n delayed signals, which can be represented as ck[1], ck[2], ck[3]...ck[n-2], ck[n-1], ck[n] respectively. Since the number of phase-detection circuits is m, it is only necessary to output m delayed signals to the m phase-detection circuits.

[0081] Each of the m phase-detection circuits is used to receive a delayed signal and a clock input signal (as a reference signal), and compare the phase relationship between the received delayed signal and the clock input signal. The m phase-detection circuits correspond to the m delayed signals output by the delay chain circuit one by one, and each phase-detection circuit receives a different delayed signal. The phase-detection circuit can adopt a circuit used in the related art to detect the phase relationship between two input signals.

[0082] The logic circuit is connected to each phase detection circuit and each stage of the delay unit, and the logic circuit is used to adjust the delay of the delay unit in the delay chain circuit according to the phase relationship output by the m phase detection circuits. When adjusting the delay of the delay unit in the delay chain circuit, it can be adjusted according to only one phase relationship among the m phase relationships, that is, one phase relationship can be selected from the m phase relationships to adjust, for example, the phase relationship corresponding to the last delay signal ck[n] can be selected to adjust.

[0083] The logic circuit may be a logic circuit with a control function, such as a decoder or a state machine. In some possible implementations, the above logic circuit may also be a control circuit.

[0084] During adjustment, the desired delay may be achieved through multiple adjustments, and a control signal may be output according to the selected phase relationship to control the capacitance of each delay branch in each delay unit. For example, Figure 3 The state of the switch of the branch where the capacitor is located. The minimum adjustment step (such as the minimum control word) can be increased or decreased each time the adjustment is made, and the required delay can be achieved after multiple adjustments.

[0085] The phase relationship may include two types: lag and lead. If the comparison result is 1, it means that the phase of the delayed signal is ahead of the phase of the clock input signal. If the comparison result is 0, it means that the phase of the delayed signal is behind the phase of the clock input signal. The opposite can also be expressed. When controlling the capacitance of each delay branch in each level of delay unit according to the phase relationship, if the initial comparison result is 0, it means that the phase of the delayed signal is behind the phase of the clock input signal. At this time, the total delay of the delay chain circuit is greater than 1 clock cycle (the clock cycle of clkin). The total delay of the delay chain circuit can be reduced by reducing the capacitance value until the comparison result is 1 and the capacitance of the delay chain circuit is stopped. On the contrary, if the initial comparison result is 1, the total delay of the delay chain circuit is less than 1 clock cycle. The total delay of the delay chain circuit can be increased by increasing the capacitance value until the comparison result is 0 and the capacitance of the delay chain circuit is stopped.

[0086] After the negative feedback loop of the voltage drop detection circuit is stable, if the power supply voltage drops, the sensitivity of the delay chain circuit will be reduced accordingly, thereby increasing the delay. If the voltage drop value exceeds the sensitivity of the voltage drop detection circuit, the logic circuit can also output a droop signal (droopdetcted) to start the dynamic frequency reduction technology.

[0087] When studying this application, the inventor found that if the sensitivity of the voltage drop detection circuit is slightly smaller than the voltage drop value, the voltage gain of the chip is the largest when using the dynamic frequency reduction technology. Due to different application scenarios, the corresponding loads are also different. When the voltage drop detection circuit shown in this application is applied to a specific scenario, the corresponding load is fixed. For this specific scenario, the voltage gain of the voltage drop detection circuit at each sensitivity can be tested, and then the sensitivity with the largest voltage gain can be selected. After that, during use, there is no need to adjust the sensitivity of the voltage drop detection circuit.

[0088] The sensitivity of the voltage drop detection circuit is related to the sensitivity of the delay chain circuit. The sensitivity can be changed by adjusting the state of the controllable delay branch in the delay chain circuit.

[0089] Voltage drop detection circuit The embodiment of the present application also provides a chip, which may include the above-mentioned voltage drop detection circuit. In some embodiments, the chip may be a chip with various specific voltage drop detection functions, including but not limited to a processor chip. The processor chip may be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence), an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a data processing core of a DSP (Digital Signal Processor), etc., or may be a processor chip used in some large-scale data computing and other scenarios. The above is only an example and should not be a limitation to the present application.

[0090] The chip provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned voltage drop detection circuit embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference may be made to the corresponding contents in the aforementioned voltage drop detection circuit embodiment.

[0091] An embodiment of the present application further provides an electronic device, which may include the above-mentioned voltage drop detection circuit. In some possible implementations, the electronic device may also include the above-mentioned chip.

[0092] When the chip is a processor, in some possible implementations, such as Figure 8 As shown, Figure 8The structure block diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device comprises: a transceiver, a memory, a communication bus and a processor.

[0093] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store computer programs, software function modules or data, and the processor is used to execute the software function modules or computer programs stored in the memory.

[0094] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0095] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processor (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application may be implemented or executed. Or the processor may also be any conventional processor, etc.

[0096] Among them, the above-mentioned electronic devices include but are not limited to mobile phones, tablets, computers, servers, etc.

[0097] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0098] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0099] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A delay chain circuit, characterized in that: include: n-stage delay units, each stage of the delay unit comprises an output terminal and k input terminals, n is an integer greater than or equal to 2, and k is an integer greater than or equal to 2; At least one input terminal of the i-th delay unit is connected to the output terminal of the i-1-th delay unit, where i is an integer greater than or equal to 2 and less than or equal to n; The sensitivity of each level of delay unit is adjustable, and each level of delay unit includes k delay branches connected in parallel; the k delay branches include at least one controllable delay branch, and the state of each controllable delay branch includes an on state or an off state.

2. The delay chain circuit according to claim 1, characterized in that: The k delay branches further include a fixed delay branch, and the fixed delay branch is connected in parallel with the at least one controllable delay branch.

3. The delay chain circuit according to claim 1, characterized in that: Each controllable delay branch includes: a controllable device and a delay device; the controllable device and the delay device are connected in series; The controllable device is used to control the state of the controllable delay branch.

4. The delay chain circuit according to claim 3, characterized in that: The delay device comprises: An inverter and an adjustable capacitor circuit; the output end of the inverter is connected to the first end of the adjustable capacitor circuit, the second end of the adjustable capacitor circuit is grounded, and the capacitance of the adjustable capacitor circuit is adjustable; The adjustable capacitance circuit is used to adjust the delay of the delay device.

5. The delay chain circuit according to claim 3, characterized in that: The controllable device includes a selector, and multiple controllable delay branches multiplex the same selector.

6. The delay chain circuit according to any one of claims 1 to 5, characterized in that: The input signals of the k input terminals of the first-stage delay unit are all the same, and the input signals of the k input terminals of the second-stage to n-stage delay units are partially the same or completely different.

7. The delay chain circuit according to claim 6, characterized in that: If k=3 and i is greater than or equal to 4, the three input signals of the i-th delay unit include one of the following: The three input signals are all output signals of the i-1th stage delay unit; The first input signal of the three input signals is the output signal of the i-1th delay unit, the second input signal is the output signal of the i-1th delay unit, and the third input signal is the output signal of the i-2th delay unit; The first input signal of the three input signals is the output signal of the i-1th delay unit, the second input signal is the output signal of the i-2th delay unit, and the third input signal is the output signal of the i-2th delay unit; The first input signal of the three input signals is the output signal of the i-1th delay unit, the second input signal is the output signal of the i-2nd delay unit, and the third input signal is the output signal of the i-3rd delay unit.

8. A voltage drop detection circuit, characterized in that: include: The delay chain circuit according to any one of claims 1 to 7, wherein the delay chain circuit is used to delay a clock input signal and output m delayed signals, where m is an integer greater than or equal to 1; m phase detector circuits, each of which is used to receive a delayed signal and the clock input signal, and compare the phase relationship between the received delayed signal and the clock input signal; A logic circuit is connected to each of the phase detection circuits and each level of delay unit, and the logic circuit is used to adjust the delay of the delay unit in the delay chain circuit according to the phase relationship output by the m phase detection circuits.

9. A chip, characterized in that: include: The voltage drop detection circuit as claimed in claim 8.

10. An electronic device, characterized in that: include: A voltage drop detection circuit as claimed in any one of claims 1 to 8.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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