Parallel circuit architecture of multi-phase power level chip, circuit board and electronic equipment

Abstract

The invention discloses a parallel circuit architecture of a multi-phase power level chip, a circuit board and electronic equipment, and relates to the technical field of electronic circuits. And when it is detected that the current of the target current detection end is greater than the current of the other current detection ends, reducing the duty ratio of the target pulse signal, so that the current of each power level chip is the same. And when the current of the target current detection end is detected to be smaller than the current of the other current detection ends, the duty ratio of the target pulse signal is too low, so that the duty ratio of the target pulse signal is increased, and the current of each power level chip is the same. Therefore, the output current of each power level chip connected in parallel can be the same to ensure the stability and the service life of the circuit, and one pulse signal can control a plurality of power level chips, so that the pins of the main control module can be saved.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a parallel circuit architecture of a multi-phase power stage chip, a circuit board and an electronic device. Background Art

[0002] A power stage chip is a chip with temperature detection, current detection, current balancing and driving. Power stage chips are commonly used to power GPUs and CPUs and are used in servers and AI.

[0003] In the related technology, the power stage chip is responsible for the voltage conversion output, and multiple power stage chips in parallel have the characteristics of high conversion efficiency, high integration, large current, and high frequency. In scenarios that require high power and high efficiency, such as industrial motor drives, electric vehicles, charging piles, and UPS (uninterruptible power supplies), multiple power stage chips need to be used in parallel. In order to ensure the consistency of the drain current of the parallel power stage chips in the on state and switching transient state, and to avoid static and dynamic uneven current problems caused by uneven current distribution, the output current of each power stage chip needs to be the same.

[0004] However, in the current parallel circuit architecture of multi-phase power stage chips, when multiple power stage chips are connected in parallel, the output currents of the power stage chips are different, resulting in reduced circuit stability and circuit life. Summary of the invention

[0005] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a parallel circuit architecture of multi-phase power stage chips, a circuit board and an electronic device, which can make the output current of each parallel power stage chip the same to ensure the stability and service life of the circuit.

[0006] According to the first aspect of the present application, a parallel circuit architecture of a multi-phase power stage chip includes:

[0007] A main control module, wherein the main control module is provided with a plurality of current detection terminals and a plurality of pulse output terminals, and the number of the current detection terminals corresponds one to one with the number of the pulse output terminals;

[0008] A plurality of current modules, and the current detection terminals correspond to the current modules one by one; each of the current modules includes a plurality of power-level chips, and the number of the pulse output terminals is equal to the number of the power-level chips in one of the current modules; the control terminal of each power-level chip in the current module is connected to the pulse output terminal one by one;

[0009] The current detection end is connected to a current detection pin of a power stage chip in the corresponding current module; and the pulse output end connected to the power stage chip connected to the current detection end in each current module is different;

[0010] The main control module is used for:

[0011] The pulse output terminals respectively output pulse signals, and the current of the correspondingly connected power stage chips is detected through the current detection terminals;

[0012] When it is detected that the current of the target current detection terminal is greater than the current of the other current detection terminals, reducing the duty cycle of the pulse signal of the pulse output terminal connected to the power stage chip connected to the target current detection terminal;

[0013] When it is detected that the current of the target current detection terminal is less than the current of the remaining current detection terminals, the duty cycle of the pulse signal of the pulse output terminal connected to the power stage chip connected to the target current detection terminal is increased.

[0014] According to the parallel circuit architecture of the multi-phase power stage chip of the first aspect of the present application, at least the following beneficial effects are possessed: in the circuit architecture of the embodiment of the present application, each current module is connected in parallel, and each power stage chip in the current module is connected in parallel. The pulse output end of the main control module outputs a pulse signal. Since the control end of each power stage chip in the current module is connected to the pulse output end in a one-to-one correspondence, each power stage chip in the current module corresponds to the pulse signal in a one-to-one correspondence. The current detection end is connected to the current detection pin of a power stage chip in the corresponding current module; and the pulse output end connected to the power stage chip connected to the current detection end in each current module is different. The target current detection terminal is any one of the multiple current detection terminals. When it is detected that the current of the target current detection terminal is greater than the current of the remaining current detection terminals, it means that the output current of the power level chip connected to the target current detection terminal is greater than the current of the remaining power level chips, and the current is mainly related to the duty cycle of the pulse signal, that is, the duty cycle of the pulse signal connected to the power level chip connected to the target current detection terminal is too high, the target pulse signal is the pulse signal connected to the power level chip connected to the target current detection terminal, and the current of each power level chip connected to the target pulse signal is too high, therefore, the duty cycle of the target pulse signal is reduced to make the current of each power level chip the same. When it is detected that the current of the target current detection terminal is less than the current of the remaining current detection terminals, it means that the duty cycle of the target pulse signal is too low, therefore, the duty cycle of the target pulse signal is increased to make the current of each power level chip the same. In this way, the output currents of the power level chips connected in parallel can be made the same to ensure the stability and service life of the circuit, and in this application, one pulse signal can control multiple power level chips, which can save the pins of the main control module.

[0015] According to some embodiments of the first aspect of the present application, the main control module includes a plurality of first signal processing sub-circuits, and the first signal processing sub-circuits correspond one-to-one to the pulse output terminals;

[0016] The first signal processing subcircuit includes a first transconductance operational amplifier, a first resistor, a second resistor, a third resistor, a first current source and a first signal processing unit, wherein the positive input terminal of the first transconductance operational amplifier is grounded through the first resistor, and the positive input terminal of the first transconductance operational amplifier and the first resistor serve as the first current input terminal of the first signal processing subcircuit, and the first current input terminal is connected to each of the current detection terminals; the negative input terminal of the first transconductance operational amplifier is grounded through the second resistor, and the negative input terminal of the first transconductance operational amplifier and the second resistor serve as the second current input terminal of the first signal processing subcircuit, and the second current input terminal is connected to the target current detection terminal; the output terminal of the first transconductance operational amplifier is grounded through the third resistor; the output terminal of the first current source and the voltage input terminal of the first signal processing unit are connected between the third resistor and the output terminal of the first transconductance operational amplifier, and the output terminal of the first signal processing unit serves as the pulse output terminal corresponding to the target current detection terminal, and the signal input terminal of the first signal processing unit is connected to the signal output terminal of the first signal processing unit;

[0017] The first signal processing unit is used to increase or decrease a duty cycle of an output signal of a signal output terminal of the first signal processing unit based on a voltage of the third resistor.

[0018] According to some embodiments of the first aspect of the present application, the first signal processing unit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, and a fourth resistor, the gate of the first field effect transistor serves as a signal input end of the first signal processing unit, the gate of the first field effect transistor is connected to the gate of the second field effect transistor, the drain of the first field effect transistor is connected to the drain of the second field effect transistor, and the source of the second field effect transistor is grounded; one end of the fourth resistor is connected to the source of the first field effect transistor, and the other end serves as a voltage input end of the first signal processing unit; one end of the first capacitor is connected to the drain of the second field effect transistor, and the other end is grounded; the gate of the third field effect transistor is connected to the gate of the second field effect transistor, the source of the third field effect transistor is grounded, the source of the third field effect transistor is connected to the drain of the second field effect transistor, the gate of the fourth field effect transistor, and the gate of the fifth field effect transistor, the source of the fourth field effect transistor is grounded, the drain of the fourth field effect transistor is connected to the drain of the fifth field effect transistor, and the source of the fifth field effect transistor is connected to the supply voltage.

[0019] According to some embodiments of the first aspect of the present application, the first signal processing unit further includes a first selector, wherein a first input end of the first selector is connected to the drain of the fourth field effect transistor; a second input end of the first selector is connected to the gate of the first field effect transistor, the first selector is further connected to an external control signal, and an output end of the first selector serves as a signal output end of the first signal processing unit;

[0020] When the external control signal is at a low level, the signal at the output end of the first selector is the signal at the first input end;

[0021] When the external control signal is at a high level, the signal at the output terminal of the first selector is the signal at the second input terminal.

[0022] According to some embodiments of the first aspect of the present application, the current module includes a plurality of second signal processing sub-circuits, and the plurality of second signal processing sub-circuits correspond one-to-one to the power stage chips in the current module; the second signal processing sub-circuit includes:

[0023] The second signal processing subcircuit includes a second transconductance operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second current source, and a second signal processing unit. The positive input terminal of the second transconductance operational amplifier is grounded through the fifth resistor, and the positive input terminal of the first transconductance operational amplifier and the fifth resistor are used as the first current input terminal of the second signal processing subcircuit, and the first current input terminal is connected to the current detection pin of each power stage chip in the current module; the reverse input terminal of the second transconductance operational amplifier is grounded through the sixth resistor, and the reverse input terminal of the second transconductance operational amplifier and the sixth resistor are used as the second current input terminal of the second signal processing subcircuit, and the second current input terminal is connected to the current detection pin of the corresponding power stage chip; the output terminal of the second transconductance operational amplifier is grounded through the seventh resistor; the output terminal of the second current source and the voltage input terminal of the second signal processing unit are connected between the seventh resistor and the output terminal of the second transconductance operational amplifier, and the output terminal of the second signal processing unit is used as the pulse output terminal corresponding to the target current detection terminal, and the signal input terminal of the second signal processing unit is connected to the signal output terminal of the second signal processing unit;

[0024] The second signal processing unit is used to increase or decrease a duty cycle of an output signal of a signal output terminal of the second signal processing unit based on a voltage of the seventh resistor.

[0025] According to some embodiments of the first aspect of the present application, the second signal processing unit includes a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, and an eighth resistor, the gate of the sixth field effect transistor serves as a signal input end of the first signal processing unit, the gate of the sixth field effect transistor is connected to the gate of the seventh field effect transistor, the drain of the sixth field effect transistor is connected to the drain of the seventh field effect transistor, and the source of the seventh field effect transistor is grounded; one end of the eighth resistor is connected to the source of the sixth field effect transistor, and the other end serves as a voltage input end of the first signal processing unit; one end of the first capacitor is connected to the drain of the seventh field effect tube, and the other end is grounded; the gate of the eighth field effect tube is connected to the gate of the seventh field effect tube, the source of the eighth field effect tube is grounded, the source of the eighth field effect tube is connected to the drain of the seventh field effect tube, the gate of the ninth field effect tube, and the gate of the tenth field effect tube, the source of the ninth field effect tube is grounded, the drain of the ninth field effect tube is connected to the drain of the tenth field effect tube, and the source of the tenth field effect tube is connected to the supply voltage.

[0026] According to some embodiments of the first aspect of the present application, the resistance of the second resistor is N times the resistance of the first resistor, where N is the number of the current detection terminals.

[0027] According to some embodiments of the first aspect of the present application, the resistance of the sixth resistor is X times the resistance of the fifth resistor, where X is the number of the current modules to the power stage chips.

[0028] A second aspect embodiment of the present application provides a circuit board, comprising a parallel circuit architecture of a multi-phase power stage chip as described in any one of the first aspect embodiments.

[0029] A third aspect of the present application provides an electronic device, comprising the circuit board as described in the second aspect of the present application.

[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0032] Figure 1 A schematic diagram of the structure of the parallel circuit architecture of the multi-phase power stage chip according to an embodiment of the present application;

[0033] Figure 2 A schematic diagram of the structure of a power stage chip according to an embodiment of the present application;

[0034] Figure 3is a schematic structural diagram of a first signal processing sub-circuit in an embodiment of the present application;

[0035] Figure 4 This is a schematic diagram of the structure of a first signal processing unit in an embodiment of the present application;

[0036] Figure 5 It is a timing diagram of PWM and PWMO of an embodiment of the present application;

[0037] Figure 6 for Figure 1 Signal diagram of PWM1, PWM2, PWM3 and PWM4. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0039] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0040] In the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0041] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0042] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0043] The first aspect of the present application provides a parallel circuit architecture of a multi-phase power stage chip. Figure 1 , Figure 1 This is a structural diagram of the parallel circuit architecture of the multi-phase power stage chip of the embodiment of the present application. The parallel circuit architecture of the multi-phase power stage chip of the embodiment of the present application includes a main control module and multiple current modules. The main control module is provided with multiple current detection terminals and multiple pulse output terminals, and the number of current detection terminals corresponds one-to-one to the pulse output terminals; and the current detection terminals correspond one-to-one to the current modules; each current module includes multiple power stage chips, and the number of pulse output terminals is equal to the number of power stage chips in one current module; the control terminal of each power stage chip in the current module is connected to the pulse output terminal in a one-to-one correspondence; the current sharing pins of each power stage chip in the current module are interconnected; the current detection terminal is connected to the current detection pin of a power stage chip in the corresponding current module; and the pulse output terminals connected to the power stage chips connected to the current detection terminals in each current module are different;

[0044] The main control module is used to: output pulse signals respectively through the pulse output terminal, and detect the current of the corresponding connected power level chip through the current detection terminal; when it is detected that the current of the target current detection terminal is greater than the current of the remaining current detection terminals, reduce the duty cycle of the pulse signal of the pulse output terminal connected to the power level chip connected to the target current detection terminal; when it is detected that the current of the target current detection terminal is less than the current of the remaining current detection terminals, increase the duty cycle of the pulse signal of the pulse output terminal connected to the power level chip connected to the target current detection terminal.

[0045] Specifically, in the circuit architecture of the embodiment of the present application, each current module is connected in parallel, and each power level chip in the current module is connected in parallel. The pulse output end of the main control module outputs a pulse signal. Since the control end of each power level chip in the current module is connected to the pulse output end in a one-to-one correspondence, each power level chip in the current module corresponds to the pulse signal in a one-to-one correspondence. The current detection end is connected to the current detection pin of a power level chip in the corresponding current module; and the pulse output end connected to the power level chip connected to the current detection end in each current module is different. The target current detection terminal is any one of the multiple current detection terminals. When it is detected that the current of the target current detection terminal is greater than the current of the remaining current detection terminals, it means that the output current of the power level chip connected to the target current detection terminal is greater than the current of the remaining power level chips, and the current is mainly related to the duty cycle of the pulse signal, that is, the duty cycle of the pulse signal connected to the power level chip connected to the target current detection terminal is too high, the target pulse signal is the pulse signal connected to the power level chip connected to the target current detection terminal, and the current of each power level chip connected to the target pulse signal is too high, therefore, the duty cycle of the target pulse signal is reduced to make the current of each power level chip the same. When it is detected that the current of the target current detection terminal is less than the current of the remaining current detection terminals, it means that the duty cycle of the target pulse signal is too low, therefore, the duty cycle of the target pulse signal is increased to make the current of each power level chip the same. In this way, the output currents of the power level chips connected in parallel can be made the same to ensure the stability and service life of the circuit, and in this application, one pulse signal can control multiple power level chips, which can save the pins of the main control module.

[0046] For example, refer to Figure 1 , the number of current modules is 4, and the 4 current modules are groupA, groupB, groupC, and groupD. The number of power stage chips in the current module is 4. In one current module, the 4 power stage chips are PS1, PS2, PS3, and PS4. The main control module is provided with 4 current detection terminals and 4 pulse output terminals. The 4 pulse output terminals are PWM1, PWM2, PWM3, and PWM4, and the 4 current detection terminals are CSA, CSB, CSC, and CSD. For example, when it is detected that the current at CSA is too large, it means that the output current of PS1 in groupA is too large, that is, the duty cycle of PWM1 is too high. Therefore, the output current of PS4 in groupB, PS3 in groupC, and PS2 in groupD is also too large. The main control module reduces the duty cycle of the pulse signal output by PWM1 to reduce the current of PS1 in groupA, PS4 in groupB, PS3 in groupC, and PS2 in groupD, so that the output current of each power stage chip is the same. Refer to Figure 6 , Figure 6 for Figure 1 Signal diagram of PWM1, PWM2, PWM3 and PWM4.

[0047] It should be noted that the models of the power stage chips are the same, and the output current of the power stage chip is related to the duty cycle of the pulse signal. The higher the duty cycle of the pulse signal, the greater the output current of the power stage chip connected to the pulse signal. In the current module, the current sharing pins of the power stage chips are connected to each other. Figure 2 , Figure 2 The schematic diagram of the structure of the power stage chip of the embodiment of the present application. The power stage chip includes a current balancing unit, a current sampling unit, an upper tube driver, a lower tube driver, an upper power tube and a lower power tube, and also includes a capacitor CL and an inductor L. The current balancing unit is connected to a pulse signal, and the current balancing unit is used to control the upper tube driver and the lower tube driver based on the pulse signal. The current sampling unit is used to sample the output current of the power stage chip and transmit the output current to the current balancing unit. The current balancing unit is provided with a current sharing pin. Figure 1 and Figure 2 In the figure, Ishr is the current sharing pin, and CS is the current detection pin. In a multi-phase parallel power supply system, the Ishr pin achieves current balance between phases by connecting a specific resistor (usually 3K ohms). This can ensure that the current of each phase is evenly distributed to avoid the situation where some phases are overloaded and other phases are under-currented. The upper tube driver is connected to the gate of the upper power tube, and the lower tube driver is connected to the gate of the lower power tube. The upper power tube is HS, and the lower power tube is LG. The source of the upper power tube is connected to the input voltage VIN, the source of the lower power tube is grounded, and the drain of the lower power tube is connected to the drain of the upper power tube, and one end of the inductor L is connected between the connection between the lower power tube and the upper power tube, and the other end serves as the output Vout of the power stage chip and is grounded through the capacitor CL. The present application does not limit the specific structure of the current balancing unit and the current adopting unit, and Figure 2 The illustrated power stage chip is only an example, and the power stage chip may also include other electrical components, and this application does not make any specific limitation on the power stage chip.

[0048] It should be noted that Figure 1 The number of current modules and the number of power stage chips illustrated are merely examples and should not be construed as limitations on the present application.

[0049] It is understandable that, referring to Figure 3 , Figure 3 This is a schematic diagram of the structure of the first signal processing sub-circuit of the embodiment of the present application. The main control module includes multiple first signal processing sub-circuits, and the first signal processing sub-circuits correspond to the pulse output terminals one by one;

[0050] The first signal processing subcircuit includes a first transconductance operational amplifier, a first resistor, a second resistor, a third resistor, a first current source and a first signal processing unit. The positive input terminal of the first transconductance operational amplifier is grounded through the first resistor, and the positive input terminal of the first transconductance operational amplifier and the first resistor serve as the first current input terminal of the first signal processing subcircuit, and the first current input terminal is connected to each current detection terminal; the reverse input terminal of the first transconductance operational amplifier is grounded through the second resistor, and the reverse input terminal of the first transconductance operational amplifier and the second resistor serve as the second current input terminal of the first signal processing subcircuit, and the second current input terminal is connected to the target current detection terminal; the output terminal of the first transconductance operational amplifier is grounded through the third resistor; the output terminal of the first current source and the voltage input terminal of the first signal processing unit are connected between the third resistor and the output terminal of the first transconductance operational amplifier, and the output terminal of the first signal processing unit serves as the pulse output terminal corresponding to the target current detection terminal, and the signal input terminal of the first signal processing unit is connected to the signal output terminal of the first signal processing unit;

[0051] The first signal processing unit is used to increase or decrease the duty cycle of the output signal of the signal output terminal of the first signal processing unit based on the voltage of the third resistor.

[0052] It is worth noting that the resistance of the first resistor is N times the resistance of the second resistor, where N is the number of current detection terminals. Figure 1 In the example, N is 4, which means that the resistance of the second resistor is 4 times that of the first resistor. Figure 3 ,exist Figure 3 In the example, the first resistor is Rs / 4, the second resistor is Rs<4:1>, SUM(CS ) represents the first current input terminal of the first signal processing sub-circuit, and CS<4:1> represents the second current input terminal of the first signal processing sub-circuit. SUM(CS ) terminal is the sum of the currents of the CSA terminal, the CSB terminal, the CSC terminal, and the CSD terminal. The current of the CS<4:1> terminal is the current of one of the CSA terminal, the CSB terminal, the CSC terminal, and the CSD terminal. gm<4:1> is a first transconductance operational amplifier, Ios<4:1> is a first current source, RL<4:1> is a third resistor, ADPWM is a first signal processing unit, and Vdly<4:1> represents the voltage of RL. PWM<4:1> represents a pulse signal, which is one of PWM1, PWM2, PWM3, and PWM4. Igm<4:1> represents the output current of the first transconductance operational amplifier. VIshr represents the voltage of the first resistor, and Vcs<4:1> represents the voltage of the second resistor. ADPWM is a first signal processing unit.

[0053] Specifically, for example, CS<4:1> is the current of the CSA end. If VIshr is greater than Vcs, it means that the average current of the CSA end, CSB end, CSC end, and CSD end is greater than the current of the CSA end, that is, the average current of PS1 of groupA, the current of PS1 of groupB, the current of PS1 of groupC, and the current of PS1 of groupD is greater than the current of PS1 of groupA. At this time, Igm<4:1> is a negative value, and Vdly<4:1> decreases, which increases the duty cycle of the output signal of the signal output end of the first signal processing unit, that is, increases the duty cycle of PWM1 connected to PS1 in groupA.

[0054] If VIshr is less than Vcs, it means that the average current of the CSA terminal, CSB terminal, CSC terminal, and CSD terminal is less than the current of the CSA terminal, that is, the average current of PS1 of groupA, the current of PS1 of groupB, the current of PS1 of groupC, and the current of PS1 of groupD is less than the current of PS1 of groupA. At this time, Igm<4:1> is a positive value, then Vdly<4:1> increases, and the duty cycle of the output signal of the signal output terminal of the first signal processing unit is reduced, that is, the duty cycle of PWM1 connected to PS1 in groupA is reduced.

[0055] It is understandable that, referring to Figure 4 , Figure 4 The first signal processing unit of the embodiment of the present application is a schematic diagram of the structure. The first signal processing unit includes a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, and a fourth resistor. The gate of the first field effect tube serves as the signal input end of the first signal processing unit, the gate of the first field effect tube is connected to the gate of the second field effect tube, the drain of the first field effect tube is connected to the drain of the second field effect tube, and the source of the second field effect tube is grounded; one end of the fourth resistor is connected to the source of the first field effect tube, and the other end serves as the voltage input end of the first signal processing unit; one end of the first capacitor is connected to the drain of the second field effect tube, and the other end is grounded; the gate of the third field effect tube is connected to the gate of the second field effect tube, the source of the third field effect tube is grounded, the source of the third field effect tube is connected to the drain of the second field effect tube, the gate of the fourth field effect tube, and the gate of the fifth field effect tube, the source of the fourth field effect tube is grounded, the drain of the fourth field effect tube is connected to the drain of the fifth field effect tube, and the source of the fifth field effect tube is connected to the power supply voltage.

[0056] Specifically, in Figure 4 In the embodiment, the first field effect tube is P1, the second field effect tube is N1, the third field effect tube is N2, the fourth field effect tube is N3, the fifth field effect tube is P2, the first capacitor is C1, and the fourth resistor is R1. Figure 4 PWM in the figure indicates a pulse signal, which is one of PWM1, PWM2, PWM3, and PWM4, and PWMO indicates a processed pulse signal. Figure 5 , Figure 5 This is the timing diagram of PWM and PWMO of the embodiment of the present application. When PWM is rising, N2 opens quickly, causing N3 to open quickly, then the rising edge delay of PWM is very small and can be ignored; when PWM falls, P1 opens, Vdly and R1 generate current to charge the first capacitor C1, and the voltage on C1 gradually rises. When the voltage on the first capacitor rises to the threshold voltage of N3, N3 opens; changing the size of Vdly can change the charging current, which in turn causes different charging times for the first capacitor, that is, different delays, thereby changing the duty cycle of PWM; if Vdly is large, the charging current is large, the charging speed is fast, and the delay is small, then the duty cycle of the output PWMO is small. When Vdly decreases, the charging current becomes smaller, the charging speed becomes slower, the delay becomes larger, and the duty cycle of the output PWMO becomes larger.

[0057] In some other embodiments, each power stage chip in the current module can be connected to the same PWM signal.

[0058] In one embodiment, referring to Figure 4 The first signal processing unit further includes a first selector, a first input end of the first selector is connected to the drain of the fourth field effect transistor; a second input end of the first selector is connected to the gate of the first field effect transistor, the first selector is also connected to an external control signal, and an output end of the first selector is used as a signal output end of the first signal processing unit;

[0059] When the external control signal is at a low level, the signal at the output end of the first selector is the signal at the first input end;

[0060] When the external control signal is at a high level, the signal at the output terminal of the first selector is the signal at the second input terminal.

[0061] Specifically, TrimCBL is an external control signal. Usually, in the first signal processing unit, the external control signal is at a low level.

[0062] In one embodiment, the current module includes multiple second signal processing sub-circuits, and the multiple second signal processing sub-circuits correspond one-to-one to the power stage chips in the current module; it should be noted that the second signal processing sub-circuit can be set inside the power stage chip or outside the power stage chip. When the second signal processing sub-circuit is set inside the power stage chip, the second signal processing sub-circuit serves as a current balancing unit of the power stage chip.

[0063] The second signal processing sub-circuit comprises:

[0064] The second signal processing subcircuit includes a second transconductance operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second current source and a second signal processing unit. The positive input terminal of the second transconductance operational amplifier is grounded through the fifth resistor, and the positive input terminal of the first transconductance operational amplifier and the fifth resistor serve as the first current input terminal of the second signal processing subcircuit, and the first current input terminal is connected to the current detection pin of each power stage chip in the current module; the reverse input terminal of the second transconductance operational amplifier is grounded through the sixth resistor, and the reverse input terminal of the second transconductance operational amplifier and the sixth resistor serve as the second current input terminal of the second signal processing subcircuit, and the second current input terminal is connected to the current detection pin of the corresponding power stage chip; the output terminal of the second transconductance operational amplifier is grounded through the seventh resistor; the output terminal of the second current source and the voltage input terminal of the second signal processing unit are connected between the seventh resistor and the output terminal of the second transconductance operational amplifier, and the output terminal of the second signal processing unit serves as the pulse output terminal corresponding to the target current detection terminal, and the signal input terminal of the second signal processing unit is connected to the signal output terminal of the second signal processing unit;

[0065] The second signal processing unit is used to increase or decrease the duty cycle of the output signal of the signal output terminal of the second signal processing unit based on the voltage of the seventh resistor.

[0066] The second signal processing unit includes a sixth field effect tube, a seventh field effect tube, an eighth field effect tube, a ninth field effect tube, a tenth field effect tube, and an eighth resistor. The gate of the sixth field effect tube serves as a signal input end of the first signal processing unit, the gate of the sixth field effect tube is connected to the gate of the seventh field effect tube, the drain of the sixth field effect tube is connected to the drain of the seventh field effect tube, and the source of the seventh field effect tube is grounded; one end of the eighth resistor is connected to the source of the sixth field effect tube, and the other end serves as a voltage input end of the first signal processing unit; one end of the first capacitor is connected to the drain of the seventh field effect tube, and the other end is grounded; the gate of the eighth field effect tube is connected to the gate of the seventh field effect tube, the source of the eighth field effect tube is grounded, the source of the eighth field effect tube is connected to the drain of the seventh field effect tube, the gate of the ninth field effect tube, and the gate of the tenth field effect tube, the source of the ninth field effect tube is grounded, the drain of the ninth field effect tube is connected to the drain of the tenth field effect tube, and the source of the tenth field effect tube is connected to the power supply voltage.

[0067] The resistance of the sixth resistor is X times the resistance of the fifth resistor, where X is the number of current modules to power stage chips.

[0068] The second signal processing unit also includes a second selector, a first input end of the second selector is connected to the drain of the ninth field effect tube; the second input end of the second selector is connected to the gate of the first field effect tube, and the second selector is also connected to an external control signal. The output end of the second selector serves as the signal output end of the second signal processing unit. The signal output end of the second signal processing unit is connected to the control end of the power stage chip to control the operation of the upper power tube and the lower power tube.

[0069] When the external control signal is at a low level, the signal at the output end of the second selector is the signal at the first input end;

[0070] When the external control signal is at a high level, the signal at the output terminal of the second selector is the signal at the second input terminal.

[0071] Exemplarily, the number of current modules to power stage chips is 4, so X is 4. The number of second signal processing sub-circuits is 4. The first field effect tube is equivalent to the sixth field effect tube, the second field effect tube is equivalent to the seventh field effect tube, the third field effect tube is equivalent to the eighth field effect tube, the fourth field effect tube is equivalent to the ninth field effect tube, and the fifth field effect tube is equivalent to the tenth field effect tube; the first resistor is equivalent to the fifth resistor, the second resistor is equivalent to the sixth resistor, the third resistor is equivalent to the seventh resistor, the fourth resistor is equivalent to the eighth resistor, the first current source is equivalent to the second current, the first transconductance operational amplifier is equivalent to the second transconductance operational amplifier, and the first selector is equivalent to the second selector. Therefore, the second signal processing sub-circuit has the same structure and principle as the first signal processing sub-circuit, which will not be repeated here.

[0072] In one embodiment, referring to Figure 1 , the current detection pin of a power level chip in each current module is connected to the current detection end of the main control module, and the power level chip is the master chip (Mater), and the other power level chips in the current module are slave chips. In each current module, PS1 is the master chip, and PS2 to PS3 are slave chips. In the second signal processing sub-circuit, if the power level chip corresponding to the second signal processing sub-circuit is the master chip, the external control signal of the second selector in the second signal processing sub-circuit is a high level, that is, the current module does not process the pulse signal connected to the master chip, and directly uses the pulse signal output by the main control module to control the operation of the master chip, which can ensure the stability of the system. In the second signal processing sub-circuit corresponding to the slave chip, the external control signal of the second selector is a low level.

[0073] In another embodiment, no matter whether the power stage chip corresponding to the second signal processing subcircuit is a master chip or a slave chip, the external control signal of the second selector is at a low level, and those skilled in the art can set the level of the external control signal according to actual needs.

[0074] In some embodiments, the current detection pin of the master chip in the current module is connected to the current detection pin of at least one slave chip, so that the current input to the current detection terminal of the master control module is the sum of the output current of the master chip and the output current of at least one slave chip. Exemplarily, in each current module, the current output pins of PS1, PS2, PS3, and PS4 are connected, and the current at the current detection terminal of the current module (i.e., current CS<4:1>) is the sum of the output current of PS1, the output current of PS2, the output current of PS3, and the output current of PS4. And SUM(CS ) is the sum of the four CS<4:1>. For example, CS<4:1> is the sum of the output currents of PS1, PS2, PS3, and PS4 in groupA. If Vcs<4:1> is greater than VIshr, it means that the total output current of groupA is greater than the average of the total output currents of groupA, groupB, groupC, and groupD. Since the pulse signal connected to the main chip PS1 of groupA is PWM1, the duty cycle of PMW1 is reduced to reduce the total output current of groupA.

[0075] If Vcs<4:1> is less than VIshr, it means that the total output current of groupA is less than the average of the total output currents of groupA, groupB, groupC and groupD. Since the pulse signal connected to the main chip PS1 of groupA is PWM1, the duty cycle of PMW1 is increased to increase the total output current of groupA.

[0076] A second aspect of the present application provides a circuit board, comprising a parallel circuit architecture of a multi-phase power stage chip of the first aspect.

[0077] Since the circuit board includes the parallel circuit architecture of the multi-phase power stage chip in the embodiment of the first aspect, the corresponding content of the parallel circuit architecture of the multi-phase power stage chip in the embodiment mentioned in the first aspect is also applicable to the circuit board in the embodiment mentioned in the second aspect, and has the same implementation principle and technical effect. In order to avoid redundant description, it will not be described in detail here.

[0078] A third aspect of the present application provides an electronic device, comprising a circuit board according to the second aspect.

[0079] Since the electronic device includes the circuit board of the second aspect embodiment, and the circuit board includes the parallel circuit architecture of the multi-phase power stage chip of the first aspect embodiment, the corresponding content of the parallel circuit architecture of the multi-phase power stage chip in the embodiment mentioned in the first aspect is also applicable to the electronic device in the embodiment mentioned in the third aspect, and has the same implementation principle and technical effect. In order to avoid redundant description, it will not be described in detail here.

[0080] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present application. In addition, the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

Claims

1. A parallel circuit architecture of a multi-phase power stage chip, characterized in that: include: A main control module, wherein the main control module is provided with a plurality of current detection terminals and a plurality of pulse output terminals, and the number of the current detection terminals corresponds one to one with the number of the pulse output terminals; A plurality of current modules, and the current detection terminals correspond to the current modules one by one; each of the current modules includes a plurality of power-level chips, and the number of the pulse output terminals is equal to the number of the power-level chips in one of the current modules; The control end of each power stage chip in the current module is connected to the pulse output end in a one-to-one correspondence; The current detection end is connected to a current detection pin of a power stage chip in the corresponding current module; and the pulse output end connected to the power stage chip connected to the current detection end in each current module is different; The main control module is used for: The pulse output terminals respectively output pulse signals, and the current of the correspondingly connected power stage chips is detected through the current detection terminals; When it is detected that the current of the target current detection terminal is greater than the current of the other current detection terminals, reducing the duty cycle of the pulse signal of the pulse output terminal connected to the power stage chip connected to the target current detection terminal; When it is detected that the current of the target current detection terminal is less than the current of the remaining current detection terminals, the duty cycle of the pulse signal of the pulse output terminal connected to the power stage chip connected to the target current detection terminal is increased.

2. The parallel circuit architecture of the multi-phase power stage chip according to claim 1, characterized in that: The main control module includes a plurality of first signal processing sub-circuits, and the first signal processing sub-circuits correspond one-to-one to the pulse output terminals; The first signal processing subcircuit includes a first transconductance operational amplifier, a first resistor, a second resistor, a third resistor, a first current source and a first signal processing unit, wherein the positive input terminal of the first transconductance operational amplifier is grounded through the first resistor, and the positive input terminal of the first transconductance operational amplifier and the first resistor serve as the first current input terminal of the first signal processing subcircuit, and the first current input terminal is connected to each of the current detection terminals; the negative input terminal of the first transconductance operational amplifier is grounded through the second resistor, and the negative input terminal of the first transconductance operational amplifier and the second resistor serve as the second current input terminal of the first signal processing subcircuit, and the second current input terminal is connected to the target current detection terminal; the output terminal of the first transconductance operational amplifier is grounded through the third resistor; the output terminal of the first current source and the voltage input terminal of the first signal processing unit are connected between the third resistor and the output terminal of the first transconductance operational amplifier, and the output terminal of the first signal processing unit serves as the pulse output terminal corresponding to the target current detection terminal, and the signal input terminal of the first signal processing unit is connected to the signal output terminal of the first signal processing unit; The first signal processing unit is used to increase or decrease a duty cycle of an output signal of a signal output terminal of the first signal processing unit based on a voltage of the third resistor.

3. The parallel circuit architecture of the multi-phase power stage chip according to claim 2, characterized in that: The first signal processing unit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, and a fourth resistor. The gate of the first field effect transistor P1 serves as a signal input terminal of the first signal processing unit, the gate of the first field effect transistor is connected to the gate of the second field effect transistor N1, the drain of the first field effect transistor is connected to the drain of the second field effect transistor, and the source of the second field effect transistor is grounded; one end of the fourth resistor is connected to the source of the first field effect transistor, and the other end serves as a voltage input terminal of the first signal processing unit; one end of the first capacitor is connected to the drain of the second field effect transistor, and the other end is grounded; the gate of the third field effect transistor N2 is connected to the gate of the second field effect transistor, the source of the third field effect transistor is grounded, the source of the third field effect transistor is connected to the drain of the second field effect transistor, the gate of the fourth field effect transistor N3, and the gate of the fifth field effect transistor P2, the source of the fourth field effect transistor is grounded, the drain of the fourth field effect transistor is connected to the drain of the fifth field effect transistor, and the source of the fifth field effect transistor is connected to the power supply voltage.

4. The parallel circuit architecture of the multi-phase power stage chip according to claim 3, characterized in that: The first signal processing unit further includes a first selector, wherein a first input end of the first selector is connected to the drain of the fourth field effect transistor; a second input end of the first selector is connected to the gate of the first field effect transistor, the first selector is further connected to an external control signal, and an output end of the first selector serves as a signal output end of the first signal processing unit; When the external control signal is at a low level, the signal at the output end of the first selector is the signal at the first input end; When the external control signal is at a high level, the signal at the output terminal of the first selector is the signal at the second input terminal.

5. The parallel circuit architecture of the multi-phase power stage chip according to claim 1, characterized in that: The current module includes a plurality of second signal processing sub-circuits, and the plurality of second signal processing sub-circuits correspond one-to-one to the power stage chips in the current module; the second signal processing sub-circuits include: The second signal processing subcircuit includes a second transconductance operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, a second current source, and a second signal processing unit. The positive input terminal of the second transconductance operational amplifier is grounded through the fifth resistor, and the positive input terminal of the first transconductance operational amplifier and the fifth resistor are used as the first current input terminal of the second signal processing subcircuit, and the first current input terminal is connected to the current detection pin of each power stage chip in the current module; the reverse input terminal of the second transconductance operational amplifier is grounded through the sixth resistor, and the reverse input terminal of the second transconductance operational amplifier and the sixth resistor are used as the second current input terminal of the second signal processing subcircuit, and the second current input terminal is connected to the current detection pin of the corresponding power stage chip; the output terminal of the second transconductance operational amplifier is grounded through the seventh resistor; the output terminal of the second current source and the voltage input terminal of the second signal processing unit are connected between the seventh resistor and the output terminal of the second transconductance operational amplifier, and the output terminal of the second signal processing unit is used as the pulse output terminal corresponding to the target current detection terminal, and the signal input terminal of the second signal processing unit is connected to the signal output terminal of the second signal processing unit; The second signal processing unit is used to increase or decrease a duty cycle of an output signal of a signal output terminal of the second signal processing unit based on a voltage of the seventh resistor.

6. The parallel circuit architecture of the multi-phase power stage chip according to claim 5, characterized in that: The second signal processing unit includes a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, and an eighth resistor, the gate of the sixth field effect transistor serves as a signal input terminal of the first signal processing unit, the gate of the sixth field effect transistor is connected to the gate of the seventh field effect transistor, the drain of the sixth field effect transistor is connected to the drain of the seventh field effect transistor, and the source of the seventh field effect transistor is grounded; One end of the eighth resistor is connected to the source of the sixth field effect transistor, and the other end serves as the voltage input end of the first signal processing unit; one end of the first capacitor is connected to the drain of the seventh field effect transistor, and the other end is grounded; the gate of the eighth field effect transistor is connected to the gate of the seventh field effect transistor, the source of the eighth field effect transistor is grounded, the source of the eighth field effect transistor is connected to the drain of the seventh field effect transistor, the gate of the ninth field effect transistor, and the gate of the tenth field effect transistor, the source of the ninth field effect transistor is grounded, the drain of the ninth field effect transistor is connected to the drain of the tenth field effect transistor, and the source of the tenth field effect transistor is connected to the supply voltage.

7. The parallel circuit architecture of the multi-phase power stage chip according to claim 2, characterized in that: The resistance of the second resistor is N times the resistance of the first resistor, where N is the number of the current detection terminals.

8. The parallel circuit architecture of the multi-phase power stage chip according to claim 5, characterized in that: The resistance of the sixth resistor is X times the resistance of the fifth resistor, where X is the number of the current modules to the power stage chips.

9. A circuit board, characterized in that: A parallel circuit architecture comprising a multi-phase power stage chip as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the circuit board as claimed in claim 9.

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