Analog-to-digital conversion circuit, chip and electronic device based on boost module

Abstract

The present disclosure relates to the field of analog-to-digital conversion, and proposes an analog-to-digital conversion circuit, a chip and an electronic device based on a boosting module. The circuit comprises a boosting module, a clock buffer module, a conversion module and a feedback module. The power supply voltage of the boosting module, the conversion module and the feedback module is less than or equal to a first threshold value. The boosting module is used to generate at least one voltage signal with a voltage value greater than the power supply voltage to power the clock buffer module. The clock buffer module is used to generate at least one pair of clock signals with a swing greater than the first threshold value, and output the clock signals to the conversion module to drive at least one unit in the conversion module. The conversion module is used to obtain a digital output signal according to an analog input signal and a feedback signal. The feedback module is used to generate a feedback signal according to the latest digital output signal and output the feedback signal to the conversion module. The analog-to-digital conversion circuit of the present disclosure has a smaller chip area and lower power consumption, and can realize high-quality analog-to-digital conversion at a low voltage.

Description

Technical Field

[0001] This disclosure relates to the field of analog-to-digital conversion, and more particularly to an analog-to-digital conversion circuit, chip, and electronic device based on a boost module. Background Technology

[0002] With the application and development of the Internet of Things (IoT), obtaining real-time information and data from IoT devices has become indispensable. Power supply for IoT devices is a crucial aspect of IoT system design, as it directly impacts device reliability, durability, and cost. Common power supply methods for IoT devices include battery power, solar power, cable power, wireless charging, and energy harvesting (EH). Energy harvesting refers to utilizing ambient energy, such as solar power, wind power, mechanical vibration, or temperature differences, to provide power, reducing reliance on batteries.

[0003] However, in some environments, the energy density that can be harvested is often low, and the voltage that can be generated is also very low, so IoT devices must operate at low voltages. This poses a significant challenge to the performance of some circuits in IoT devices (such as analog-to-digital converters). Some existing analog-to-digital converters cannot maintain high-quality analog-to-digital conversion when the supply voltage is low, while others, although they can maintain high-quality analog-to-digital conversion at low supply voltages, significantly increase the power consumption and chip area occupied by the analog-to-digital converter circuit. Summary of the Invention

[0004] In view of this, this disclosure proposes an analog-to-digital converter circuit, chip, and electronic device based on a boost module. The analog-to-digital converter circuit of the embodiments of this disclosure occupies a smaller chip area, consumes less power, and can achieve high-quality analog-to-digital conversion at low voltage.

[0005] According to one aspect of this disclosure, an analog-to-digital converter circuit based on a boost module is provided. The circuit includes a boost module, a clock buffer module, a conversion module, and a feedback module. The power supply voltage of the boost module, the conversion module, and the feedback module is less than or equal to a first threshold. The boost module is used to generate at least one voltage signal with a voltage value greater than the power supply voltage, and the voltage signal is used to power the clock buffer module. The clock buffer module is used to generate at least one pair of clock signals with a swing greater than the first threshold and outputs the clock signals to the conversion module to drive at least one unit in the conversion module. The conversion module is used to obtain a digital output signal based on an analog input signal and a feedback signal. The feedback module is used to generate the feedback signal based on the latest digital output signal and output it to the conversion module.

[0006] In one possible implementation, the conversion module includes a first chopper unit, a capacitor filter unit, a dead-time control unit, a voltage-to-current conversion unit, a second chopper unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a second input signal, and the feedback signal includes a differential first feedback signal and a second feedback signal. A first terminal of the first chopper unit receives the first input signal, a second terminal of the first chopper unit receives the second input signal, a third terminal of the first chopper unit is connected to a first terminal of the capacitor filter unit, and a fourth terminal of the first chopper unit is connected to a second terminal of the capacitor filter unit. The third terminal of the capacitor filter unit is connected to a first terminal of the dead-time control unit and a third terminal of the feedback module, and the fourth terminal of the capacitor filter unit is connected to a second terminal of the dead-time control unit and a fourth terminal of the feedback module. The first feedback signal is output, and the second feedback signal is output from the fourth terminal of the feedback module; the third terminal of the dead-time control unit is connected to the first terminal of the voltage-to-current conversion unit, and the fourth terminal of the dead-time control unit is connected to the second terminal of the voltage-to-current conversion unit; the third terminal of the voltage-to-current conversion unit is connected to the first terminal of the second chopper unit, and the fourth terminal of the voltage-to-current conversion unit is connected to the second terminal of the second chopper unit; the third terminal of the second chopper unit is connected to the first terminal of the integration unit, and the fourth terminal of the second chopper unit is connected to the second terminal of the integration unit; the third terminal of the integration unit is connected to the first terminal of the quantization unit, and the fourth terminal of the integration unit is connected to the second terminal of the quantization unit; the third terminal of the quantization unit is connected to the first terminal of the output unit, and the fourth terminal of the quantization unit is connected to the second terminal of the output unit; the digital output signal is output from the third terminal of the output unit.

[0007] In one possible implementation, the quantization unit is a time-domain quantization unit, the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented using digital circuits.

[0008] In one possible implementation, the clock signal is used to drive the first chopper unit, the dead-time control unit, and the second chopper unit.

[0009] In one possible implementation, the boost module includes multiple DC-DC converters, the power supply voltage is input to the multiple DC-DC converters respectively, the clock buffer module includes multiple clock buffers, each DC-DC converter is connected to a clock buffer, each DC-DC converter boosts the input voltage signal to obtain a boosted voltage signal and outputs it to the clock buffer connected to it, and each clock buffer generates a pair of clock signals according to the received voltage signal and outputs them.

[0010] In one possible implementation, the swing of the clock signal used to drive the dead-time control unit is greater than or equal to a second threshold, and the swing of the clock signal used to drive the first chopper unit and the second chopper unit is greater than or equal to a third threshold, wherein the second threshold is greater than the third threshold.

[0011] In one possible implementation, the boost module includes a DC-DC converter, the clock buffer module includes a clock buffer, the DC-DC converter is connected to the clock buffer, the DC-DC converter boosts the input voltage signal to obtain a boosted voltage signal and outputs it to the clock buffer, and the clock buffer generates a pair of clock signals based on the received voltage signal and outputs them.

[0012] In one possible implementation, the feedback module includes a logic control unit, a third chopper unit, and a capacitive digital-to-analog converter unit. The first terminal of the logic control unit serves as the first terminal of the feedback module, the second terminal of the logic control unit serves as the second terminal of the feedback module, the third terminal of the logic control unit is connected to the first terminal of the third chopper unit, and the fourth terminal of the logic control unit is connected to the second terminal of the third chopper unit. The third terminal of the third chopper unit is connected to the first terminal of the capacitive digital-to-analog converter unit, and the fourth terminal of the third chopper unit is connected to the second terminal of the capacitive digital-to-analog converter unit. The third terminal of the capacitive digital-to-analog converter unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog converter unit serves as the fourth terminal of the feedback module.

[0013] According to another aspect of this disclosure, a chip is provided, including the analog-to-digital conversion circuit described in any of the preceding claims.

[0014] According to another aspect of this disclosure, an electronic device is provided, including the chip described above.

[0015] According to the analog-to-digital conversion circuit of this disclosure, by setting a boost module and a clock buffer module, a clock signal with a swing higher than a first threshold can be obtained. The conversion module is driven by this higher-swing clock signal. The conversion module obtains a digital output signal based on the analog input signal and the feedback signal. The feedback module generates a feedback signal based on the latest digital output signal and outputs it to the conversion module, thereby achieving high-quality analog-to-digital conversion. In the analog-to-digital conversion circuit, only some units in the conversion module are driven by a high-swing clock signal, and only the clock buffer module requires a voltage signal with a voltage value greater than the first threshold. The boost module, other units of the conversion module, and the feedback module can still be powered by a power supply voltage lower than the first threshold. Therefore, the overall power consumption of the analog-to-digital conversion circuit is low. Furthermore, the voltage signal obtained by boosting is not provided to the entire analog-to-digital conversion circuit, so there is no need to set up a large area of ​​capacitor to store additional charge, resulting in a smaller chip area. In summary, the analog-to-digital conversion circuit of this disclosure occupies a smaller chip area, has lower power consumption, and can achieve high-quality analog-to-digital conversion at low voltage.

[0016] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0018] Figure 1 This diagram illustrates how an energy harvesting system powers circuitry in an IoT device.

[0019] Figure 2 This illustrates one operating scheme for the ADC when the supply voltage is low.

[0020] Figure 3 This illustrates an alternative operating scheme for the ADC when the supply voltage is low.

[0021] Figure 4 Exemplary application scenarios of analog-to-digital conversion circuits according to embodiments of the present disclosure are shown.

[0022] Figure 5 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure is provided.

[0023] Figure 6a A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure is provided.

[0024] Figure 6b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure is provided.

[0025] Figure 7 A schematic diagram showing the structure of the boost module and clock buffer module according to an embodiment of the present disclosure is provided.

[0026] Figure 8 A schematic diagram showing the structure of the boost module and clock buffer module according to an embodiment of the present disclosure is provided.

[0027] Figure 9 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure is provided. Detailed Implementation

[0028] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0029] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0030] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0031] Figure 1 This diagram illustrates how an energy harvesting system powers circuitry in an IoT device.

[0032] like Figure 1 As shown, an energy harvesting system can harvest energy from an external energy source and convert it into a supply voltage (VDD) for output to data transceiver modules, digital signal processors (DSPs), analog-to-digital converters (ADCs), etc., in IoT devices. The energy density harvested by such a system is often less than 100 μW / cm³. 2 The corresponding output voltage is typically below 300mV. This voltage powers the ADC, DSP, and data transceiver modules in the system. For the ADC, achieving high-quality analog-to-digital conversion at such a low voltage is extremely difficult.

[0033] Figure 2 This illustrates one operating scheme for the ADC when the supply voltage is low.

[0034] like Figure 2As shown, a DC-DC converter can be used to directly boost the low voltage VDD output from the energy harvesting system to a high voltage VDD' that allows the ADC to operate normally, and then provide this voltage to the ADC as its power supply voltage. The ADC will then convert the input analog signal VDD into a DC-DC converter. IN Converted to digital signal D OUT And output. But this leads to a significant increase in the overall power consumption of the ADC. In addition, the voltage signal output by the DC-DC converter is used as the power supply voltage for the entire ADC, so a very large capacitor needs to be added to the chip to store the charge, which increases the chip area and thus the cost of the chip.

[0035] Figure 3 This illustrates an alternative operating scheme for the ADC when the supply voltage is low.

[0036] like Figure 3 As shown, another approach is to use ADCs that can still function normally at low voltages, such as oversampling ADCs based on inverter amplifiers, oversampling ADCs based on ring oscillators, and successive approximation register (SAR) ADCs based on carefully designed comparators. This allows for direct analog-to-digital conversion at the low voltage VDD output of the energy harvesting system, converting the input analog signal VDD into digital signal VDD. IN Converted to digital signal D OUT And output. However, the circuit modules in these ADCs are often very sensitive to the supply voltage, and the analog-to-digital conversion quality fluctuates greatly. Furthermore, the analog-to-digital conversion quality of these ADCs at low voltages, such as conversion linearity and conversion accuracy, is significantly different from that of ADCs performing analog-to-digital conversion at normal voltages.

[0037] In summary, some existing analog-to-digital (ADC) circuits cannot maintain high-quality ADC conversion when the supply voltage is low. While some existing ADC circuits can maintain high-quality ADC conversion at low supply voltages, they increase power consumption and chip area. Therefore, how to reduce the power consumption and chip area of ​​ADC circuits while maintaining high-quality ADC conversion has become a pressing technical problem to be solved in this field.

[0038] In view of this, this disclosure proposes an analog-to-digital converter circuit, chip, and electronic device based on a boost module. The analog-to-digital converter circuit of the embodiments of this disclosure occupies a smaller chip area, consumes less power, and can achieve high-quality analog-to-digital conversion at low voltage.

[0039] Figure 4 Exemplary application scenarios of analog-to-digital conversion circuits according to embodiments of the present disclosure are shown.

[0040] like Figure 4 As shown, the electronic device may include an energy harvesting system and a chip. The analog-to-digital conversion circuit of this embodiment may be disposed on the chip. The energy harvesting system can power the chip. The output voltage of the energy harvesting system may be less than a first threshold, that is, the energy harvesting system outputs an ultra-low voltage. The value of the first threshold can be set according to the application scenario requirements, for example, set to 0.3V. This embodiment does not limit the specific value of the first threshold.

[0041] The analog-to-digital converter circuit can receive the analog input signal to be converted, perform analog-to-digital conversion to obtain a digital output signal, and then output it.

[0042] The chip may further include a data transceiver module (not shown) and a digital signal processor (not shown). Analog input signals can be signals received by the data transceiver module and then transmitted by the data transceiver module to the analog-to-digital converter circuit. Digital output signals can be output to the digital signal processor for processing, or transmitted to the data transceiver module for transmission to other devices / modules; this disclosure does not limit this.

[0043] Those skilled in the art will understand that if the electronic device itself has a power supply, the chip can also be powered by the power supply. Even when the power supply is insufficient and the output voltage is less than a first threshold voltage signal, the analog-to-digital conversion circuit on the chip can still achieve high-quality analog-to-digital conversion. This disclosure does not limit the power source of the chip.

[0044] Figure 5 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure is provided.

[0045] like Figure 5 As shown, in one possible implementation, the circuit includes a boost module, a clock buffer module, a conversion module, and a feedback module, wherein the power supply voltage of the boost module, the conversion module, and the feedback module is less than or equal to a first threshold.

[0046] The boost module is used to generate at least one voltage signal with a voltage value greater than the power supply voltage, and the voltage signal is used to power the clock buffer module;

[0047] The clock buffer module is used to generate at least one pair of clock signals with an amplitude greater than a first threshold, and outputs the clock signals to the conversion module to drive at least one unit in the conversion module;

[0048] The conversion module is used to obtain a digital output signal based on the analog input signal and the feedback signal;

[0049] The feedback module is used to generate a feedback signal based on the latest digital output signal and output it to the conversion module.

[0050] For example, an analog-to-digital conversion circuit may include a boost module, a clock buffer module, a conversion module, and a feedback module, wherein the boost module, the conversion module, and the feedback module are all powered by a power supply voltage less than a first threshold.

[0051] The boost module generates a voltage signal with a value greater than the power supply voltage, which powers the clock buffer module. The clock buffer module is powered by a voltage greater than a first threshold, thus generating a clock signal with a swing greater than the first threshold. Provided the boost module generates at least one voltage signal, the clock buffer module can generate at least one pair of clock signals, each pair consisting of two differential clock signals.

[0052] The clock buffer module outputs a clock signal to the conversion module to drive at least one unit within the conversion module. The conversion module may include multiple units, some of which are critical and can maintain high performance when driven by a high-swing clock signal. In this case, the clock signal generated by the clock buffer module can be used to drive these critical units.

[0053] This disclosure does not limit the specific structure of the boost module, clock buffer module, and conversion module, as long as they can achieve the above functions. Examples of the structure of the boost module, clock buffer module, and conversion module, as well as examples of key units, are given later.

[0054] The analog-to-digital conversion process can be divided into three main stages: voltage-to-current conversion, integration, and quantization, all of which can be completed by the conversion module. Before entering the voltage-to-current conversion stage, the analog input signal can undergo operations such as chopping to optimize signal quality. During voltage-to-current conversion, the larger the swing of the analog input signal, the greater the deviation of the final digital output signal. Therefore, the conversion module can use feedback signals to adjust the swing of the analog input signal, and then perform voltage-to-current conversion, integration, and quantization on the adjusted analog input signal to obtain the digital output signal.

[0055] The analog input signal is periodically input to the conversion module, therefore the conversion module may output a digital output signal more than once. The feedback signal can be generated by the feedback module based on the latest digital output signal. This method improves the accuracy of adjusting the analog-to-digital conversion process using the feedback signal. This disclosure does not limit the specific structure of the feedback module, as long as the feedback module can achieve the above functions. An example of the structure of the feedback module is given later.

[0056] According to the analog-to-digital conversion circuit of this disclosure, by setting a boost module and a clock buffer module, a clock signal with a swing higher than a first threshold can be obtained. The conversion module is driven by this higher-swing clock signal. The conversion module obtains a digital output signal based on the analog input signal and the feedback signal. The feedback module generates a feedback signal based on the latest digital output signal and outputs it to the conversion module, thereby achieving high-quality analog-to-digital conversion. In the analog-to-digital conversion circuit, only some units in the conversion module are driven by a high-swing clock signal, and only the clock buffer module requires a voltage signal with a voltage value greater than the first threshold. The boost module, other units of the conversion module, and the feedback module can still be powered by a power supply voltage lower than the first threshold. Therefore, the overall power consumption of the analog-to-digital conversion circuit is low. Furthermore, the voltage signal obtained by boosting is not provided to the entire analog-to-digital conversion circuit, so there is no need to set up a large area of ​​capacitor to store additional charge, resulting in a smaller chip area. In summary, the analog-to-digital conversion circuit of this disclosure occupies a smaller chip area, has lower power consumption, and can achieve high-quality analog-to-digital conversion at low voltage.

[0057] Figure 6a and Figure 6b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure is provided.

[0058] like Figure 6a and Figure 6b As shown, in one possible implementation, the conversion module includes a first chopper unit 10, a capacitor filter unit 20, a dead-time control unit 30, a voltage-to-current conversion unit 40, a second chopper unit 50, an integration unit 60, a quantization unit 70, and an output unit 80.

[0059] The analog input signals include a differential first input signal VINP and a differential second input signal VINN, and the feedback signals include a differential first feedback signal VFP and a differential second feedback signal VFN.

[0060] The first terminal a1 of the first chopper unit receives the first input signal VINP, the second terminal a2 of the first chopper unit receives the second input signal VINN, the third terminal a3 of the first chopper unit is connected to the first terminal b1 of the capacitor filter unit, and the fourth terminal a4 of the first chopper unit is connected to the second terminal b2 of the capacitor filter unit.

[0061] The third terminal b3 of the capacitor filter unit is connected to the first terminal d1 of the dead zone control unit and the fourth terminal n4 of the feedback module. The fourth terminal b4 of the capacitor filter unit is connected to the second terminal d2 of the dead zone control unit and the third terminal n3 of the feedback module. The fourth terminal n4 of the feedback module outputs the first feedback signal VFP, and the third terminal n3 of the feedback module outputs the second feedback signal VFN.

[0062] The third terminal d3 of the dead zone control unit is connected to the first terminal e1 of the voltage-to-current conversion unit, and the fourth terminal d4 of the dead zone control unit is connected to the second terminal e2 of the voltage-to-current conversion unit.

[0063] The third terminal e3 of the voltage-to-current conversion unit is connected to the first terminal f1 of the second chopper unit, and the fourth terminal e4 of the voltage-to-current conversion unit is connected to the second terminal f2 of the second chopper unit.

[0064] The third terminal f3 of the second chopper unit is connected to the first terminal g1 of the integrator unit, and the fourth terminal f4 of the second chopper unit is connected to the second terminal g2 of the integrator unit.

[0065] The third terminal g3 of the integration unit is connected to the first terminal h1 of the quantization unit, the fourth terminal g4 of the integration unit is connected to the second terminal h2 of the quantization unit, the third terminal h3 of the quantization unit is connected to the first terminal j1 of the output unit and the first terminal n1 of the feedback unit, and the fourth terminal h4 of the quantization unit is connected to the second terminal j2 of the output unit and the second terminal n2 of the feedback unit.

[0066] The third terminal j3 of the output unit outputs the digital output signal DOUT.

[0067] For example, the conversion module may include a first chopper unit, a capacitor filter unit, a dead-time control unit, a voltage-to-current conversion unit, a second chopper unit, an integration unit, a quantization unit, and an output unit.

[0068] The first chopper unit can receive an external analog input signal. The analog input signal can be a differential signal, including a first input signal and a second input signal. In this case, the first chopper unit, the capacitor filter unit, the dead-time control unit, the voltage-to-current conversion unit, the second chopper unit, the integration unit, and the quantization unit each include two input terminals and two output terminals; the output unit may include two input terminals and one output terminal.

[0069] The first chopper unit receives a first input signal at its first end, a second input signal at its second end, outputs the signal VAP obtained by chopping the first input signal at its third end, and outputs the signal VAN obtained by chopping the second input signal at its fourth end.

[0070] like Figure 6b As shown, the first chopper unit may include switches S1-S4. The first terminal s11 of S1 is connected to the first terminal s31 of S3, serving as the first terminal of the first chopper unit. The second terminal s12 of S1 is connected to the first terminal s41 of S4, serving as the third terminal of the first chopper unit. The first terminal s21 of S2 is connected to the second terminal s42 of S4, serving as the second terminal of the first chopper unit. The second terminal s22 of S2 is connected to the second terminal s32 of S3, serving as the fourth terminal of the first chopper unit.

[0071] Those skilled in the art should understand that the first chopper unit can also be implemented using other structures, as long as it has chopping function and can chop the differential input signal to obtain the differential output signal. The embodiments of this disclosure do not limit the specific structure of the first chopper unit.

[0072] Signals VAP and VAN are output from the first chopper unit and then input to the first and second terminals of the capacitor filter unit, respectively. Figure 6b As shown, the capacitor filter unit may include capacitor C3 and capacitor C4. One end of capacitor C3 serves as the first end of the capacitor filter unit, and the other end of capacitor C3 serves as the third end of the capacitor filter unit; one end of capacitor C4 serves as the second end of the capacitor filter unit, and the other end of capacitor C4 serves as the fourth end of the capacitor filter unit.

[0073] Capacitor C3 can be used to filter out interference components in signal VAP. Capacitor C4 can be used to filter out interference components in signal VAN. Since the third terminal of the capacitor filter unit is also connected to the fourth terminal of the feedback module, and the fourth terminal of the capacitor filter unit is also connected to the third terminal of the feedback module, the feedback signal output by the feedback module is a differential signal including a first feedback signal VFP and a second feedback signal VFN. The fourth and third terminals of the feedback module output the first feedback signal VFP and the second feedback signal VFN, respectively. Therefore, after the interference components in signal VAP are filtered out, the amplitude is adjusted by the first feedback signal VFP to obtain signal VBP, which is then output to the first terminal of the dead-zone control unit. After the interference components in signal VAN are filtered out, the amplitude is adjusted by the second feedback signal VFN to obtain signal VBN, which is then output to the second terminal of the dead-zone control unit.

[0074] like Figure 6b As shown, the dead-time control unit may include switches S5 and S6. One end of switch S5 serves as the first terminal of the dead-time control unit, and the other end serves as the third terminal. One end of switch S6 serves as the second terminal of the dead-time control unit, and the other end serves as the fourth terminal. The third terminal of the dead-time control unit is connected to the first terminal of the voltage-to-current conversion unit, and the fourth terminal is connected to the second terminal. After signals VBP and VBN enter the voltage-to-current conversion unit, they enter the voltage-to-current conversion stage described above. Therefore, switches S5 and S6 can be controlled to open for a short period each cycle (the cycle frequency can be the sampling frequency of the analog-to-digital conversion circuit) to prevent signals VBP and VBN from entering the voltage-to-current conversion unit, thereby optimizing the quality of the signal output by the voltage-to-current conversion unit (e.g., removing glitches from the signal output by the voltage-to-current conversion unit). The time period for controlling switches S5 and S6 to open can be set according to the application scenario requirements; this embodiment does not impose any limitations on this.

[0075] The voltage-to-current conversion unit can convert the input signal VBP into a current signal IEP, and the input signal VBN into a current signal IEN. The function of the voltage-to-current conversion unit can be implemented using existing transconductance amplifiers, which will not be elaborated upon here.

[0076] The current signal IEP can be input to the first terminal of the second chopper unit, and the current signal IEN can be input to the second terminal of the second chopper unit. The structure and function of the second chopper unit can be the same as those of the first chopper unit, and will not be described again here. The third terminal of the second chopper unit outputs the signal IFP obtained by chopping the signal IEP, and the fourth terminal outputs the signal IFN obtained by chopping the signal IEN.

[0077] like Figure 6b As shown, the integration unit may include a first integrator and a second integrator. The signal IFP can be input to one end of the first integrator (the first end of the integration unit), where the first integrator integrates the signal IFP and outputs the signal IGP through the other end (the third end of the integration unit). The signal IFN can be input to one end of the second integrator (the second end of the integration unit), where the second integrator integrates the signal IFN and outputs the signal IGN through the other end (the fourth end of the integration unit). The first and second integrators can be implemented based on existing technology, and their structures will not be described in detail here.

[0078] Signal IGP can be input to the first terminal of the quantization unit, and signal IGN can be input to the second terminal of the quantization unit. The quantization unit can quantize signal IGP into value A and signal IGN into value B. Value A can be output through the third terminal of the quantization unit, and value B can be output through the fourth terminal of the quantization unit. The quantization unit can be implemented based on existing technology, and its structure will not be described in detail here.

[0079] Value A can be input to the first terminal of the output unit, and value B can be input to the second terminal of the output unit. For example... Figure 6b As shown, the output unit can perform a subtraction operation on values ​​A and B, and output the result as a digital output signal DOUT. The digital output signal DOUT can be output from the third terminal of the output unit. The output unit can be implemented based on existing technology, and its specific structure will not be described in detail here.

[0080] See Figure 6a Values ​​A and B are also input to the feedback module. Based on values ​​A and B, the feedback module outputs a first feedback signal VFP and a second feedback signal VFN. For an example of the structure of the feedback module and how it performs the above functions, please refer to [link to relevant documentation]. Figure 9 .

[0081] In one possible implementation, the quantization unit is a time-domain quantization unit, and the integration unit is a time-domain integration unit, both implemented using digital circuits.

[0082] For example, since time-domain integration and quantization units perform signal processing in the time domain rather than the analog domain, both can be implemented using digital circuits. Digital circuits can operate at low voltages (especially those using advanced manufacturing processes; the more advanced the process, the lower the operating voltage), allowing time-domain integration and quantization units to maintain high performance even at power supply voltages below a first threshold. This further increases the proportion of digital circuitry in the analog-to-digital converter (ADC) circuit, further reducing its power consumption.

[0083] In one possible implementation, a clock signal is used to drive the first chopper unit, the dead-time control unit, and the second chopper unit.

[0084] For example, the clock signal output by the clock buffer module mentioned above can be used to drive at least one unit in the conversion module. In one example, the driven unit could be the first chopper unit, the dead-time control unit, or the second chopper unit.

[0085] The swing amplitudes of the clock signals driving the first chopper unit, the dead-time control unit, and the second chopper unit can be the same or different, and this disclosure does not impose any restrictions on this.

[0086] In one possible implementation, the swing of the clock signal used to drive the dead-time control unit is greater than or equal to a second threshold, and the swing of the clock signal used to drive the first chopper unit and the second chopper unit is greater than or equal to a third threshold, wherein the second threshold is greater than the third threshold.

[0087] For example, the higher the swing of the clock signal, the better the effect of driving the first chopper unit, the dead-time control unit, and the second chopper unit, but the greater the power consumption. Therefore, the clock signal driving the first chopper unit, the dead-time control unit, and the second chopper unit can be determined according to their requirements for the swing of the clock signal.

[0088] In one example, the clock signal swing required by the first and second chopper units can be equal to a third threshold (e.g., 0.9V). The dead-time control unit requires a higher clock signal swing, which can be equal to a second threshold (e.g., 1.1V). Assuming the clock buffer module outputs a first pair of clock signals with a swing of 0.9V, a second pair of clock signals with a swing of 1V, and a third pair of clock signals with a swing of 1.1V, in this case, the first pair of clock signals can be used to drive the first and second chopper units, and the third pair of clock signals can be used to drive the dead-time control unit.

[0089] If the swing of the pair of clock signals with the lowest swing output by the clock buffer module has exceeded the second threshold, then the pair of clock signals with the lowest swing can be used to drive the first chopper unit, the dead-time control unit, and the second chopper unit.

[0090] That is, the swing of the clock signal used to drive the dead-time control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopper unit and the second chopper unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0091] The third threshold can be greater than the first threshold, and the specific value of the third threshold is not limited in the embodiments of this disclosure.

[0092] In this way, the power consumption of the analog-to-digital conversion circuit can be reduced while ensuring the quality of analog-to-digital conversion.

[0093] Figure 7 A schematic diagram showing the structure of the boost module and clock buffer module according to an embodiment of the present disclosure is provided.

[0094] like Figure 7 As shown, in one possible implementation, the boost module includes a DC-DC converter, the clock buffer module includes a clock buffer, and the DC-DC converter is connected to the clock buffer.

[0095] The DC-DC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer. The clock buffer generates a pair of clock signals based on the received voltage signal and outputs them.

[0096] For example, if the voltage value of the boosted voltage signal from a single DC-DC converter is greater than or equal to a first threshold, then the boost module only needs to include one DC-DC converter. Correspondingly, the clock buffer module can also include only one clock buffer. The output of the DC-DC converter is connected to the input of the clock buffer. The DC-DC converter boosts the input voltage signal to obtain a boosted voltage signal and outputs it to the clock buffer. The clock buffer generates a pair of clock signals based on the received voltage signal and outputs them. The clock signals generated by the clock buffer can be differential clock signals, and the low level of the clock signal can be 0, while the high level can be equal to the voltage value of the received voltage signal.

[0097] Both the DC-DC converter and the clock buffer can be implemented based on existing technologies, and their structures will not be described in detail here.

[0098] This approach simplifies the structure of the boost module and clock buffer module.

[0099] Figure 8 A schematic diagram showing the structure of the boost module and clock buffer module according to an embodiment of the present disclosure is provided.

[0100] like Figure 8 As shown, in one possible implementation, the boost module includes multiple DC-DC converters, with the power supply voltage input to each of the multiple DC-DC converters. The clock buffer module includes multiple clock buffers, with each DC-DC converter connected to one clock buffer.

[0101] Each DC-DC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer connected to it. Each clock buffer generates a pair of clock signals based on the received voltage signal and outputs them.

[0102] For example, as described above, different units driven by the clock signal may have different requirements for the clock signal swing. Therefore, the boost module can include multiple DC-DC converters with different boost capabilities. The power supply voltage is input to multiple DC-DC converters, and each DC-DC converter outputs a voltage signal with a different voltage value. This ensures that for each unit to be driven, there is a DC-DC converter whose output voltage value matches the clock signal swing required by that unit. Correspondingly, the clock buffer module can also include multiple clock buffers, with the output of each DC-DC converter connected to the input of one clock buffer. Each clock buffer generates and outputs a pair of clock signals based on the received voltage signal. The clock signals generated by the clock buffers can be differential clock signals, where the low level of the clock signal can be 0 and the high level can be equal to the voltage value of the received voltage signal, thus obtaining multiple pairs of clock signals with different swings. In this case, multiple pairs of clock signals with different swings can meet the clock signal swing requirements of all units to be driven.

[0103] In this way, the clock buffer module can output a clock signal that meets the requirements of the application scenario.

[0104] Figure 9 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure is provided.

[0105] like Figure 9 As shown, in one possible implementation, the feedback module includes a logic control unit, a third chopper unit, and a capacitive digital-to-analog converter unit.

[0106] The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopper unit, and the fourth end of the logic control unit is connected to the second end of the third chopper unit.

[0107] The third terminal of the third chopper unit is connected to the first terminal of the capacitive digital-to-analog converter unit, and the fourth terminal of the third chopper unit is connected to the second terminal of the capacitive digital-to-analog converter unit.

[0108] The third terminal of the capacitive digital-to-analog converter unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog converter unit serves as the fourth terminal of the feedback module.

[0109] For example, the feedback module as a whole can be implemented using digital circuits, and may include a logic control unit 11, a third chopper unit 21, and a capacitive digital-to-analog converter unit 31.

[0110] The first terminal n1 of the logic control unit serves as the first terminal of the feedback module, receiving value A, and the second terminal n2 of the logic control unit serves as the second terminal of the feedback module, receiving value B. Based on values ​​A and B, the logic control unit can obtain a digital control signal, which can be a differential signal, including signals ctrl1 and ctrl2. The digital control signal is used to control the degree of adjustment of the feedback module to the analog input signal. The logic control unit can be implemented based on existing technology, and the specific implementation method of the logic control unit will not be elaborated here.

[0111] The third terminal P3 of the logic control unit can be connected to the first terminal Q1 of the third chopper unit, and the fourth terminal P4 of the logic control unit can be connected to the second terminal Q2 of the third chopper unit. Signals ctrl1 and ctrl2 are input to the third chopper unit for chopping. Signal ctrl1 is chopped to obtain signal ctrl11, and signal ctrl2 is chopped to obtain signal ctrl22. The third chopper unit can be implemented based on existing technology, and its specific implementation will not be elaborated here.

[0112] The third terminal q3 of the third chopper unit can input signal ctrl11 to the first terminal p1 of the capacitive digital-to-analog converter (DAC), and the fourth terminal q4 of the third chopper unit can input signal ctrl22 to the second terminal p2 of the DAC. The DAC performs digital-to-analog conversion on signal ctrl11 to obtain signal VFN, and performs digital-to-analog conversion on signal ctrl22 to obtain signal VFP. Signals VFP and VFN can be analog signals. In this case, signal VFP can be used in operations with signal VAP, and signal VFN can be used in operations with signal VAN. The third terminal n3 of the DAC outputs signal VFN, and the fourth terminal n4 outputs signal VFP. The DAC can be implemented based on existing technology, and the specific implementation method will not be elaborated here.

[0113] This disclosure also provides a chip, including the analog-to-digital converter circuit described above. A schematic diagram of the chip structure can be found [link to schematic diagram]. Figure 4 .

[0114] This disclosure also provides an electronic device, including the chip described above. The electronic device may be a terminal device or a server; this disclosure does not limit the specific type of electronic device.

[0115] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0116] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital converter circuit based on a boost module, characterized in that, The circuit includes a boost module, a clock buffer module, a conversion module, and a feedback module. The power supply voltage of the boost module, the conversion module, and the feedback module is less than or equal to a first threshold. The boost module is used to generate at least one voltage signal with a voltage value greater than the power supply voltage, and the voltage signal is used to power the clock buffer module. The clock buffer module is used to generate at least one pair of clock signals with an amplitude greater than the first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module; The conversion module is used to obtain a digital output signal based on the analog input signal and the feedback signal; The feedback module is used to generate the feedback signal based on the latest digital output signal and output it to the conversion module; The conversion module includes a first chopper unit, a capacitor filter unit, a dead-time control unit, a voltage-to-current conversion unit, a second chopper unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a differential second input signal, and the feedback signal includes a differential first feedback signal and a differential second feedback signal. The first terminal of the first chopper unit receives the first input signal, the second terminal of the first chopper unit receives the second input signal, the third terminal of the first chopper unit is connected to the first terminal of the capacitor filter unit, and the fourth terminal of the first chopper unit is connected to the second terminal of the capacitor filter unit. The third terminal of the capacitor filter unit is connected to the first terminal of the dead zone control unit and the third terminal of the feedback module. The fourth terminal of the capacitor filter unit is connected to the second terminal of the dead zone control unit and the fourth terminal of the feedback module. The third terminal of the feedback module outputs the first feedback signal, and the fourth terminal of the feedback module outputs the second feedback signal. The third terminal of the dead zone control unit is connected to the first terminal of the voltage-to-current conversion unit, and the fourth terminal of the dead zone control unit is connected to the second terminal of the voltage-to-current conversion unit. The third terminal of the voltage-to-current conversion unit is connected to the first terminal of the second chopper unit, and the fourth terminal of the voltage-to-current conversion unit is connected to the second terminal of the second chopper unit. The third end of the second chopper unit is connected to the first end of the integrator unit, and the fourth end of the second chopper unit is connected to the second end of the integrator unit. The third end of the integration unit is connected to the first end of the quantization unit, the fourth end of the integration unit is connected to the second end of the quantization unit, the third end of the quantization unit is connected to the first end of the output unit, and the fourth end of the quantization unit is connected to the second end of the output unit. The digital output signal is output from the third terminal of the output unit; The clock signal is used to drive the first chopper unit, the dead-time control unit, and the second chopper unit.

2. The circuit according to claim 1, characterized in that, The quantization unit is a time-domain quantization unit, and the integration unit is a time-domain integration unit. Both the quantization unit and the integration unit are implemented using digital circuits.

3. The circuit according to claim 1, characterized in that, The boost module includes multiple DC-DC converters, and the power supply voltage is input to each of the multiple DC-DC converters. The clock buffer module includes multiple clock buffers, and each DC-DC converter is connected to one clock buffer. Each DC-DC converter boosts the input voltage signal to obtain the boosted voltage signal and outputs it to the clock buffer connected to it. Each clock buffer generates a pair of clock signals based on the received voltage signal and outputs them.

4. The circuit according to claim 1, characterized in that, The swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, and the swing of the clock signal used to drive the first chopper unit and the second chopper unit is greater than or equal to the third threshold, wherein the second threshold is greater than the third threshold.

5. The circuit according to claim 1, characterized in that, The boost module includes a DC-DC converter, and the clock buffer module includes a clock buffer; the DC-DC converter is connected to the clock buffer. The DC-DC converter boosts the input voltage signal to obtain a boosted voltage signal and outputs it to the clock buffer. The clock buffer generates a pair of clock signals based on the received voltage signal and outputs them.

6. The circuit according to claim 3, characterized in that, The feedback module includes a logic control unit, a third chopper unit, and a capacitive digital-to-analog converter unit. The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopper unit, and the fourth end of the logic control unit is connected to the second end of the third chopper unit. The third terminal of the third chopper unit is connected to the first terminal of the capacitive digital-to-analog converter unit, and the fourth terminal of the third chopper unit is connected to the second terminal of the capacitive digital-to-analog converter unit. The third terminal of the capacitive digital-to-analog converter unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog converter unit serves as the fourth terminal of the feedback module.

7. A chip, characterized in that, The analog-to-digital converter circuit includes any one of claims 1-6.

8. An electronic device, characterized in that, Includes the chip described in claim 7.

Images