SAR ADC with backplane sampling and mismatch error shaping

Abstract

A SAR ADC includes a DAC, a comparator, and SAR circuitry, wherein the DAC includes: an MSB encoded with a first capacitor; a mismatch error shaping capacitor coupled to the MSB; an LSB encoded with a second capacitor, in which a first switch group couples the first capacitor and a bottom capacitor plate of the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to a first DAC feedback control signal, wherein a second switch group is coupled to a bottom capacitor plate of the second capacitor to receive the high reference voltage or the low reference voltage in response to a second DAC feedback control signal, and wherein the SAR circuitry is configured to feed back a mismatch error value from a previous SAR conversion cycle to the LSB sub-DAC during a current sampling cycle.

Description

Technical Field

[0001] The present disclosure is generally directed to circuit systems for data conversion.In one aspect, the present disclosure is generally directed to analog-to-digital converter (ADC) systems. Background Art

[0002] In electronic devices, an analog / digital converter (ADC, A / D or A to D) is a system that converts analog signals into digital signals. Successive approximation register (SAR) ADC is a widely used type of analog / digital converter that provides low power, medium speed, moderate to high resolution, minimal active analog circuitry, small die size, low latency, and high reusability. In operation, the SAR ADC converts a continuous analog waveform into a discrete digital representation via a binary search. For example, a 12-bit SAR ADC converts an analog input voltage into a 12-bit binary representation. The SAR ADC operates using a binary search principle, where the ADC makes decisions for each bit of resolution to converge to a digital output for each analog / digital conversion. The SAR ADC includes a digital / analog converter ("DAC") and a comparator connected in a feedback loop with SAR logic. The DAC can be formed by an array of binary weighted elements such as capacitors and / or resistors. In CMOS implementations, DACs are often implemented with capacitor arrays because capacitors are characterized by less mismatch error, faster settling time, and less current consumption than resistors for a given area, allowing for higher resolution, higher speed, and lower power. Each binary weighted element corresponds to a binary digit of a corresponding binary representation. To generate a 12-bit binary representation, a DAC may include twelve binary weighted elements and a dummy or terminal element, but the DAC may also use other weighting schemes for the elements, such as non-radix-2 or unary or combinations of weighting schemes.

[0003] During analog-to-digital conversion, the SAR ADC uses a sampling phase to sample the input voltage at the DAC, and during the comparison phase, the DAC elements are used to successively approximate the input voltage. At each successive approximation step, the SAR logic stores the comparator output at the output register as a digital word that provides a digital representation of the analog input voltage.

[0004] While SAR ADCs provide good performance up to about 12 bits, there are significant limitations beyond 12 bits where DAC element matching as well as comparator and preamplifier noise degrade the signal-to-noise-and-distortion ratio (“SNDR”) performance. Additionally, existing DACs have other performance limitations with reduced input range and / or gain errors that degrade SNDR performance. Oversampling techniques can only improve ADC accuracy and reduce the SNDR penalty from DAC element matching if dynamic element matching is used, but dynamic element matching (DEM) is rarely used on more than 4 to 5 most significant bits due to logic complexity and cost.

[0005] As can be seen from the foregoing, existing SAR ADC solutions for quickly and efficiently performing analog-to-digital conversion are actually extremely difficult because it is difficult to balance the design constraints of providing an efficient, low-complexity SAR ADC with the performance requirements of performing high-speed analog-to-digital conversion. Other limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of this application with reference to the accompanying drawings and detailed description. Summary of the invention

[0006] It should now be appreciated that an apparatus, method, program code, and system for controlling a successive approximation register (SAR) analog-to-digital converter (ADC) has been provided, the successive approximation register analog-to-digital converter comprising a digital-to-analog converter (DAC), a comparator, and a successive approximation register (SAR) circuit system. The disclosed DAC is connected and configured to generate an output voltage from a DAC feedback control signal, and comprises a plurality of most significant bit (MSB) capacitors having bottom and top capacitor plates. In selected embodiments, the plurality of MSB capacitors are encoded with one or more binary capacitors having bottom and top capacitor plates. The disclosed DAC also comprises a plurality of least significant bit (LSB) capacitors having bottom and top capacitor plates. In selected embodiments, the plurality of LSB capacitors are encoded with one or more binary capacitors having bottom and top capacitor plates. The DAC also comprises a mismatch error shaping capacitor having bottom and top capacitor plates, wherein the mismatch error shaping capacitor is connected in a bit position between the plurality of LSB capacitors and the plurality of MSB capacitors. The DAC also includes a first set of switches to couple the bottom capacitor plates of the plurality of MSB capacitors and the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to a first DAC feedback control signal, wherein the high reference voltage is greater than the low reference voltage. In selected embodiments, each switch in the first set of switches is a tri-state switch for selectively connecting the bottom capacitor plates of the plurality of MSB capacitors or the mismatch error shaping capacitor to the analog input voltage, the high reference voltage, or the low reference voltage in response to the first DAC feedback control signal. The DAC also includes a second set of switches to couple the bottom capacitor plates of the plurality of LSB capacitors to receive a high reference voltage or a low reference voltage in response to a second DAC feedback control signal. In selected embodiments, each switch in the second set of switches is a two-state switch for selectively connecting the bottom capacitor plates of the plurality of LSB capacitors to the high reference voltage or the low reference voltage in response to the second DAC feedback control signal. In other selected embodiments, the second set of switches couples the bottom capacitor plates of the plurality of LSB capacitors in response to the second DAC feedback control signal to receive a high reference voltage or a low reference voltage corresponding to a mismatch error value from a previous SAR conversion cycle. The disclosed comparator has a first input coupled to receive an output voltage from a DAC, a second input, and a comparison output based on a voltage difference between the first input and the second input. The disclosed SAR circuitry has an input coupled to receive the comparison output, and an output to provide a digital value corresponding to a digital representation of an analog input voltage, wherein the SAR circuitry is configured to feed back a mismatch error value from a previous SAR conversion cycle to the plurality of LSB capacitors during a current sampling cycle via a second DAC feedback control signal provided to a second set of switches.In selected embodiments, the SAR circuitry is configured to perform mismatch error shaping of the least significant bits in the DAC by sampling an equivalent charge of the plurality of LSB capacitors in the DAC using a mismatch error shaping capacitor. In other selected embodiments, the SAR circuitry is configured to control a second set of switches to couple the bottom capacitor plates of the plurality of LSB capacitors to a low reference voltage between each sampling cycle and each subsequent conversion cycle. In other selected embodiments, the SAR circuitry is configured to subtract mismatch error values ​​from a predetermined number of least significant bits corresponding to the plurality of LSB capacitors from a digital value at each conversion cycle to produce a final digital representation of the analog input voltage, wherein the mismatch error values ​​are determined during a previous conversion cycle. In selected embodiments, the mismatch error shaping capacitor has a capacitance that is equal in magnitude to the sum of the capacitances of the plurality of LSB capacitors. In selected embodiments, the DAC is a segmented DAC as a scaling capacitor having first and second scaling capacitor plates, wherein the first scaling capacitor plate is connected to the top capacitor plate of the plurality of MSB capacitors and the second scaling capacitor plate is connected to the top capacitor plate of the plurality of LSB capacitors, and wherein the top capacitor plate of the mismatch error shaping capacitor is connected to the first scaling capacitor plate and the top capacitor plate of the plurality of MSB capacitors. In such embodiments, the capacitance of the mismatch error shaping capacitor is approximately equal to the sum of the capacitances of the plurality of LSB capacitors as seen through the scaling capacitor. In selected embodiments, the DAC further comprises a terminal capacitor having bottom and top capacitor plates, wherein the top capacitor plate of the terminal capacitor is connected to the second scaling capacitor plate and the top capacitor plate of the LSB capacitor, and the bottom capacitor plate of the terminal capacitor is connected to the second set of switches.

[0007] In another form, a SAR ADC method, apparatus, program code, and system are provided. The disclosed method includes providing an analog input voltage and a mismatch error shaping code voltage value to a split capacitor digital / analog converter (DAC), the split capacitor digital / analog converter including a most significant bit (MSB) sub-DAC having one or more MSBs encoded with one or more first capacitors, a least significant bit (LSB) sub-DAC having one or more LSBs encoded with one or more second capacitors, a mismatch error shaping capacitor coupled to the MSB sub-DAC, and a scaling capacitor coupled between the LSB and MSB sub-DACs. In addition, the disclosed method includes initiating bottom plate sampling of the analog input voltage on a first capacitor and a mismatch error shaping capacitor of the MSB sub-DAC, wherein the one or more second capacitors of the LSB sub-DAC receive the mismatch error shaping code voltage value. In selected embodiments, the mismatch error shaping code voltage value corresponds to an LSB result captured from a digital value during a previous SAR ADC conversion cycle. In selected embodiments, the bottom plate sampling is initiated by connecting a common mode voltage to a first capacitor of the MSB sub-DAC and a top capacitor plate of the mismatch error shaping capacitor. The disclosed method also includes ending the bottom plate sampling of the analog input voltage. In addition, the disclosed method includes initiating an injection phase by resetting the one or more second capacitors of the LSB sub-DAC. In selected embodiments, the injection phase is initiated by connecting a low reference voltage to the bottom capacitor plate of the split capacitor DAC, and the split capacitor DAC resets the one or more second capacitors of the LSB sub-DAC. The disclosed method also includes performing a comparison using the output of the split capacitor DAC to provide a comparison output of the current SAR ADC conversion cycle. In addition, the disclosed method includes performing a successive approximation on the comparison output to provide a digital value representing the input voltage to the split capacitor DAC. The disclosed method also includes capturing a current LSB result from the digital value for subsequent SAR ADC conversion cycles. In addition, the disclosed method includes performing mismatch error shaping on the digital value by subtracting the LSB result captured from the previous SAR ADC conversion cycle from the digital value. In selected embodiments, the first capacitor of the MSB sub-DAC and the second capacitor of the LSB sub-DAC are each encoded with one or more binary capacitors. In other selected embodiments, the split capacitor DAC also includes a terminal capacitor coupled to the LSB sub-DAC.

[0008] In yet another form, a SAR ADC device, method, program code, and system are provided, which include first and second DACs, a differential comparator, and a SAR circuit system. The first DAC is configured to receive a first input voltage signal, a high voltage reference, and a low voltage reference, and to generate a first DAC output therefrom. In addition, the first DAC includes a first MSB sub-DAC having one or more MSBs encoded with one or more first capacitors, a first LSB sub-DAC having one or more LSBs encoded with one or more second capacitors, and a first mismatch error shaping capacitor coupled to the first MSB sub-DAC. The second DAC is configured to receive a second input voltage signal, a high voltage reference, and a low voltage reference, and to generate a second DAC output therefrom. In addition, the second DAC includes a second MSB sub-DAC having one or more MSBs encoded with one or more first capacitors, a second LSB sub-DAC having one or more LSBs encoded with one or more second capacitors, and a second mismatch error shaping capacitor coupled to the second MSB sub-DAC. The differential comparator has a first input coupled to receive a first DAC output from the first DAC, a second input coupled to receive a second DAC output from the second DAC, and a comparator output. In addition, the differential comparator is configured to generate a differential comparison of the first and second DAC outputs at the comparator output. The SAR circuit system has an input coupled to receive the comparator output. In addition, the SAR circuit system is configured to provide a digital value corresponding to a digital representation of the difference between the first analog input voltage and the second analog input voltage. In addition, the SAR circuit system is configured to feed back a control signal to the first DAC and the second DAC. In response to the control signal, the first DAC initiates a first DAC bottom plate sampling of the first analog input voltage on the first capacitor and the first mismatch error shaping capacitor of the first MSB sub-DAC, while the one or more second capacitors of the first LSB sub-DAC receive the first mismatch error shaping code voltage value. In addition, the control signal causes the second DAC to initiate a second DAC bottom plate sampling of the second analog input voltage on the first capacitor and the second mismatch error shaping capacitor of the second MSB sub-DAC, while the one or more second capacitors of the second LSB sub-DAC receive the second mismatch error shaping code voltage value. Subsequently, the control signal ends the first and second DAC bottom plate sampling of the first and second analog input voltages at the first DAC and the second DAC. Subsequently, the control signal causes the first DAC and the second DAC to initiate an injection phase in the first DAC and the second DAC by resetting the one or more second capacitors of the first and second LSB sub-DACs. Subsequently, the differential comparator performs a differential comparison of the first and second DAC outputs to provide a differential comparison of the current SAR ADC conversion cycle at the comparator output. Subsequently, the SAR circuit system performs a successive approximation on the differential comparison to provide a digital value.Once the SAR conversion is complete, the current LSB result is captured from the digital value for use in a subsequent SAR ADC conversion cycle. Additionally, mismatch error shaping is performed on the digital value by subtracting the LSB result captured from the previous SAR ADC conversion cycle from the digital value. In selected embodiments, the first capacitors of the first and second MSB sub-DACs and the second capacitors of the first and second LSB sub-DACs are each encoded with one or more binary capacitors, respectively. In other selected embodiments, the first DAC may include a first terminal capacitor coupled to the first LSB sub-DAC, and the second DAC may include a second terminal capacitor coupled to the second LSB sub-DAC. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention and its numerous objects, features and advantages achieved will be understood when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0010] Figure 1 Depicted is a simplified block diagram of a microcontroller computer system in accordance with selected embodiments of the present disclosure.

[0011] Figure 2 Depicting a schematic block diagram of a top-plate sampling SAR ADC.

[0012] Figure 3 Depicts a schematic block diagram of a backplane sampling SAR ADC.

[0013] Figure 4 A simplified circuit schematic depicting the DAC used in a top-plate sampling SAR ADC.

[0014] Figure 5A -C depicts an exemplary sampling, injection, and conversion stages of a mismatch error shaping sequence for use with a top-plate sampling SAR ADC.

[0015] Figure 6 A simplified circuit schematic depicting a DAC for a backplane sampling SAR ADC.

[0016] Figure 7 A simplified circuit schematic depicting a segmented DAC for a backplane sampling SAR ADC.

[0017] Figure 8 Depicted is a simplified circuit schematic of a segmented DAC for a backplate sampling SAR ADC including specified MES sampling capacitors in accordance with selected embodiments of the present disclosure.

[0018] Fig. 9 A simplified flow chart illustrating logic for operating a backplate sampling SAR ADC including a specified MES sampling capacitor is shown in accordance with selected embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Systems, apparatus, and methods are described for a backplane sampling successive approximation register (SAR) analog-to-digital converter (ADC) having a digital-to-analog converter (DAC) component formed with a multi-bit capacitor array, wherein additional capacitors at specified locations in the multi-bit capacitor array are used to enable mismatch error shaping (MES) on less significant capacitors in the multi-bit capacitor array. Providing the additional capacitors enables MES by replacing the LSB used to sample the input voltage, thereby freeing the LSB for sampling, and switching Vrefh or Vrefl as needed for MES. In selected embodiments, the backplane sampling DAC component is implemented as a segmented DAC, and the additional capacitors are added to the most significant bit (MSB) section of the segmented DAC so that mismatch error shaping can be performed on the less significant bit section while dynamic element matching or calibration techniques can be performed on the MSB section. In other embodiments, the backplane sampling DAC component is a non-segmented DAC, and the extra capacitor at a specified location in the multi-capacitor array is sized to have a value of the sum of the terminal capacitor and all lower effective capacitors, so that mismatch error shaping can be performed on the lower significant bit capacitors while dynamic element matching or calibration techniques can be performed on the extra capacitors and the higher effective capacitors. In addition to enabling mismatch error shaping of the lower significant bits, the extra capacitors can also be used to recover lost input range caused by mismatch error shaping by using the extra bits as essentially redundant bits equivalent to the sum of the terminal capacitor and all lower effective capacitors being used for MES during the SAR phase. It will be appreciated that if the segmented DAC does not sample the input voltage on the LSB array, then the terminal capacitor is not required.

[0020] Reference now Figure 1 , which depicts a simplified block diagram of a microcontroller computer system 10 according to selected embodiments of the present disclosure. As depicted, the microcontroller computer system 10 includes one or more processors 11 and a memory 12 connected to a data converter 14, one or more other modules 15, and an external bus interface 16 via a bidirectional bus 13. It will be appreciated that the microcontroller computer system 10 may receive inputs and provide outputs by means of a bus 17 or a plurality of electrical signals 17 coupled to the external bus interface 16. In other embodiments, the microcontroller computer system 10 may include more than one processor 11 and a memory 12 connected to a data converter 14, one or more other modules 15, and an external bus interface 16. Figure 1 As disclosed herein, microcontroller computer system 10 may be implemented as a single integrated circuit, as multiple integrated circuits, or as a combination of integrated circuits and discrete components.

[0021] To provide a contextual understanding of the present disclosure, reference is now made to Figure 2, which depicts a schematic block diagram of a SAR ADC 20 that performs top plate sampling of a received differential voltage input signal (Vin+, Vin-). The disclosed SAR ADC 20 includes a digital-to-analog converter (DAC) 21 and a comparator 24 connected in a feedback loop with a digital SAR logic block 25 that performs a binary search algorithm to provide an n-bit DAC feedback control signal to the DAC 21. The depicted DAC 21 includes a first sampling array 22 and a second sampling array 23 of capacitor elements. As depicted, each of the sampling arrays 22, 23 may include a capacitive sampling circuit (e.g., capacitors 22A-n, 23A-n), wherein the sampling capacitor Csmp has a top plate connected to the voltage input signal using connection switches 27, 28 and a bottom plate connected to a high reference voltage Vrefh or a low reference voltage Vrefl, the connection switches being controlled by a DAC control value (DAC CONTROL) generated by the SAR logic block 25. Other embodiments may use any type of charge redistribution array for data conversion. Additionally, alternative embodiments may utilize any desired and appropriate elements (eg, resistive elements, capacitive elements, combinations thereof, etc.).

[0022] The SAR ADC 20 has a first differential input terminal that receives a first differential input signal (Vin+), which is a positive differential input signal in this example, and a second differential input terminal that receives a second differential input signal (Vin-), which is a negative differential input signal in this example.

[0023] The first differential input terminal is connected to the positive input terminal of the comparator 24 through the first sampling switch S1. In this way, the first sampling switch S1 can selectively connect the first differential input terminal to the comparator 24 or disconnect it (and also connect to the plurality of first sampling capacitors Csmp in the first capacitive sampling array 22A-n or disconnect it, as will be discussed below). When the first sampling switch S1 is closed, the circuit samples the first differential input signal (Vin+). When the first sampling switch S1 is open, the circuit converts the sampled value of the first differential input signal (Vin+). The first capacitive sampling array 22A-n is also connected to the positive input terminal of the comparator 24. More specifically, the analog output signal from the first capacitive sampling array 22A-n is provided to the positive input terminal of the comparator 24.

[0024] In a similar manner, the second differential input terminal is connected to the negative input terminal of the comparator 24 through the second sampling switch S2. In this way, the second sampling switch S2 can selectively connect the second differential input terminal to the comparator 24 or disconnect it (and also connect to a plurality of second sampling capacitors Csmp in the second capacitive sampling array 23A-n, as will be discussed below). When the second sampling switch S2 is closed, the circuit samples the second differential input signal (Vin-). When the second sampling switch S2 is open, the circuit converts the sampled value of the second differential input signal (Vin-). The second capacitive sampling array 23A-n is also connected to the negative input terminal of the comparator 24. More specifically, the analog output signal from the second capacitive sampling array 23A-n is provided to the negative input terminal of the comparator 24.

[0025] The comparator 24 has a comparator output CMPOUT connected to the input of the digital SAR logic block 25. At each step of the approximation, the digital SAR logic block 25 stores the comparator output CMPOUT in the SAR register 26 in response to the latch signal. The digital SAR logic block 25 also processes the comparator output signal CMPOUT to generate a DAC control feedback signal DACCONTROL, which provides a DAC control value representing an n-bit digital word for supplying as a control to the first capacitive sampling array 22A-n and the second capacitive sampling array 23A-n in the DAC 21. In addition, the digital SAR logic block 25 generates a latch feedback signal LATCH provided to latch the comparator 24. The digital SAR logic block 25 also generates an output signal (RESULT) providing a digital representation of the differential input voltage signal Vin+, Vin-. The digital SAR logic block 25 also generates an ADC output signal (RESULT) representing a digital code at the end of the analog-to-digital conversion, as is also known in the art of SAR ADCs.

[0026] The DAC 21 includes a first capacitive sampling array 22A-n having a plurality of first sampling capacitors Csmp. Each first sampling capacitor Csmp is connected to the positive input of the comparator 24 through a top capacitor plate. In addition, each first sampling capacitor Csmp is connected to a connection switch 27 through a bottom capacitor plate, and the connection switch is controlled by a DAC control feedback signal from the digital SAR logic block 25 so that the bottom capacitor plate receives a corresponding reference voltage Vrefh, Vrefl representing the bit value of the digital word provided by the digital SAR logic block 25.

[0027] The DAC 21 also includes a second capacitive sampling array 23A-n having a plurality of second sampling capacitors Csmp. Each second sampling capacitor Csmp is connected to the negative input terminal of the comparator 24 through a top capacitor plate. In addition, each second sampling capacitor Csmp is connected to a connection switch 28 through a bottom capacitor plate, and the connection switch is controlled by the DAC control feedback signal from the digital SAR logic block 25 so that the bottom capacitor plate receives a corresponding reference voltage Vrefh, Vrefl representing the bit value of the digital word provided by the digital SAR logic block 25.

[0028] The SAR ADC 20 performs top plate sampling of the received differential signals because the first differential input signal (Vin+) and the second differential input signal (Vin-) are connected to the top plates of the sampling capacitors Csmp in the first capacitive sampling array 22A-n and the second capacitive sampling array 23A-n. It will be appreciated that there are advantages and disadvantages to performing top plate sampling of the differential input signaling (Vin+, Vin-) on the SAR ADC 20. One advantage of top plate sampling is that fewer switches are required than bottom plate sampling (described below). The main disadvantage of top plate sampling is that the unit capacitor Csmp and the input to the comparator 24 produce a top plate parasitic capacitance that reduces the input range. In addition, the top plate parasitic capacitor introduces gain error, which can become nonlinear if the parasitic effect is nonlinear. In addition, the sampling switches for the top plate sampling capacitors are susceptible to input voltage dependent clock feedthrough and charge injection.

[0029] To provide a contextual understanding of the present disclosure, reference is now made to Figure 3 , which depicts a schematic block diagram of a SAR ADC 30 that performs backplane sampling of a received differential voltage input signal (Vin+, Vin-). The disclosed SAR ADC 30 includes a digital-to-analog converter (DAC) 31 and a comparator 34 connected in a feedback loop with a digital SAR logic block 35 that performs a binary search algorithm to provide an n-bit DAC feedback control signal to the DAC 31. Figure 2 The corresponding feature description in Figure 3 To the extent that features are described herein, they will not necessarily be described again here.

[0030] The depicted DAC 31 includes a first sampling array 32 and a second sampling array 33 of elements. As depicted, each of the sampling arrays 32, 33 may include a capacitive sampling circuit (e.g., capacitors 32A-n, 33A-n), where the sampling capacitor Csmp has a top plate connected to the comparator 34 and a bottom plate connected to the voltage input signal, the high reference voltage Vrefh, or the low reference voltage Vrefl via a connection switch 37 under the control of the DAC control value (DAC CONTROL) generated by the SAR logic block 35. Other embodiments may use any type of charge redistribution array for data conversion. Again, alternative embodiments may use any desired and appropriate elements (e.g., resistive elements, capacitive elements, combinations thereof, etc.).

[0031] Instead of connecting the differential input signal (Vin+, Vin-) directly to the comparator 34, the SAR ADC 30 has a first differential input terminal at the first capacitive sampling array 32A-n that receives the first differential input signal (Vin+), which is a negative differential input signal in this example. The first differential input signal (Vin+) is in turn connected to the bottom plate of the sampling capacitor Csmp through a three-state connection switch 37, and the sampling capacitor has a top plate directly connected to the positive input terminal of the comparator 34. The three-state connection switch 37 is also connected to receive the reference voltage Vrefh, Vrefl. Therefore, the three-state connection switch 37 can selectively connect the bottom plate of each of the plurality of first sampling capacitors Csmp to: (i) the first differential input terminal or (ii) a corresponding one of the reference voltages Vrefh, Vrefl.

[0032] The SAR ADC 30 also includes a second differential input terminal at the second capacitive sampling array 33A-n that receives a second differential input signal (Vin-), which is a positive differential input signal in this example. The second differential input signal (Vin-) is in turn connected to the bottom plate of the sampling capacitor Csmp through a three-state connection switch 38 (also referred to as a three-way switch), and the sampling capacitor has a top plate directly connected to the negative input terminal of the comparator 34. The three-state connection switch 38 is also connected to receive the reference voltage Vrefh, Vrefl. Therefore, the three-state connection switch 38 can selectively connect the bottom plate of each of the plurality of second sampling capacitors Csmp to: (i) the second differential input terminal or (ii) a corresponding one of the reference voltages Vrefh, Vrefl.

[0033] The positive input terminal of the comparator 34 is connected to the common mode voltage (VCM) through the sampling switch 39, and the sampling switch can selectively connect the comparator 34 (and also the sampling capacitors Csmp in the first capacitive sampling array 32A-n) to VCM or disconnect. Similarly, the negative input terminal of the comparator 34 is connected to the common mode voltage (VCM) through the sampling switch 39, and the sampling switch can selectively connect the comparator 34 (and also the sampling capacitors Csmp in the second capacitive sampling array 33A-n) to VCM or disconnect.

[0034] It will be appreciated that when the three-state connection switches 37, 38 connect the bottom plate of each of the sampling capacitors Csmp in the first capacitive sampling array 32A-n and the second capacitive sampling array 33A-n to the first differential input terminal (Vin+) and the second differential input terminal (Vin-), respectively, and the sampling switch 39 connects the positive input terminal and the negative input terminal of the comparator 24 to VCM, the SAR ADC 30 is in a sampling operation state. In addition, when the three-state connection switches 37, 38 connect the bottom plate of each of the sampling capacitors Csmp in the first capacitive sampling array 32A-n and the second capacitive sampling array 33A-n to a corresponding one of the reference voltages Vrefh, Vrefl, respectively, and the sampling switch 39 disconnects the positive input terminal and the negative input terminal of the comparator 24 from VCM, the SAR ADC 30 is in a conversion operation state. In this arrangement, SAR ADC 30 performs bottom plate sampling of received differential signals because the first differential input signal (Vin+) and the second differential input signal (Vin-) are connected to the bottom plates of sampling capacitors Csmp in the first and second capacitive sampling arrays 32A-n, 33A-n.

[0035] In the depicted configuration, the comparator 34 has a comparator output CMPOUT connected to the input of the digital SAR logic block 35. At each step of the approximation, the digital SAR logic block 35 stores the comparator output CMPOUT in the SAR register 36 in response to the latch signal. The digital SAR logic block 35 also processes the comparator output signal CMPOUT to generate a DAC control feedback signal DAC CONTROL, which provides a DAC control value representing an n-bit digital word for supplying as a control to the first capacitive sampling array 32A-n and the second capacitive sampling array 33A-n in the DAC 31. In addition, the digital SAR logic block 35 generates a latch feedback signal LATCH provided to latch the comparator 34. The digital SAR logic block 35 also generates an output signal (RESULT) providing a digital representation of the differential input voltage signal Vin-, Vin+. The digital SAR logic block 35 also generates an ADC output signal (RESULT) representing a digital code at the end of the analog-to-digital conversion, as is also known in the art of SAR ADCs.

[0036] The SAR ADC 30 performs bottom plate sampling of the received differential signals because the first differential input signal (Vin+) and the second differential input signal (Vin-) are connected to the bottom plates of the sampling capacitors Csmp in the first capacitive sampling array 32A-n and the second capacitive sampling array 33A-n. It will be appreciated that there are advantages and disadvantages to performing bottom plate sampling of the differential input signaling (Vin+, Vin-) on the SAR ADC 30. Although more switches are required than top plate sampling, bottom plate sampling avoids the parasitic capacitance problem and allows a full input range without gain error (or with very low gain error). Bottom plate sampling also avoids input voltage dependent clock feedthrough and charge injection associated with closing the sampling switches. However, for both top plate sampling and bottom plate sampling SAR ADCs, the linearity of the capacitor array in the DAC is the main limiting factor because the oversampling technique is only effective for reducing noise, but not for eliminating distortion caused by any nonlinearity in the capacitor array. Trace parasitics and unit capacitance mismatch are two factors that affect linearity. Ideally, nonlinear errors introduced by trace parasitics in capacitor arrays can be solved by perfect circuit and layout design, but perfection is not always achievable. Unit capacitance mismatch is also a difficult problem to solve because it is related to process accuracy parameters and capacitor size.

[0037] To provide a contextual understanding of the present disclosure, reference is now made to Figure 4, which depicts a simplified circuit schematic of a 12-bit DAC 40 for a top plate sampling SAR ADC. The depicted DAC 40 includes a capacitor array 42, including a first terminal capacitor having a unit capacitance value C, and 12 additional capacitors corresponding to bits b0-b11, each having a binary weighted capacitance, starting with a first capacitor having a capacitance of C, a second capacitor having a capacitance of 2C, and continuing until a 12th capacitor having a capacitance of 2048C.

[0038] Each capacitor in the capacitor array 42 is selectively coupled between an input voltage Vin and a low reference voltage Vrefh or a high reference voltage Vrefh via a corresponding switch. Specifically, the input voltage Vin can be selectively applied to the top plate of the capacitor array 42 via an input switch 41, which can be activated by asserting an input control signal. In addition, each capacitor bottom plate (e.g., 4C) can be coupled to Vrefh by asserting a corresponding control bit (e.g., b2) to turn on a corresponding Vrefh switch, or can be coupled to Vrefl by deasserting a corresponding control bit (e.g., b2) to turn on a corresponding Vrefl switch. The top plate of each capacitor in the capacitor array 42 can be coupled to provide a Vdac signal directly to a comparator input. A first portion of the capacitor array 42 having a larger capacitance value (e.g., 1024C, 2048C) corresponds to the most significant bit (MSB) of the DAC 40, and a second portion of the capacitor array 42 having a smaller capacitance value (e.g., C, 2C ...) corresponds to the least significant bit (LSB) of the DAC40.

[0039] One of the main limiting factors for linearity in SAR ADC design is DAC element matching. There are many techniques to improve matching, including calibration methods and dynamic element matching methods. However, these techniques are usually performed only on the MSB because the required logic becomes too large for a full array of high-resolution ADCs. Another method to improve the linearity of the rest of the ADC (LSB capacitor matching) is the mismatch error shaping (MES) method. In this method, the LSB result of the previous conversion is sampled for the current conversion by connecting the LSB capacitor bottom plate to Vrefh / Vrefl during the sampling phase, depending on its result from the previous successive approximation (SAR) phase. For the top plate sampling MES method, there is an extra "stage" at the end of sampling, where these LSBs are switched to Vrefl before starting the SAR conversion phase. The result is then digitally adjusted to subtract the previous LSB result. Mathematically, this produces a 1st order shaping of the LSB capacitor mismatch. However, the main drawback of this method is that it reduces the input range of the ADC. Although there are ways to restore this input range, these ways increase the complexity and cost of SAR ADC design.

[0040] To provide a contextual understanding of the present disclosure, reference is now made to Figure 5A -C, which depicts an exemplary sampling, injection, and conversion phases of a mismatch error shaping sequence for use with a top-plate sampling SAR ADC. Specifically, Figure 5A The sampling phase is depicted, where the input voltage Vin is connected to the top sampling plate, which is directly connected to the comparator input Vdac (e.g., Vin=Vdac). At this time, only the most significant bit (MSB) [N] is reset, and the less significant bits [N-1][N-2] are set to 1V and 0V, respectively, as part of the mismatch error shaping of these bits (as indicated by the dashed box 51).

[0041] like Figure 5B As depicted, when the input voltage sampling switch 52 is opened causing the Vdac node to float, the sampling phase is completed, after which the injection phase begins. During the injection phase, the DAC is pushed into a reset state by resetting the bottom capacitor (indicated by the dashed box 53) for the less significant bit [N-1][N-2] to 0V and setting the top capacitor (indicated by the dashed box 54) for the less significant bit [N-1][N-2] to 1V. This produces an additional voltage E on the floating Vdac node. [n-1] , which represents the previous sample E [n-1] In other words, the comparator input voltage Vdac = -Vin + Vlsb[n-1].

[0042] like Figure 5C As depicted, the conversion phase begins, which uses the comparator input voltage Vdac=Vdac-Vin+Vlsb[n-1] to perform a binary SAR algorithm for converting the analog voltage into a digital voltage. During the conversion phase, the ADC sample N includes the digitally corrected residual E of the previous conversion. [n] , leaving behind an analog error due to the remaining mismatch with the previous sample. This is essentially 1st order mismatch shaping where the voltage input signal Vin is oversampled and the mismatch is pushed to a higher frequency and filtered out, resulting in improved total harmonic distortion performance.

[0043] To provide a contextual understanding of the present disclosure, reference is now made to Figure 6, which depicts a simplified circuit schematic of a 12-bit DAC 60 for a bottom-plate sampling SAR ADC. The depicted DAC 60 includes a capacitor array 62, including a first terminal capacitor having a unit capacitance value C, and 12 additional capacitors corresponding to bits b0-b11, each having a binary weighted capacitance, starting with a first capacitor having a capacitance of C, a second capacitor having a capacitance of 2C, and continuing until a 12th capacitor having a capacitance of 2048C. Each top plate of the capacitor array 62 is connected by a switch 61 to be driven to a common mode voltage Vcm during a sampling phase, while an analog input signal Vin is applied to the capacitor bottom plate using a switching circuit system 63. In addition to receiving the analog input signal Vin, the switching circuit system 63 also receives a high voltage reference Vrefh and a low voltage reference Vrefl, and each of these signals is coupled to a selected number of binary weighted capacitors 62 in response to a DAC control signal. In particular, each of the switching circuits 63 connected to the binary weighted capacitors 62 can be individually and selectively manipulated to select any of the three signals in response to the DAC control signal. As can be seen from the foregoing, the fact that the analog input signal Vin is sampled on the bottom plates of all capacitors means that the mismatch error shaping technique cannot be used with a bottom plate sampling SAR ADC because the Vrefh and Vrefl voltages cannot be sampled on the LSB capacitors since the bottom plates of the LSB capacitors are being used for sampling.

[0044] To provide a contextual understanding of the present disclosure, reference is now made to Figure 7, which shows a simplified circuit schematic of a segmented DAC 70 that can be connected to a comparator as part of a backplane sampling SAR ADC. The depicted segmented DAC 70 includes a capacitor array 72, including a first terminal capacitor having a unit capacitance value C, and 12 additional capacitors corresponding to bits b0-b11 that are segmented into different capacitor sub-arrays or segments. In addition, the depicted capacitor array 72 includes attenuation or scaling capacitors Csc1, CSc2, which are included to split the array into multiple array portions or segments, including an LDAC array (for the least significant bits, BITS<3:0>), an INT-DAC array (for the middle significant bits, BITS<7:4>), and an MDAC array (for the most significant bits, BITS<11:8>). In particular, the capacitors corresponding to the LDAC array correspond to bits 0-3 and each have a binary weighted capacitance, starting with a bit 0 capacitor having a unit capacitance of C, followed by a bit 1 capacitor having a unit capacitance of 2C, a bit 2 capacitor having a unit capacitance of 4C, and a bit 3 capacitor having a unit capacitance of 8C. Similarly, the capacitors corresponding to the INT-DAC array correspond to bits 7-4 and each have a binary weighted capacitance, starting with the bit 4 capacitor having a unit capacitance of C, followed by the bit 5 capacitor having a unit capacitance of 2C, the bit 6 capacitor having a unit capacitance of 4C, and the bit 7 capacitor having a unit capacitance of 8C. Finally, the capacitors corresponding to the MDAC array correspond to bits 11-8 and each have a binary weighted capacitance, starting with the bit 8 capacitor having a unit capacitance of C, followed by the bit 9 capacitor having a unit capacitance of 2C, the bit 10 capacitor having a unit capacitance of 4C, and the bit 11 capacitor having a unit capacitance of 8C. Although the capacitors in the segmented DAC 70 are shown as binary weighted capacitors for simplicity, it will be appreciated that any suitable grouping and / or decoding method may be used.

[0045] Each capacitor in array 72 is connected through switching circuit 71 to charge the top plate of each MSB capacitor to a common mode voltage (Vcm). In addition, in response to a DAC control signal supplied to switching circuit 73, the bottom plate of capacitor 72 is connected to a high reference voltage Vrefh, a low reference voltage Vrefl, or an analog input voltage Vin through switching circuit 73, where Vrefl≤Vin≤Vrefh. Although not shown, the DAC control circuit system provides a gating control signal to switch 73 to connect the bottom plate of capacitor array 72 to Vrefl, Vrefh, and Vin signals as needed based on the current operation (e.g., the sampling or comparison phase of the conversion). The operation of the DAC control circuit system relative to normal sampling and conversion operations is known in the art and will not be discussed in full detail. In summary, the analog input voltage Vin is first sampled during the sampling phase when each of the MSB capacitor top plates is charged to the common mode voltage Vcm, and then the analog input voltage Vin is sampled by setting the bottom capacitor plate to Vin. Since Vrefh>Vrefl, setting the bottom capacitor plate to Vrefh can be referred to as turning the capacitor on, and setting the bottom capacitor plate to Vrefl can be referred to as turning the capacitor off.After the sampling phase, the comparison or conversion phase is initiated, where each result bit value is again determined by a comparator and digital SAR logic block (not shown).

[0046] By using scaling capacitors Cs1, Csc2 to separate the array 72 into array segments LDAC, INT-DAC, MDAC, the overall capacitance, size, power consumption, and RC time constant of the capacitor array 72 are reduced compared to a non-segmented capacitor array. In particular, the depicted example of a segmented 4-4-4 12b DAC capacitor array for backplane sampling ADC 70 requires only 48 capacitor elements, while a full 12b DAC capacitor array (e.g., Figure 6 ) requires 4096 capacitor elements. However, there are disadvantages that come with segmenting the DAC capacitor array 72. For example, the scaling capacitors (Csc1, Csc2) can degrade the element matching in the DAC 70 because the scaling capacitors are typically not unit-sized. In addition, mismatch error shaping cannot be performed for this backplane sampling configuration because all capacitor array elements 72 are used to sample the analog input voltage Vin.

[0047] In order to provide a detailed understanding of selected embodiments of the present disclosure, reference is now made to Figure 8 , which shows the MES sampling capacitor C for the specified MES 1 is a simplified circuit diagram of a DAC 80 of a backplane sampling SAR ADC. The depicted DAC 80 includes a capacitor array 82 including a plurality of additional capacitors corresponding to bits b0-b11, and an additional MES sampling capacitor CMES , the additional MES sampling capacitor is located at a specified position in the capacitor array 82 for providing mismatch error shaping (MES) from the less significant capacitors in the capacitor array 82 such that input voltage sampling occurs only on the more significant capacitors in the capacitor array 82. In a selected embodiment, the DAC 80 includes attenuation or scaling capacitors Csc1, CSc2, which are included to split the capacitor array 82 into multiple array portions or segments, including an LDAC array (for the least significant bits, BITS <3:0>), an INT-DAC array (for the intermediate significant bits, BITS <7:4>), and an MDAC array (for the most significant bits, BITS <11:8>). In such embodiments, the capacitors in each array segment may have binary weighted capacitance values, starting with a first bit capacitor having a unit capacitance C, then a second bit capacitor having a unit capacitance of 2C, a third bit capacitor having a unit capacitance of 4C, and a fourth bit capacitor having a unit capacitance of 8C. However, in other embodiments, non-binary capacitor grouping may be used.

[0048] Each capacitor in the array 82 is connected via a switching circuit 81 to charge the top plate of each MSB capacitor to the common mode voltage (Vcm). Additionally, in response to DAC control signals supplied to the switching circuit 83, the bottom plates of the capacitors 82 in the LDAC array and the INT-DAC array are connected via the switching circuit 83 to a high reference voltage Vrefh or a low reference voltage Vrefl, where Vrefl < Vrefh. However, in response to DAC control signals supplied to the switching circuit 84, the bottom plates of the capacitors 82 in the MDAC array are connected via the switching circuit 84 to the high reference voltage Vrefh, the low reference voltage Vrefl, or the analog input voltage Vin, where Vrefl < Vrefh. Although not shown, the DAC control circuitry provides gating control signals to the switches 83, 84 to connect the bottom plates of the capacitor array 82 to the Vrefl, Vrefh, and Vin signals as needed based on the current operation (e.g., sampling or comparison phases of a conversion).

[0049] In Figure 8 the example depicted, the most significant DAC array (MDAC) also includes a single capacitor C MES, as an additional capacitor bit to effectively sample the equivalent charge of all lower effective capacitor bits (e.g., BITS<0:7>). In this configuration, the analog input voltage Vin is sampled only on the most effective capacitor bit (e.g., BITS<11:8>), thereby enabling the lower effective capacitor bits (e.g., BITS<0:7>) to be used for mismatch error shaping. After each conversion, the resulting bit values ​​7:0 of ​​the converted digital result value are applied during sampling of the next ADC conversion (e.g., a bit value of "1" in the digital result value means that Vrefh is selected on the backplane during sampling, and a bit value of "0" in the digital result value means that Vrefl is selected on the backplane during sampling). Subsequently, just before the SAR starts the next conversion, the backplane of 7:0 is all switched to Vrefl. When the SAR completes and realizes the conversion result, the value of 7:0 applied during sampling is digitally subtracted from the result. This will provide first order shaping of the mismatch of the less significant capacitor bits (e.g., BITS<0:7>) in a similar manner to the top plate sampling version depicted in Figure 5. In fact, it also shapes the mismatch error of the scaling capacitors Csc1, Csc2, which are difficult to match because they are typically of non-unit size.

[0050] As described above, one of the known problems from using mismatch error shaping is the loss of input range. However, including a single additional capacitor to the MDAC array can be used to restore or recover the lost input range caused by performing mismatch error shaping. This is done by using an additional bit as the equivalent of a BIT during the successive approximation (SAR) phase. <8> This is achieved by adding redundant bits. This increases the range to just enough to recover even the maximum possible LSB value (BITS<7:0>=$FF) that is being sampled during mismatch error shaping to allow accurate approximation of input voltages throughout the entire range (Vrefl to Vrefh) while performing mismatch error shaping. Another advantage of the additional capacitors is that gain errors can be eliminated by using the additional capacitors to sample the input. Yet another and additional possible benefit from the additional capacitors is that the circuit generating the analog input voltage Vin experiences more uniform parasitic capacitance because it only drives the MDAC array and does not drive the sampling capacitors in the LDAC array and INT-DAC array that have parasitic capacitance values ​​that are not commensurate with the bits because the bottom plate is not scaled by the scaling capacitors Csc1, CSc2.

[0051] like Figure 8 As shown in MES Located in the LSB position of the MDAC array. This has the advantage of using only a single unit capacitance value C for the sampling capacitor C MES However, it will be appreciated that the additional capacitor C MESThe capacitors C may be located in other locations in the MDAC array or capacitor array 82, but they will need to be sized to provide mismatch error shaping (MES) from the lower effective capacitors in the capacitor array 82 and to provide dynamic element matching or other calibration on the additional capacitors and the higher effective capacitors. MES can be located in a more significant bit position (e.g., next to a 2C capacitor in an MDAC array), provided that the additional capacitor C MES The size of is at least as large as the sum of the lower effective capacitors.

[0052] In addition to including additional capacitors C in the segmented DAC capacitor array 82 MES In addition, an additional capacitor C may be included with a non-segmented DAC capacitor array that does not include a bridge capacitor (eg, Csc1, Csc2). MES In such a non-segmented DAC embodiment, the capacitor array would include additional capacitor elements (eg, 4096 capacitors instead of 48 capacitors), and the additional capacitors C MES will need to be positioned and appropriately sized to have a capacitance value equal to the sum of all the less significant capacitors so that mismatch error shaping can be performed on the less significant bit capacitors. For example, a standard 12b non-segmented DAC may include an additional capacitor C immediately adjacent to bit position BIT=9. MES , in this case the additional capacitor C MES Capacitance value = 512C.

[0053] In order to provide additional details for improving the understanding of the selected first embodiment of the present disclosure, reference is now made to Fig. 9 , which depicts a simplified flow chart 90 showing logic for operating a backplane sampling SAR ADC including a specified MES sampling capacitor to perform mismatch error shaping of selected least significant bits. In an exemplary embodiment, Fig. 9 The processing shown in can be performed at a SAR ADC having a SAR engine implemented in dedicated hardware, software, or a hybrid implementation and configured to control the SAR DAC and the comparator with a feedback control signal that feeds back the mismatch error from the previous conversion cycle to the LSB capacitor so that the additional capacitors in the MSB segment can be used to perform mismatch error shaping during the current sampling phase.

[0054] The method begins at step 91 with control logic and / or hardware at the SAR engine being configured to initiate a bottom plate sampling phase of the analog input voltage on the MSB capacitor and the design MES sampling capacitor while the LSB capacitor bottom plate receives the LSB mismatch error code from the previous sampling phase (step 92). Figure 3 and8 In the example shown in , SAR control logic 35 may be used to generate a sampling DAC control feedback signal that initiates a sampling phase at DAC 31 by connecting the analog input voltage Vin to the bottom capacitor plate while the common mode voltage Vcm is connected to the top capacitor plate.

[0055] At step 93, the bottom plate sampling phase ends. Figure 3 and 8 In the example shown in FIG. 1 , the control logic and / or hardware at the SAR engine 35 can be configured to end the bottom plate sampling phase at the DAC 31 by resetting the sampling DAC control feedback signal to disconnect the analog input voltage Vin from the bottom capacitor plate and disconnect the common mode voltage Vcm from the top capacitor plate.

[0056] At step 94, the DAC injection phase is initiated by resetting the LSB capacitors in the DAC array. Figure 3 and 8 In the example shown in FIG. 4 , control logic and / or hardware at the SAR engine 35 may be configured to initiate the DAC injection phase by switching the bottom capacitor plate of the DAC array to a lower reference voltage Vref1, effectively resetting the LSB capacitor.

[0057] At step 95, a conversion phase is initiated at the comparator for the current bit, starting with the most significant bit. Figure 3 and 8 In the example shown in , the control logic and / or hardware at the SAR engine 35 may be configured to initiate a conversion phase by generating a clock signal for feedback to the comparator to initiate a conversion phase for the current bit.

[0058] At step 96, the conversion phase ends at the comparator for the current bit. Figure 3 and 8 In the example shown in , the control logic and / or hardware at the SAR engine 35 may be configured to end the conversion phase by generating a latch signal for feedback to the comparator to capture the comparator result for the current bit.

[0059] At step 97, the SAR engine updates the DAC control value based on the comparator result. Figure 3 and 8 In the example shown in , the control logic and / or hardware at the SAR engine 35 may be configured to update the DAC control value by storing the comparison result in the SAR register 36 .

[0060] At step 98, a determination is made as to whether the DAC control value for the least significant bit (LSB) has been captured. If not (negative outcome to decision 98), the next most significant bit is selected or incremented (step 99), and steps 95 through 98 are iteratively repeated until the DAC control code for the least significant bit is updated (affirmative outcome to decision 98), at which time the current LSB result is captured for use as the mismatch error code for the next sampling phase (step 100), and the SAR result from the current sampling phase is reduced by subtracting the previously captured LSB result (step 101). Figure 3 and 8 In the example shown in , control logic and / or hardware at the SAR engine 35 may be configured to digitally subtract a previous conversion LSB value (previous mismatch error code) from the complete SAR result stored in the SAR register 36 .

[0061] At step 102, the process ends.

[0062] As disclosed herein, the disclosed methods, systems, and apparatus for performing bottom-plate sampling SAR ADC conversions may be implemented with a successive approximation register engine implemented in dedicated hardware, software, or hybrid implementations and connected and controlled by a control logic and / or computer program product having program code portions for performing the steps of the method and / or for performing the functions of the device or system, wherein designated additional capacitors in a multi-bit capacitor array are used to provide mismatch error shaping (MES) from lower effective capacitors in the multi-bit capacitor array such that input voltage sampling occurs only on higher effective capacitors in the multi-bit capacitor array. Although the embodiments are described in the context of using an exemplary SAR engine to control a multi-bit bottom sampling capacitor array that uses designated MES sampling capacitors to perform mismatch error shaping on lower effective capacitor bits, the proposed bottom-plate sampling SAR ADC calculation methods, systems, and apparatus may use any desired configuration of control logic, latches, and registers to perform mismatch error shaping on designated MES sampling capacitors. For example, although Figure 8 The discussion thereof describes an exemplary SAR ADC architecture including a segmented DAC array, but this exemplary architecture is presented only to provide a useful reference when discussing various aspects of the present invention. Of course, for the purpose of discussion, the description of the architecture has been simplified, and it is only one of many different types of suitable architectures that can be used according to the present invention.

[0063] Those skilled in the art will recognize that the boundaries between logic blocks and circuit elements are merely illustrative, and alternative embodiments may merge logic blocks or circuit elements, or impose alternative decompositions of functionality on various logic blocks or circuit elements. Therefore, it should be understood that the architectures depicted herein are merely exemplary, and in fact, many other architectures that implement the same functionality may be implemented. In an abstract but still clear sense, any arrangement of components for implementing the same functionality is effectively "associated" so that the desired functionality is achieved. Therefore, any two components combined herein to achieve a particular functionality may be considered to be "associated" with each other so that the desired functionality is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated may also be considered to be "operably connected" or "operably coupled" to each other to achieve the desired functionality. In addition, those skilled in the art will recognize that the boundaries between the functionality of the operations described above are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed in other operations. In addition, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may change in different other embodiments.

[0064] Various illustrative embodiments of the present invention have been described in detail with reference to the accompanying drawings. Although various details are set forth in the foregoing description, it should be understood that the present invention can be practiced without these specific details, and many specific implementation decisions can be made for the present invention described herein to achieve the specific goals of the circuit designer, such as compliance with process technology or related design restrictions, which vary from one embodiment to another. Although such research and development work may be complex and time-consuming, it is nothing more than a routine task for ordinary technicians in the field who benefit from the present disclosure. For example, in order to avoid limiting or confusing the present invention, selected aspects are shown in block diagram form rather than in detail. In addition, some parts of the detailed description provided herein are presented in terms of algorithms or operations of data in a computer memory. Such descriptions and representations are used by technicians in the field to describe and convey the essence of their work to other technicians in the field. Although the described exemplary embodiments disclosed herein relate to an exemplary SAR engine, the present invention is not necessarily limited to the exemplary embodiments shown herein, and various embodiments of the circuit system and method disclosed herein can be implemented with other devices and software components. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limiting the present invention, because the present invention can be modified and implemented in different but equivalent ways, which are obvious to those skilled in the art who benefit from the teachings herein. Accordingly, the above description is not intended to limit the present invention to the specific forms set forth, but on the contrary it is intended to cover such alternatives, modifications and equivalents as may be included in the spirit and scope of the present invention as defined by the appended claims, so that those skilled in the art should understand that they can make various changes, substitutions and modifications in its broadest form without departing from the spirit and scope of the present invention.

[0065] The benefits, other advantages, and solutions to problems are described above with respect to specific embodiments. However, those benefits, advantages, solutions to problems, and any elements that may cause any benefit, advantage, or solution to occur, or become more significant, shall not be construed as key, required, or essential features or elements of any or all claims. As used herein, the term "comprises" or any other variation thereof is intended to encompass non-exclusive inclusions, such that a process, method, article, or device that includes a list of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device.

Claims

1. A successive approximation register SAR analog / digital converter ADC, characterized in that: include: A digital-to-analog converter DAC is connected and configured to generate an output voltage from a DAC feedback control signal, the segmented DAC comprising: a plurality of most significant bit MSB capacitors having bottom and top capacitor plates, a plurality of least significant bit LSB capacitors having bottom and top capacitor plates, a mismatch error shaping capacitor having bottom and top capacitor plates, wherein the mismatch error shaping capacitor is connected in a bit position between the plurality of LSB capacitors and the plurality of MSB capacitors, a first set of switches to couple the plurality of MSB capacitors and the bottom capacitor plate of the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to a first DAC feedback control signal, wherein the high reference voltage is greater than the low reference voltage, and a second set of switches to couple the bottom capacitor plate of the plurality of LSB capacitors to receive the high reference voltage or the low reference voltage in response to a second DAC feedback control signal; a comparator having a first input coupled to receive the output voltage from the DAC, a second input, and a comparison output based on a voltage difference between the first input and the second input; and a successive approximation register (SAR) circuitry having an input coupled to receive the comparison output, and an output to provide a digital value corresponding to a digital representation of the analog input voltage, wherein the SAR circuitry is configured to feed back a mismatch error value from a previous SAR conversion cycle to the plurality of LSB capacitors during a current sampling cycle via the second DAC feedback control signal provided to the second set of switches.

2. The SAR ADC according to claim 1, wherein: The DAC comprises a segmented DAC including a scaling capacitor having a first scaling capacitor plate and a second scaling capacitor plate, wherein the first scaling capacitor plate is connected to the top capacitor plate of the plurality of MSB capacitors and the second scaling capacitor plate is connected to the top capacitor plate of the plurality of LSB capacitors, and wherein the top capacitor plate of the mismatch error shaping capacitor is connected to the first scaling capacitor plate and the top capacitor plate of the plurality of MSB capacitors.

3. The SAR ADC according to claim 1, wherein: The second set of switches couples the bottom capacitor plate of the LSB capacitor to receive a high reference voltage or the low reference voltage corresponding to the mismatch error value from the previous SAR conversion cycle in response to the second DAC feedback control signal.

4. The SAR ADC according to claim 1, wherein: The SAR circuitry is configured to control the second set of switches to couple the bottom capacitor plates of the plurality of LSB capacitors to the low reference voltage between each sampling cycle and each subsequent conversion cycle.

5. The SAR ADC according to claim 1, wherein: The SAR circuitry is configured to subtract a mismatch error value from a predetermined number of least significant bits corresponding to the plurality of LSB capacitors from the digital value at each conversion cycle to produce a final digital representation of the analog input voltage, wherein the mismatch error value is determined during a previous conversion cycle.

6. A method in a successive approximation register SAR analog-to-digital converter ADC, characterized in that: The method comprises: providing an analog input voltage and a mismatch error shaping code voltage value to a split capacitor digital-to-analog converter DAC, the split capacitor digital-to-analog converter comprising an MSB sub-DAC having one or more most significant bits MSB encoded with one or more first capacitors, an LSB sub-DAC having one or more least significant bits LSB encoded with one or more second capacitors, a mismatch error shaping capacitor coupled to the MSB sub-DAC, and a scaling capacitor coupled between the LSB sub-DAC and the MSB sub-DAC; initiating backplate sampling of the analog input voltage on the first capacitor and the mismatch error shaping capacitor of the MSB sub-DAC, wherein the one or more second capacitors of the LSB sub-DAC receive a mismatch error shaping code voltage value; Ending the bottom plate sampling of the analog input voltage; initiating an injection phase by resetting the one or more second capacitors of the LSB sub-DAC; performing a comparison using an output of the split capacitor DAC to provide a comparison output for a current SAR ADC conversion cycle; performing successive approximation on the comparison output to provide a digital value representing an input voltage to the split capacitor DAC; capturing a current LSB result from the digital value for use in a subsequent SAR ADC conversion cycle; and Mismatch error shaping is performed on the digital value by subtracting the LSB result captured from the previous SAR ADC conversion cycle from the digital value.

7. The method according to claim 6, characterized in that Initiating bottom plate sampling includes connecting a common mode voltage to the first capacitor of the MSB sub-DAC and a top capacitor plate of the mismatch error shaping capacitor.

8. The method according to claim 6, characterized in that Initiating the injection phase includes connecting a low reference voltage to a bottom capacitor plate of the split-capacitor DAC, the connection resetting the one or more second capacitors of the LSB sub-DAC.

9. A successive approximation register analog-to-digital converter ("SAR ADC"), characterized in that include: a first digital-to-analog converter ("DAC") configured to receive a first input voltage signal, a high voltage reference, and a low voltage reference and to generate a first DAC output from the first input voltage signal, the high voltage reference, and the low voltage reference, wherein the first DAC includes a first MSB sub-DAC having one or more most significant bits, MSBs, encoded with one or more first capacitors, a first LSB sub-DAC having one or more least significant bits, LSBs, encoded with one or more second capacitors, and a first mismatch error shaping capacitor coupled to the first MSB sub-DAC; a second DAC configured to receive a second input voltage signal, the high voltage reference, and the low voltage reference and to generate a second DAC output from the second input voltage signal, the high voltage reference, and the low voltage reference, wherein the second DAC includes a second MSB sub-DAC having one or more most significant bits MSB encoded with one or more first capacitors, a second LSB sub-DAC having one or more least significant bits LSB encoded with one or more second capacitors, and a second mismatch error shaping capacitor coupled to the second MSB sub-DAC; a differential comparator having a first input coupled to receive the first DAC output from the first DAC, a second input coupled to receive the second DAC output from the second DAC, and a comparator output, the differential comparator being configured to produce a differential comparison of the first DAC output and the second DAC output at the comparator output; as well as a successive approximation register (SAR) circuitry having an input coupled to receive the comparator output, wherein the SAR circuitry is configured to provide a digital value corresponding to a digital representation of a difference between a first analog input voltage and a second analog input voltage, wherein the SAR circuitry is further configured to feed back a control signal to the first DAC and the second DAC to: initiating a first DAC bottom plate sampling of the first analog input voltage on the first capacitor and the first mismatch error shaping capacitor of the first MSB sub-DAC while the one or more second capacitors of the first LSB sub-DAC receive a first mismatch error shaping code voltage value; initiating second DAC bottom plate sampling of the second analog input voltage on the first capacitor and the second mismatch error shaping capacitor of the second MSB sub-DAC while the one or more second capacitors of the second LSB sub-DAC receive a second mismatch error shaping code voltage value; End the first DAC bottom plate sampling and the second DAC bottom plate sampling of the first analog input voltage and the second analog input voltage; initiating an injection phase in the first DAC and the second DAC by resetting the one or more second capacitors of the first LSB sub-DAC and the second LSB sub-DAC; performing a differential comparison of the first DAC output and the second DAC output to provide the differential comparison output of a current SAR ADC conversion cycle at the comparator output; performing successive approximation on the differential comparison to provide the digital value; capturing a current LSB result from the digital value for use in a subsequent SAR ADC conversion cycle; as well as Mismatch error shaping is performed on the digital value by subtracting the LSB result captured from the previous SAR ADC conversion cycle from the digital value.

10. The SAR ADC according to claim 9, characterized in that: The one or more first capacitors of the first MSB sub-DAC and the second MSB sub-DAC and the one or more second capacitors of the first LSB sub-DAC and the second LSB sub-DAC are each encoded with one or more binary capacitors, respectively; wherein the first DAC includes a first termination capacitor coupled to the first LSB sub-DAC; and Wherein the second DAC includes a second termination capacitor coupled to the second LSB sub-DAC.

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