Verilog-based multi-code-rate LDPC encoder and encoding method under CCSDS standard

Abstract

The invention provides a Verilog-based multi-code-rate LDPC (Low Density Parity Check) encoder under a CCSDS (Consultative Committee for Space Data System) standard and an encoding method, belongs to the technical field of information encoding, and solves the problems that the storage space of the LDPC encoder is wasted and the consumption of matrix resources stored and generated by the encoder is high. The LDPC encoder comprises a control module, a storage module, a cyclic shift module, a check bit calculation module and a code word register module. According to the multi-code-rate LDPC code encoder, the flexibility of the LDPC code encoder is improved by achieving design and construction of the multi-code-rate LDPC code encoder, encoding can be achieved in practical application more easily, meanwhile, the storage space of the LDPC code encoder can be saved, storage resources can be saved, and implementation of a satellite encoder in a deep space environment is facilitated.

Description

Technical Field

[0001] The invention relates to a Verilog-based multi-code rate LDPC encoder and an encoding method under the CCSDS standard, and belongs to the technical field of information encoding. Background Art

[0002] CCSDS (Consultative Committee for Data Systems) is committed to building the specifications of space communication data processing systems. At present, its communication standards have been used by many countries in the world. In 2007, the CCSDS committee included LDPC codes in the CCSDS standard. LDPC codes are a kind of linear block codes with sparse check matrices with extremely superior performance. Under the condition of using iterative decoding algorithms based on belief propagation, they have good performance close to the Shannon limit. The sparse check matrix makes the decoding complexity low.

[0003] In the field of satellite communications, the conditions of hardware resources and energy are extremely harsh, and it is difficult to bear excessive resource consumption. For example, in deep space communications, the standard 131.1-0-2 recommended by CCSDS covers 9 codewords, with the shortest code length being 1280 and the longest being 32768. When the code length is long, if the encoding method of directly multiplying the information bit and the generator matrix is ​​used, its complexity will increase quadratically with the code length, which will consume a lot of hardware resources in engineering practice. Summary of the invention

[0004] The present invention solves the problem of waste of storage space of LDPC code encoder and high consumption of encoder storage generation matrix resources, and further proposes a Verilog-based multi-rate LDPC encoder and encoding method under the CCSDS standard, wherein the LDPC encoder includes:

[0005] Control module, storage module, cyclic shift module, check bit calculation module and codeword register module;

[0006] The control module sends corresponding control signals to the storage module and the check bit calculation module according to the code rate RATE input by the encoder;

[0007] The storage module is used for storing the row generators of the code rate RATE generation matrix and providing them to the circular shift register;

[0008] The cyclic shift module is used to select the corresponding cyclic shift register according to the row generator of the code rate matrix input by the control module, generate the matrix information of the matrix cyclic sub-matrix, and pass the matrix information to the check bit calculation module after cyclic shift;

[0009] The check bit calculation module performs check bit calculation, and after all the check bits are calculated, they are passed to the code word register;

[0010] After the codeword register module calculates the check bit, the MK-bit information source in the matrix is ​​concatenated with the 2M-bit check bit to output the codeword w.

[0011] Preferably, the internal data of the storage module are row generators of three code rate generation matrices of 1024-bit LDPC codes, including a 1 / 2 code rate generation matrix, a 2 / 3 code rate generation matrix, and a 4 / 5 code rate generation matrix;

[0012] The 2 / 3 code rate generation matrix is ​​a rectangle, located in the lower left corner of the storage module generation matrix, with a width of 512 bits and a depth of 16. The 4 / 5 code rate generation matrix is ​​located on the right side of the 2 / 3 code rate generation matrix, with a width of 512 bits and a depth of 32. The 4 / 5 code rate generation matrix includes two completely identical 4 / 5 code rate sub-generation matrices, and the width of the 4 / 5 code rate sub-generation matrix is ​​256 bits. The 1 / 2 code rate generation matrix is ​​located above the 2 / 3 code rate generation matrix and the 4 / 5 code rate generation matrix, with a width of 1024 bits.

[0013] Preferably, the cyclic shift module includes a 128-bit cyclic shift register, a 68-bit cyclic shift register and a 32-bit cyclic shift register, and the 128-bit cyclic shift register, the 68-bit cyclic shift register and the 32-bit cyclic shift register are all 0 when reset.

[0014] The encoding method of the Verilog-based multi-rate LDPC encoder under the CCSDS standard includes:

[0015] Step 1: Input the clock signal clk, reset signal rst, information sequence u(i) and code rate RATE into the LDPC encoder;

[0016] Step 2: Input the clock signal clk, reset signal rst, information sequence u(i) and code rate RATE as en_in signal to the control module. By analyzing the code rate RATE, the LDPC encoder enters the encode state. Different code rates RATE enter the encode state to generate en_out12 signal, en_out23 signal and en_out45 signal. The en_out12 signal indicates that the code word is 1 / 2 code rate and enters the 1 / 2 code rate partial encoding; the en_out23 signal indicates that the code word is 2 / 3 code rate and enters the 2 / 3 code rate partial encoding; the en_out45 signal indicates that the code word is 4 / 5 code rate and enters the 4 / 5 code rate partial encoding. The working order of all modules in the LDPC encoder is determined according to the clock signal clk. The control module sends an en_rom enable signal to the cyclic shift module and an enmul enable signal to the check bit calculation module according to the code rate RATE input by the encoder.

[0017] Step 3: The storage module receives the en_rom enable signal, stores the row generators of the code rate RATE generation matrix and provides a circular shift register;

[0018] Step 4: The cyclic shift module receives the row generator of the code rate matrix input by the control module, generates matrix information of the matrix cyclic sub-matrix, and passes the matrix information to the check bit calculation module after cyclic shift;

[0019] Step 5: After receiving the enmul enable signal, the check bit calculation module performs check bit calculation. After a single calculation, it is reset by the reset signal rst and repeats steps 3-4 until all check bits are calculated. After all check bits are calculated, they are passed to the code word register.

[0020] Step 6: After the calculation is completed, the en_finish signal is set to a high level, the LDPC encoder enters the out state, and the codeword register module calculates the check bit, and then splices the MK-bit information source in the matrix with the 2M-bit check bit to output the codeword w.

[0021] Preferably, in step 2, the control module sends corresponding control signals to the cyclic shift module, the check bit calculation module and the codeword register module according to the code rate RATE input by the encoder, including:

[0022] The control module transmits the start bit of the storage module's read address according to the code rate RATE input by the encoder, and transmits the enable signal from the circular shift register module to the storage module at the same time. The control module selects the corresponding shift register in the circular shift module to work according to the code rate RATE, and transmits the enable signal from the circular shift register module to the check bit calculation module. The control module transmits the check bit calculation completion signal of the check bit calculation module as the enable signal output by the code word register, wherein the enable signal output by the code word register is the encoded code word sequence.

[0023] Preferably, step 3 specifically includes:

[0024] The code rate RATE generator matrix is ​​divided into blocks in the form of its own block cyclic submatrix, and the first row of the generator matrix cyclic submatrix is ​​stored. Then, each block cyclic generator matrix submatrix is ​​traversed in a block cyclic manner. For a generator matrix with 1024 information bits, each code rate needs to store 8192-bit values; for a generator matrix with 4096 information bits, a 32768-bit value needs to be stored; for a generator matrix with 16384 information bits, a 131072-bit value needs to be stored. The generator matrix G under the CCSDS standard is [I MK×MK W MK×3M ], the first MK bits of the generated codeword are the original information source, and the unit matrix I on the left MK×MKNo storage is performed. The generated complete check digit has 3M bits. The last M bits are punctured and not transmitted. The matrix W on the right is MK×3M Only the first W needs to be stored MK×2M The generator matrix under the CCSDS standard has a cyclic structure, which only stores the first row of each cyclic submatrix. The remaining rows can be obtained by cyclic shifting the first row. The order of the cyclic submatrix of the generator matrix is ​​M / 4. The W of each generator matrix MK×2M There are 32K circulant sub-matrices in total, and it is necessary to store the element values ​​of the generator matrix of 32K×M / 4=8k bits, where k is the number of information bits;

[0025] The expression for generating the matrix is:

[0026]

[0027] In formula (1), W i,j is a circulant matrix of size M / 4. When the code rate R=1 / 2, K is equal to 2; when R=2 / 3, K is equal to 4; when R=4 / 5, K is equal to 8.

[0028] Preferably, the code rate RATE of the cyclic submatrix in step 4 adopts a parallel coding structure, including three code rates: 1 / 2 code rate, 2 / 3 code rate and 4 / 5 code rate. The 1 / 2 code rate is binary 00 input, and 8 information bits are encoded in parallel at the 1 / 2 code rate. The 2 / 3 code rate is binary 01 input, and 4 information bits are encoded in parallel at the 2 / 3 code rate. The 4 / 5 code rate is binary 10 input, and 2 information bits are encoded in parallel at the 4 / 5 code rate.

[0029] Preferably, in step 4, the internal state of the cyclic shift module includes a start state, an input state, an assign state, a shift state and an output state, wherein the start state indicates the start of the cyclic shift operation, the input state indicates receiving information from the storage module, the assign state transmits the row generator to the check bit calculation module, the shift state indicates performing the cyclic shift, and the output state transmits an enable signal of the check bit calculation module;

[0030] In the start state, set State = 00, enter the input state, pass the en_rom signal to 1 to the storage module as an enable, and let it send the row generator. After receiving the row generator, pass it to shift_data, and set State = 01 to enter the assign state.

[0031] In the assign state, set en_rom=0; pass the value of shift_data to data as the generator matrix signal output to the check bit calculation module, and set State=11 to enter the output state.

[0032] In the output state, enmul=1 is set as the enable signal of the check bit calculation module, where Num plus 1 indicates that the data has been transmitted once, and State=10 is set to enter the shift state.

[0033] In the shift state, the value of Num is determined. If the value of Num is less than L, L=16 indicates that a circulant submatrix has not been transferred, then a circulant shift is performed on shift_data, and enmul=0, State=01 is set to enter the assign state; if the value of Num is greater than L, State=00 is set to enter the input state.

[0034] Preferably, the step of calculating the check digit in step 5 includes:

[0035] Step 5.1: u 1 Serial input, the corresponding circular shift register stores W 1,1 The first line of M / 4bit 1,1 , input information source u 1 (1) The information source u 1 (1) With the row generator w 1,1 After ANDing, it is stored in the code word register module, where u i (i=1,2,…,4K) is to divide the information sequence u(i) into 4K equal parts in sequence, each with M / 4 bits, s i (i=1,2,…,8) means the check bit s is divided into 8 equal parts in sequence, each with M / 4 bits;

[0036] Step 5.2: The second information bit u 1 (2) Input, row generator w 1,1 After circular shift, 1 (2) AND, the value of the AND is different from the value calculated in step 5.1 of the codeword register module;

[0037] Step 5.3: Repeat step 5.2 until u 1 The last bit u 1 (M / 4) After the calculation is completed, input the next set of information sources u 2 , clear all values ​​in the circular shift register and then store the check matrix W of the corresponding column in the next row 2,1 The first line of w 2,1 ;

[0038] Step 5.4: Repeat steps 5.1 to 5.3 until all u i All traversals are completed, completing the task of a basic computing unit, and the codeword register module outputs the first part s of the complete codeword s1 ;

[0039] The calculation formula of the check digit s is:

[0040]

[0041] Preferably, in step 5.4, a set of s is calculated in a calculation basic unit i It needs to circularly shift (M / 4-1)×4K times, reload the value of the circular shift register 4K times, and one information bit and 8 minimum units participate in the operation in parallel.

[0042] The beneficial effects of the present invention are:

[0043] (1) The present invention can save the storage space of the LDPC code encoder, save storage resources, and is conducive to the implementation of satellite encoders in deep space environments.

[0044] (2) The present invention improves the flexibility of the LDPC code encoder by implementing the design and construction of a multi-rate LDPC code encoder, which is more conducive to encoding in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the structure of a Verilog-based multi-rate LDPC encoder under the CCSDS standard provided by the present invention;

[0046] Figure 2 A schematic diagram of the structure of the cyclic shift module provided by the present invention;

[0047] Figure 3 A schematic diagram of the structure of the check digit calculation module provided by the present invention;

[0048] Figure 4 A schematic diagram of the structure of a control module provided by the present invention;

[0049] Figure 5 A sequential storage memory map of the storage module before the improvement provided by the present invention;

[0050] Figure 6 A data storage memory diagram of the improved storage module provided by the present invention;

[0051] Figure 7 The state transition diagram of the encoder provided by the present invention;

[0052] Figure 8 A schematic diagram of the workflow of the check digit calculation module provided by the present invention;

[0053] Fig. 9 A state transition diagram of a cyclic shift module provided by the present invention;

[0054] Fig.10 A structural diagram of a 1 / 2 code rate cyclic shift module provided by the present invention;

[0055] Fig.11 A 1 / 2 code rate simulation waveform diagram of the encoder provided by the present invention;

[0056] Fig.12 A 2 / 3 code rate simulation waveform diagram of the encoder provided by the present invention;

[0057] Fig.13 The 4 / 5 code rate simulation waveform diagram of the encoder provided by the present invention;

[0058] Fig.14 A codeword text comparison result diagram generated by the encoder provided by the present invention at 1 / 2 code rate;

[0059] Fig.15 A diagram showing the comparison results of codeword texts generated by the encoder at 2 / 3 code rate provided by the present invention;

[0060] Fig.16 This is a diagram showing the comparison results of codeword text generated by the encoder provided by the present invention at a 4 / 5 code rate. DETAILED DESCRIPTION

[0061] Specific implementation method 1: Combination Figure 1-6 To illustrate this embodiment, Figure 1 As shown, the structure of the Verilog-based multi-rate LDPC encoder under the CCSDS standard described in this embodiment includes:

[0062] Control module, storage module (ROM), cyclic shift module, check bit calculation module (MUL) and codeword register module;

[0063] The encoder input signals are: clock signal clk, reset signal rst, information sequence u(i), code rate RATE. The code rate RATE is two bits. LDPC codes have three code rates. The code rate 1 / 2 is input as binary 00, the code rate 2 / 3 is input as binary 01, and the code rate 4 / 5 is input as binary 10. The output signal is the encoded codeword sequence.

[0064] The control module sends (or transmits) control signals to each module according to the input code rate and the pipeline working relationship between each module. For the storage module, the control module transmits the start bit of the storage module read address according to the input code rate, and transmits the enable signal of the circular shift register module to the ROM at the same time. For the three circular shift register modules, the control module selects the corresponding shift register to work according to the code rate. For the check bit calculation check bit calculation module, the control module transmits the enable signal of the circular shift register module to the check bit calculation module. For the code word register module, the control module transmits the check bit calculation completion signal of the check bit calculation module as the enable signal output by the code word register.

[0065] The data transmission between modules is as follows Figure 1 As shown by the wide arrow in the figure, the storage module transmits the information of the matrix generation to the three cyclic shift register modules; the cyclic shift register module transmits the generated matrix information to the check bit calculation module after cyclic shift, and the check bit calculation module transmits it to the code word register after completing the calculation of all the check bits. The code word register splices the MK-bit information source with the 2M-bit check bit and outputs the code word w.

[0066] like Figure 4 As shown, the control module has three ROM address start bit selection data. After receiving the input RATE, the corresponding address start bit selection data signal is selected for output. There are 3 circular shift register enable signals, which are all 0 when reset. After the input RATE signal, the corresponding circular shift register enable signal is pulled high to start working. The code rate corresponding to MUL has a corresponding calculation state, and the corresponding state is selected according to the code rate signal. When the circular shift register is working, data is transferred once per cycle, and the MUL enable signal is pulled high at the same time to make it calculate once; after each cycle of a circular sub-matrix, the ROM enable signal is pulled high to make it transfer the row generator of the new circular sub-matrix.

[0067] The structure of the circular shift module is as follows: Figure 2 As shown in the figure, the structure of the check bit calculation module is as follows Figure 3 As shown, the function of the storage module is to provide row generators for the circulant submatrix of the circulant shift register generator matrix. Its internal data is the row generators of the three code rate generator matrices of the 1024-bit LDPC code. For the 1 / 2 code rate, the memory of the row generator occupies a space of 128×8bit in width and 8 in depth; for the 2 / 3 code rate, the memory of the row generator occupies a space of 64×8bit in width and 16 in depth; for the 4 / 5 code rate, the memory of the row generator occupies a space of 32×8bit in width and 32 in depth. If the following is performed: Figure 5If the sequential storage method shown in FIG. 1 is used for storage, it will occupy 64K space. However, in fact, the row generators of the generator matrices of the three code rates only need 8192×3 bits of memory space, and the utilization rate of storage resources is only 37.5%, which causes great waste. Therefore, the present embodiment is designed as follows. Figure 6 The 4 / 5 code rate matrix is ​​split in the middle and stored in parallel on the right side of the 2 / 3 code rate matrix. Since the depth of the 4 / 5 code rate matrix information is 32 and that of the 2 / 3 code rate is 16, the depths of both sides are consistent after splicing. The width of the row generator of the 1 / 2 code rate matrix is ​​1024 bits, the width of the 2 / 3 code rate is 512 bits, and the width of the 4 / 5 code rate is 256 bits, so the widths of the upper and lower parts are consistent after splicing. No memory waste is caused.

[0068] Specific implementation method 2: Combination Figure 7-16 This embodiment is described as follows. Figure 7 As shown, the Verilog-based multi-rate LDPC encoding method under the CCSDS standard described in this embodiment includes:

[0069] The LDPC encoder has three states. When the en_in signal is high, it indicates that the information source is input, and the begin state is entered. By analyzing the code rate signal, the encoder enters the encode state. Different code rates have different enable signals for entering the encode state. The en_out12 signal indicates that the code word is 1 / 2 code rate, and the 1 / 2 code rate part is encoded; the en_out23 signal indicates that the code word is 2 / 3 code rate, and the 2 / 3 code rate part is encoded; the en_out45 signal indicates that the code word is 4 / 5 code rate, and the 4 / 5 code rate part is encoded. There are two enable signals in the encode state: en_rom indicates that the storage module is driven to transfer the row generator of the generation matrix, and enmul indicates that the check bit calculation module is driven to perform XOR calculation. After calculation, the en_finish signal is set to a high level, and the encoder enters the out state to output the encoded code word.

[0070] The generated matrix in the storage module is divided into blocks in the form of its own block circulant submatrix, the first row of the circulant submatrix is ​​stored, and then each block circulant generated matrix submatrix is ​​traversed in a block circulant manner. The generated matrix G under the CCSDS standard is [I MK×MK W MK×3M ], the first MK bits of the generated codeword are the original information source, so the unit matrix I on the left MK×MK No storage is required. The generated complete check digits are 3M bits, and the last M bits are punctured and not transmitted, so the matrix W on the right is MK×3M Only the first W needs to be stored MK×2MThe generator matrix under the CCSDS standard has a cyclic structure, which only stores the first row of each cyclic submatrix, and the remaining rows can be obtained by cyclic shifting the first row. The order of the cyclic submatrix of the generator matrix is ​​M / 4, so the W of each generator matrix MK×2M There are 32K circulant sub-matrices in total, and it is necessary to store the element values ​​of the generator matrix of 32K×M / 4=8k (k is the number of information bits) bits. In summary, for a generator matrix with 1024 information bits, each code rate needs to store 8192-bit values; for a generator matrix with 4096 information bits, it is necessary to store 32768-bit values; for a generator matrix with 16384 information bits, it is necessary to store 131072-bit values.

[0071] The internal state transfer of the circular shift module is as follows: Fig. 9 As shown, there are 5 states in total. The start state indicates the start of the circular shift. The input state receives the information from the storage module. The assign state passes the row generator or the shifted vector of the row generator to the check bit calculation module. The shift state performs circular shift. The output state transmits the enable signal of the check bit calculation module. The function description of the signals used by the module is shown in Table 1.

[0072] Table 1

[0073]

[0074] When the enable signal en_out arrives, the circular shift register starts working and enters the start state. The enable signals of different code rates are given by the control module. There are 3 types of enable signals corresponding to 3 types of circular shift registers.

[0075] like Fig. 9 As shown, in the start state, set State = 00 and enter the input state. In this state, pass the en_rom signal to 1 to the storage module as an enable, so that it can send the row generator. After receiving the row generator, pass it to shift_data, and set State = 01 to enter the assign state.

[0076] In the assign state, set en_rom=0; pass the value of shift_data to data as the generation matrix information to be output to the check calculation unit; and set State=11 to enter the output state.

[0077] In the output state, enmul=1 is set as the enable signal of the verification calculation unit, Num is increased by 1, indicating that the data has been transmitted once, and State=10 is set to enter the shift state.

[0078] In the shift state, first determine the value of Num. If it is less than L=16, it indicates that a cyclic sub-matrix has not been transferred. Then perform a cyclic shift on shift_data, and set enmul=0, State=01 to enter the assign state. Otherwise, set State=00 to enter the input state. In order to realize partial parallel coding, the number of bits of the cyclic shift registers of different code rates is different. For the 1 / 2 code rate, it is 8-bit parallel coding. Therefore, a cyclic shift of 8 bits is performed at a time, and a cyclic sub-matrix of a generating matrix has 8 cyclic shift registers working. For the 2 / 3 code rate, it is 4-bit parallel coding. Therefore, a cyclic shift of 4 bits is performed at a time, and a cyclic sub-matrix of a generating matrix has 4 cyclic shift registers working. For the 1 / 2 code rate, it is 2-bit parallel coding. Therefore, a cyclic shift of 2 bits is performed at a time, and a cyclic sub-matrix of a generating matrix has 2 cyclic shift registers working. Taking the 1 / 2 code rate cyclic shift register as an example, its internal structure is as follows: Fig.10 As shown in Figure 1, the basic unit of LDPC coding under the CCSDS standard is implemented using a shift register accumulator. The form of the shift register accumulator in LDPC coding is as follows: Figure 2 As shown. The generator matrix W can be written as the structure of formula (1), each submatrix W i,j They are all circulant matrices of size M / 4. When the code rate R=1 / 2, K is equal to 2; when R=2 / 3, K is equal to 4; when R=4 / 5, K is equal to 8.

[0079]

[0080] The function of the check bit calculation module is to AND the information source with the value passed by the cyclic register. The MUL signal is the state sorting signal sent by the control module to the check bit calculation module, so that when the enable signal enmul arrives, the check bit calculation module can correctly select the sub-check bit calculation module with different code rates. When a calculation is completed, the sub-check bit calculation module sends the calculated value to the storage and performs bitwise XOR with the stored value in the shorge module. Until all the information bits are calculated, the finish signal is output as the enable of the code word register module. After receiving this enable signal, the code word storage module splices the information source with the calculated check bit and outputs the complete code word.

[0081] Calculate the check digit s = uW T The steps include:

[0082] S1:u 1 Serial input, the corresponding circular shift register stores W 1,1 The first line of M / 4bit 1,1 , input information source u 1 (1) The information source u 1(1) With the row generator w 1,1 After ANDing, it is stored in the code word register module, where u i (i=1,2,...,4K) is to divide the information sequence u(i) into 4K equal parts in sequence, each with M / 4 bits, s i (i=1,2,...,8) means the check bit s is divided into 8 equal parts in sequence, each with M / 4 bits;

[0083] S2: the second information bit u 1 (2) Input, row generator w 1,1 After circular shift, 1 (2) AND, the value of the AND is different from the value calculated in step 5.1 of the codeword register module;

[0084] S3: Repeat S2 until u 1 The last bit u 1 (M / 4) After the calculation is completed, input the next set of information sources u 2 , clear all values ​​in the circular shift register and then store the check matrix W of the corresponding column in the next row 2,1 The first line of w 2,1 ;

[0085] S4: Repeat S1-S3 until all u i All traversals are completed, completing the task of a basic computing unit, and the codeword register module outputs the first part s of the complete codeword s 1 , where it can be seen from the composition of the matrix W that Figure 8 As shown, a basic unit needs to calculate a set of s in the check bit i It needs to be circularly shifted (M / 4-1)×4K times, and the value of the circular shift register needs to be reloaded 4K times. At the same time, there are 8 groups of s i Parallel computing therefore requires eight computing units to work simultaneously. The overall check digit calculation module should be as follows: Figure 8 As shown. Each SRAA is Figure 8 In the smallest unit shown, one information bit participates in the operation in parallel with 8 smallest units.

[0086] The calculation formula of the check digit s is:

[0087]

[0088] The encoder first passed the waveform simulation of Multisim, and the interface signal table function description is shown in Table 2. When finish is high, it means that the codeword is completed and the encoder is in a waiting state. Until the next information source arrives, en_in is set to high again to write the next codeword. When finish is low, it means that the encoder is working and cannot encode the next codeword.

[0089] Table 2

[0090]

[0091] According to the theoretical design, for a 1 / 2 code rate, the check bit calculation module needs 1024 / 8=128 times to calculate a code word; for a 2 / 3 code rate, the check bit calculation module needs 1024 / 4=256 times to calculate a code word; for a 4 / 5 code rate, the check bit calculation module needs 1024 / 2=512 times to calculate a code word. Each calculation requires the cyclic shift module to transmit data to the check bit calculation module. The cyclic shift module needs 2 clocks to shift the output once, so a total of 3 clocks are required for one calculation. In addition, the cyclic shift module takes 3 more clocks when receiving the row generator of the cyclic submatrix transmitted by the storage module. For 1 / 2 code rate coding, it needs to receive the row generator 8 times; for 2 / 3 code rate coding, it needs to receive the row generator 16 times; for 4 / 5 code rate coding, it needs to receive the row generator 32 times. If the system clock is 200MHz, according to the throughput calculation formula:

[0092]

[0093] In formula (1), k is the number of information bits, num code is the number of clocks used, f is the clock frequency, and the throughput of the 1 / 2 rate encoder is calculated to be 501.96 Mbps; the throughput of the 2 / 3 rate encoder is 250.98 Mbps; and the throughput of the 4 / 5 rate encoder is 125.49 Mbps.

[0094] The waveforms of Modelsim with three encoding rates are shown below: Figure 11-13 As shown in the figure, it can be seen that when en_finish is set to a high level, encode outputs the numbered codeword. The codeword simulated by the encoder is compared with the codeword calculated by the MATLAB program. The result is correct. The display result of the text comparator is as follows Figure 14-16 shown.

[0095] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A Verilog-based multi-rate LDPC encoder under the CCSDS standard, characterized in that: The structure of the Verilog-based multi-rate LDPC encoder under the CCSDS standard includes: Control module, storage module, cyclic shift module, check bit calculation module and codeword register module; The control module sends corresponding control signals to the storage module and the check bit calculation module according to the code rate RATE input by the encoder; The storage module is used for storing the row generators of the code rate RATE generation matrix and providing them to the circular shift register; The cyclic shift module is used to select the corresponding cyclic shift register according to the row generator of the code rate matrix input by the control module, generate the matrix information of the matrix cyclic sub-matrix, and pass the matrix information to the check bit calculation module after cyclic shift; The check bit calculation module performs check bit calculation, and after all the check bits are calculated, they are passed to the code word register; After the codeword register module calculates the check bit, the MK-bit information source in the matrix is ​​concatenated with the 2M-bit check bit to output the codeword w.

2. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 1, characterized in that: The internal data of the storage module are row generators of three code rate generation matrices of 1024-bit LDPC codes, including a 1 / 2 code rate generation matrix, a 2 / 3 code rate generation matrix, and a 4 / 5 code rate generation matrix; The 2 / 3 code rate generation matrix is ​​a rectangle, located in the lower left corner of the storage module generation matrix, with a width of 512 bits and a depth of 16. The 4 / 5 code rate generation matrix is ​​located on the right side of the 2 / 3 code rate generation matrix, with a width of 512 bits and a depth of 32. The 4 / 5 code rate generation matrix includes two completely identical 4 / 5 code rate sub-generation matrices, and the width of the 4 / 5 code rate sub-generation matrix is ​​256 bits. The 1 / 2 code rate generation matrix is ​​located above the 2 / 3 code rate generation matrix and the 4 / 5 code rate generation matrix, with a width of 1024 bits.

3. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 1, characterized in that: The circular shift module includes a 128-bit circular shift register, a 68-bit circular shift register and a 32-bit circular shift register. The 128-bit circular shift register, the 68-bit circular shift register and the 32-bit circular shift register are all 0 when reset.

4. The encoding method of the Verilog-based multi-rate LDPC encoder under the CCSDS standard is applied to the Verilog-based multi-rate LDPC encoder under the CCSDS standard according to any one of claims 1 to 3, characterized in that: include: Step 1: Input the clock signal clk, reset signal rst, information sequence u(i) and code rate RATE into the LDPC encoder; Step 2: Input the clock signal clk, reset signal rst, information sequence u(i) and code rate RATE as en_in signal to the control module. By analyzing the code rate RATE, the LDPC encoder enters the encode state. Different code rates RATE enter the encode state to generate en_out12 signal, en_out23 signal and en_out45 signal. The en_out12 signal indicates that the code word is 1 / 2 code rate and enters the 1 / 2 code rate partial encoding; the en_out23 signal indicates that the code word is 2 / 3 code rate and enters the 2 / 3 code rate partial encoding; the en_out45 signal indicates that the code word is 4 / 5 code rate and enters the 4 / 5 code rate partial encoding. The working order of all modules in the LDPC encoder is determined according to the clock signal clk. The control module sends an en_rom enable signal to the cyclic shift module and an enmul enable signal to the check bit calculation module according to the code rate RATE input by the encoder. Step 3: The storage module receives the en_rom enable signal, stores the row generators of the code rate RATE generation matrix and provides a circular shift register; Step 4: The cyclic shift module receives the row generator of the code rate matrix input by the control module, generates matrix information of the matrix cyclic sub-matrix, and passes the matrix information to the check bit calculation module after cyclic shift; Step 5: After receiving the enmul enable signal, the check bit calculation module performs check bit calculation. After a single calculation, it is reset by the reset signal rst and repeats steps 3-4 until all check bits are calculated. After all check bits are calculated, they are passed to the code word register. Step 6: After the calculation is completed, the en_finish signal is set to a high level, the LDPC encoder enters the out state, and the codeword register module calculates the check bit, and then splices the MK-bit information source in the matrix with the 2M-bit check bit to output the codeword w.

5. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that: In step 2, the control module sends corresponding control signals to the cyclic shift module, the check bit calculation module and the codeword register module according to the code rate RATE input by the encoder, including: The control module transmits the start bit of the storage module's read address according to the code rate RATE input by the encoder, and transmits the enable signal from the circular shift register module to the storage module at the same time. The control module selects the corresponding shift register in the circular shift module to work according to the code rate RATE, and transmits the enable signal from the circular shift register module to the check bit calculation module. The control module transmits the check bit calculation completion signal of the check bit calculation module as the enable signal output by the code word register, wherein the enable signal output by the code word register is the encoded code word sequence.

6. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that: Step 3 specifically includes: The code rate RATE generator matrix is ​​divided into blocks in the form of its own block cyclic submatrix, and the first row of the generator matrix cyclic submatrix is ​​stored. Then, each block cyclic generator matrix submatrix is ​​traversed in a block cyclic manner. For a generator matrix with 1024 information bits, each code rate needs to store 8192-bit values; for a generator matrix with 4096 information bits, a 32768-bit value needs to be stored; for a generator matrix with 16384 information bits, a 131072-bit value needs to be stored. The generator matrix G under the CCSDS standard is [I MK×MK W MK×3M ], the first MK bits of the generated codeword are the original information source, and the unit matrix I on the left MK×MK No storage is performed. The generated complete check digit has 3M bits. The last M bits are punctured and not transmitted. The matrix W on the right is MK×3M Only the first W needs to be stored MK×2M The generator matrix under the CCSDS standard has a cyclic structure, which only stores the first row of each cyclic submatrix. The remaining rows can be obtained by cyclic shifting the first row. The order of the cyclic submatrix of the generator matrix is ​​M / 4. The W of each generator matrix MK×2M There are 32K circulant sub-matrices in total, and it is necessary to store the element values ​​of the generator matrix of 32K×M / 4=8k bits, where k is the number of information bits; The expression for generating the matrix is: In formula (1), W i,j is a circulant matrix of size M / 4. When the code rate R=1 / 2, K is equal to 2; when R=2 / 3, K is equal to 4; when R=4 / 5, K is equal to 8.

7. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that: In step 4, the code rate RATE of the cyclic submatrix adopts a parallel coding structure, including three code rates: 1 / 2 code rate, 2 / 3 code rate and 4 / 5 code rate. The 1 / 2 code rate is binary 00 input, and the 1 / 2 code rate performs 8 information bits in parallel encoding. The 2 / 3 code rate is binary 01 input, and the 2 / 3 code rate performs 4 information bits in parallel encoding. The 4 / 5 code rate is binary 10 input, and the 4 / 5 code rate performs 2 information bits in parallel encoding.

8. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that: In step 4, the internal states of the cyclic shift module include the start state, input state, assign state, shift state and output state. The start state indicates the start of the cyclic shift operation, the input state indicates receiving information from the storage module, the assign state transmits the row generator to the check bit calculation module, the shift state indicates cyclic shifting, and the output state transmits the enable signal of the check bit calculation module. In the start state, set State = 00, enter the input state, pass the en_rom signal to 1 to the storage module as an enable, and let it send the row generator. After receiving the row generator, pass it to shift_data, and set State = 01 to enter the assign state. In the assign state, set en_rom = 0, pass the value of shift_data to data as the generator matrix signal output to the check bit calculation module, and set State = 11 to enter the output state. In the output state, enmul=1 is set as the enable signal of the check bit calculation module, where Num plus 1 indicates that the data has been transmitted once, and State=10 is set to enter the shift state. In the shift state, the value of Num is determined. If the value of Num is less than L, L=16 indicates that a circulant submatrix has not been transferred, then a circulant shift is performed on shift_data, and enmul=0, State=01 is set to enter the assign state; if the value of Num is greater than L, State=00 is set to enter the input state.

9. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that: The steps for calculating the check digit in step 5 include: Step 5.1: u1 is input serially, and the corresponding circular shift register stores W 1,1 The first line of M / 4bit 1,1 , input information source u1(1), combine information source u1(1) with row generator w 1,1 After ANDing, it is stored in the code word register module, where u i (i=1,2,…,4K) is to divide the information sequence u(i) into 4K equal parts in sequence, each with M / 4 bits, s i (i=1,2,…,8) means the check bit s is divided into 8 equal parts in sequence, each with M / 4 bits; Step 5.2: The second information bit u1(2) is input, and the row generator w 1,1 After cyclic shift by one position, it is ANDed with u1(2), and the value of the ANDed is different from the value calculated in step 5.1 of the codeword register module; Step 5.3: Repeat step 5.2 until the last bit u1(M / 4) of u1 is calculated, then input the next set of information source u2, clear all values ​​in the circular shift register and then store the check matrix W of the next row and column. 2,1 The first line of w 2,1 ; Step 5.4: Repeat Step 5.1-Step 5.3 until all u i All traversals are completed, completing the task of a basic computing unit, and the codeword register module outputs the first part s1 of the complete codeword s; The calculation formula of the check digit s is:

10. The Verilog-based multi-rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that: In step 5.4, a set of s is calculated in a calculation unit i It needs to circularly shift (M / 4-1)×4K times, reload the value of the circular shift register 4K times, and one information bit and 8 minimum units participate in the operation in parallel.

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