Memory device

Abstract

A memory device includes a substrate, a first interconnect structure, first and second elements, a second interconnect structure, and a third interconnect structure. The substrate includes a first surface and a second surface opposite to each other. The first interconnect structure is disposed on the first surface of the substrate. The first element and the second element are disposed in the substrate and / or the first interconnect structure. The first interconnect structure includes a plurality of first wiring layers configured to be closest to the first element and the second element. The second interconnect structure is disposed on the first interconnect structure. A third interconnect structure is disposed on the second surface of the substrate and includes a plurality of second wiring layers configured closest to the first element and the second element. The first element and the second element each include a first electrical connection path through the first wiring layer and a second electrical connection path through the second wiring layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a memory device. Background Art

[0002] As the size of electronic devices continues to shrink and users' requirements for the performance of electronic devices continue to increase, how to make electronic devices include more components while maintaining the existing horizontal area, or how to make them have a small horizontal area while maintaining the existing number of components, has become one of the goals that technicians in this field are eager to work on. However, no matter which of the above situations is used, the density of interconnection lines (especially the density of interconnection lines closest to the components) will be significantly increased, which will require a finer line width.

[0003] In the current manufacturing process, extreme ultraviolet (EUV) with a small exposure wavelength is often used as the light source of the exposure machine. In this way, interconnects with small line widths can be achieved by reducing the wavelength of the exposure light source. However, the lithography process using EUV is not only expensive and energy-consuming, but also under the premise that the size of electronic devices continues to shrink, the lithography process using EUV will still face the problem of being unable to produce devices that meet the expected size in the future. Therefore, those skilled in the art continue to look for methods other than reducing the wavelength of the exposure light source. Summary of the invention

[0004] The present invention provides a memory device, which arranges a third interconnect structure including a second wiring layer on the back side of a substrate, so that the first element and the second element include not only a first electrical connection path through the first wiring layer on the front side of the substrate, but also a second electrical connection path through the second wiring layer on the back side of the substrate. In other words, some wiring in the wiring area on the front side of the wafer can be moved to the back side of the wafer, so the density of interconnect lines formed on the front side of the wafer can be significantly reduced. In this way, the memory device can include more elements while maintaining the existing horizontal area, and the design rules can be relaxed, thereby allowing fine line width interconnect lines to be selectively designed.

[0005] An embodiment of the present invention provides a memory device, which includes a substrate, a first interconnection structure, a second interconnection structure, and a third interconnection structure. The substrate includes a first surface and a second surface opposite to each other. The first interconnection structure is arranged on the first surface of the substrate. The first element and the second element are arranged in the substrate and / or the first interconnection structure, wherein the first interconnection structure includes a plurality of first wiring layers configured to be closest to the first element and the second element. The second interconnection structure is arranged on the first interconnection structure. The third interconnection structure is arranged on the second surface of the substrate and includes a plurality of second wiring layers configured to be closest to the first element and the second element. The first element and the second element each include a first electrical connection path through the first wiring layer and a second electrical connection path through the second wiring layer.

[0006] In one embodiment of the present invention, the substrate includes a cell region and a peripheral region adjacent to the cell region, and the first element and / or the second element is disposed in the peripheral region and electrically connected to the memory array in the cell region through a first electrical connection path and / or a second electrical connection path.

[0007] In one embodiment of the present invention, the first element and / or the second element includes a sense amplifier or a word line driver.

[0008] In one embodiment of the present invention, the first element is connected to the second element through a first electrical connection path and / or a second electrical connection path.

[0009] In one embodiment of the present invention, the third interconnect structure includes a first through hole penetrating through the substrate and contacting the first element and / or the second element.

[0010] In one embodiment of the present invention, the third interconnect structure includes a second through hole penetrating the substrate and the first interconnect structure and contacting the first wiring layer.

[0011] An embodiment of the present invention provides a memory device, which includes a first wafer and a second wafer stacked on the first wafer. The first wafer includes a first substrate, a first front-side interconnection structure, a plurality of first elements, a second front-side interconnection structure, and a first back-side interconnection structure. The first substrate includes a front-side surface and a back-side surface opposite to each other. The first front-side interconnection structure is arranged on the front-side surface of the first substrate. The first element is arranged in the first substrate and / or the first front-side interconnection structure, wherein the first front-side interconnection structure includes a plurality of first wiring layers configured to be closest to the first element. The second front-side interconnection structure is arranged on the first front-side interconnection structure. The first back-side interconnection structure is arranged on the back-side surface of the first substrate and includes a plurality of second wiring layers configured to be closest to the first element. Each first element includes a first front-side electrical connection path through the first wiring layer and a first back-side electrical connection path through the second wiring layer. The second wafer includes a second substrate, a third front-side interconnection structure, a plurality of second elements, a fourth front-side interconnection structure, and a second back-side interconnection structure. The second substrate is arranged on the second front-side interconnection structure and includes a front-side surface and a back-side surface opposite to each other. The third front-side interconnection structure is arranged on the front-side surface of the second substrate. The second element is arranged in the second substrate and / or the third front side interconnection structure, wherein the third front side interconnection structure includes a plurality of third wiring layers configured to be closest to the second element. The fourth front side interconnection structure is arranged on the third front side interconnection structure. The second back side interconnection structure is arranged on the back side surface of the second substrate and includes a plurality of fourth wiring layers configured to be closest to the second element. Each second element includes a second front side electrical connection path through the third wiring layer and a second back side electrical connection path through the fourth wiring layer. The second front side interconnection structure includes a redistribution layer connected to the second back side electrical connection path.

[0012] In one embodiment of the present invention, the redistribution layer is connected to the first front-side electrical connection path.

[0013] In one embodiment of the present invention, the first backside interconnect structure and the second backside interconnect structure include first through holes that penetrate the first substrate and the second substrate respectively and contact the first element and the second element respectively.

[0014] In one embodiment of the present invention, the first backside interconnection structure and the second backside interconnection structure include second through holes that pass through the first substrate and the first frontside interconnection structure and through the second substrate and the third frontside interconnection structure and contact the first wiring layer and the third wiring layer respectively.

[0015] In one embodiment of the present invention, the second front-side interconnect structure includes a front-side pad directly contacting the fourth wiring layer.

[0016] In one embodiment of the present invention, the second wafer includes a through via penetrating the third front-side interconnect structure, the second substrate, and the second back-side interconnect structure, and the through via contacts one of the fourth wiring layers.

[0017] Based on the above, in the memory device of the above embodiment, the third interconnect structure including the second wiring layer is arranged on the back side of the substrate, so that the first element and the second element include not only the first electrical connection path on the front side of the substrate (through the first wiring layer), but also the second electrical connection path on the back side of the substrate (through the second wiring layer). In other words, some wirings originally arranged in the wiring area on the front side of the wafer are moved to the back side of the wafer, so the density of the interconnection lines formed on the front side of the wafer can be significantly reduced. In this way, the memory device can adopt relaxed design rules (for example, interconnection lines with high density and fine line width are optional but not necessary) to achieve a design including more elements while maintaining the existing horizontal area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a cross-sectional schematic diagram of a memory device according to an embodiment of the present invention;

[0019] Figure 2 is a cross-sectional schematic diagram of a memory device according to an embodiment of the present invention;

[0020] Figure 3 yes Figure 2 A cross-sectional schematic diagram of an embodiment of a wafer 10a;

[0021] Figure 4 yes Figure 2 A cross-sectional schematic diagram of an embodiment of a wafer 10b;

[0022] Figure 5 yes Figure 2 FIG. 1 is a cross-sectional schematic diagram of an embodiment of a wafer 10c in FIG.

[0023] Explanation of symbols

[0024] 10: Wafer

[0025] 10': Wafer stacking

[0026] 10a: First Wafer

[0027] 10b: Second Wafer

[0028] 10c: The third wafer

[0029] 20: Carrying base

[0030] 20': Wafer loading

[0031] 100: base / first base / second base

[0032] 120, 150, 220: Interconnection lines

[0033] 122, 230: front side pad

[0034] 160: Under Bump Metallization (UBM) Layer / UBM Layer

[0035] 170: Electrical connection metal

[0036] 200: Basic base

[0037] 202: Components

[0038] 204: Component layer

[0039] 210: Bonding layer

[0040] 1C: Conductive contact

[0041] 1Wf, 1Wf1: First wiring layer

[0042] 1Wb, 1Wb1: Second wiring layer

[0043] 1Wf2: The third wiring layer

[0044] 1Wb2: Fourth wiring layer

[0045] 1Wf2, 1Wb3, 2Wf: Wiring layer

[0046] BS: Third Interconnect Structure

[0047] BS1: First backside interconnect structure

[0048] BS2: Second backside interconnect structure

[0049] D1: First Component

[0050] D2: Second Component

[0051] FS1: first interconnection structure / first front-side interconnection structure / third front-side interconnection structure

[0052] FS2 second interconnection structure / second front-side interconnection structure / fourth front-side interconnection structure

[0053] FEOL: Front-end manufacturing process structure

[0054] BEOL: Back-end manufacturing process structure

[0055] IL0, 110, 130, 140, 212: dielectric layer

[0056] RDL1, RDL2, RDL3: redistribution layers

[0057] S1: First surface / front surface

[0058] S2: Second surface / back surface

[0059] TSV1: First through hole

[0060] TSV2: Second through hole

[0061] TSV3: Through Via DETAILED DESCRIPTION

[0062] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the accompanying drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0063] It should be understood that when, for example, an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and / or electrical connection, and "electrical connection" or "coupling" may be the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

[0064] As used herein, "about", "approximately" or "substantially" includes the referenced value and an average value within an acceptable deviation range of the particular value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property or other property, and can apply to all properties without a single standard deviation.

[0065] The terms used herein are used to describe exemplary embodiments only and are not intended to limit the present invention. In this case, unless otherwise explained in the context, the singular form includes the plural form.

[0066] Figure 1 is a cross-sectional schematic diagram of a memory device according to an embodiment of the present invention.

[0067] Please refer to Figure 1, the memory device includes a wafer 10 and a carrier substrate 20 that carries the wafer 10. The wafer 10 includes a substrate 100, a first interconnection structure FS1, a first element D1 and a second element D2, a second interconnection structure FS2, and a third interconnection structure BS. The carrier substrate 20 includes a base substrate 200 and a bonding layer 210 formed on the base substrate 200. The base substrate 200 may include a material suitable as a substrate of the wafer, such as silicon. The bonding layer 210 may include a material suitable as an adhesive layer. The memory device may include a dynamic random-access memory (DRAM).

[0068] The substrate 100 includes a first surface S1 and a second surface S2 opposite to each other. The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The II-VI semiconductor material may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0069] The first interconnect structure FS1 is disposed on the first surface S1 of the substrate 100. The first element D1 and the second element D2 are disposed in the substrate 100 and / or the first interconnect structure FS1. For example, the first element D1 and / or the second element D2 may include a well region (not shown) formed in the substrate 100 and / or a structure (not shown) formed on the substrate 100 (i.e., located in the first interconnect structure FS1). In some embodiments, the first element D1 and / or the second element D2 may include a sense amplifier or a word line driver.

[0070] The first interconnect structure FS1 includes a plurality of first wiring layers 1Wf configured to be closest to the first element D1 and the second element D2. The first wiring layer 1Wf may include a conductive material such as a metal or a metal alloy. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof. In some embodiments, the first interconnect structure FS1 may include a dielectric layer IL0 formed on the first surface S1 of the substrate 100 and in which the first wiring layer 1Wf is formed, and a conductive contact 1C formed in the dielectric layer IL0 and connecting the first element D1 and the second element D2 to the first wiring layer 1Wf. The dielectric layer IL0 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The conductive contact 1C may include a conductive material such as a metal or a metal alloy. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof.

[0071] The second interconnect structure FS2 is disposed on the first interconnect structure FS1. The second interconnect structure FS2 is electrically connected to the first interconnect structure FS1. In some embodiments, the second interconnect structure FS2 is disposed between the first interconnect structure FS1 and the bonding layer 210 of the carrier substrate 20. In other words, in some embodiments, after forming the first interconnect structure FS1, the first element D1 and the second element D2, and the second interconnect structure FS2 of the wafer 10, the wafer 10 may be flipped and placed on the carrier substrate 20. Then, after a thinning process is performed on the back side of the wafer 10, a third interconnect structure BS is formed on the second surface S2 of the thinned substrate 100.

[0072] In some embodiments, the second interconnect structure FS2 may include a dielectric layer 110 and an interconnect line 120 formed in the dielectric layer 110. The dielectric layer 110 may include a single layer or multiple layers of dielectric layers, but the present invention is not limited thereto. The dielectric layer 110 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The interconnect line 120 may include a single layer or multiple layers of wiring layers or redistribution layers and through holes connecting the wiring layers or redistribution layers. The interconnect line 120 may include a conductive material such as a metal or a metal alloy. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof.

[0073] The third interconnect structure BS is disposed on the second surface S2 of the substrate 100 and includes a plurality of second wiring layers 1Wb configured to be closest to the first element D1 and the second element D2, so that the first element D1 and the second element D2 each include a first electrical connection path through the first wiring layer 1Wf and a second electrical connection path through the second wiring layer 1Wb. In other words, some wirings originally disposed in the wiring area on the front side of the wafer 10 are moved to the back side of the wafer 10, so that the density of the interconnect lines formed on the front side of the wafer 10 (for example, the density of the first wiring layer 1Wf) can be significantly reduced. In this way, the memory device can adopt relaxed design rules to achieve a design including more elements while maintaining the existing horizontal area, or can enable the memory device to adopt relaxed design rules to achieve a design with a smaller horizontal area while maintaining the existing number of elements. It is worth noting that the wiring layer closer to the first component D1 and the second component D2 has a higher density and a finer line width, so moving the wiring closest to the first component D1 and the second component D2 from the front side of the wafer 10 to the back side of the wafer 10 can significantly relax the design rules.

[0074] In some embodiments, based on the fact that some wirings are moved to the back side of the wafer 10, the first element D1 may be connected to the second element D2 through a first electrical connection path (e.g., a path through the first wiring layer 1Wf) and / or a second electrical connection path (e.g., a path through the second wiring layer 1Wb). In some embodiments, the substrate 100 may include a cell region and a peripheral region adjacent to the cell region, wherein the first element D1 and / or the second element D2 may be disposed in the peripheral region and electrically connected to a memory array (not shown) in the cell region through a first electrical connection path (e.g., a path through the first wiring layer 1Wf) and / or a second electrical connection path (e.g., a path through the second wiring layer 1Wb).

[0075] The third interconnect structure BS may include a dielectric layer 130 formed on the second surface S2 of the substrate 100 and a through hole (e.g., a first through hole TSV1 and a second through hole TSV2) electrically connecting the second wiring layer 1Wb to the first element D1 and / or the second element D2. For example, in some embodiments, the third interconnect structure BS may include a first through hole TSV1 passing through the dielectric layer 130 and the substrate 100 and contacting the first element D1. In some embodiments, the third interconnect structure BS may include a second through hole TSV2 passing through the dielectric layer 130, the substrate 100 and the first interconnect structure FS1 and contacting the first wiring layer 1Wf. The dielectric layer 130 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The first through hole TSV1 and / or the second through hole TSV2 may include a conductive material such as a metal, a metal alloy, a metal nitride, a metal silicide, or a combination thereof. In some embodiments, the metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or an alloy thereof. The metal nitride may be, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten silicon nitride, or a combination thereof. The metal silicide may include tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof.

[0076] The third interconnect structure BS may include a dielectric layer 140 formed on the dielectric layer 130 and covering the second wiring layer 1Wb, and an interconnect line 150 formed in the dielectric layer 140. The dielectric layer 140 may include a single layer or multiple layers of dielectric layers, but the present invention is not limited thereto. The dielectric layer 140 may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The interconnect line 150 may include a single layer or multiple layers of wiring layers or redistribution layers and through holes connecting the wiring layers or redistribution layers. The interconnect line 150 may include a conductive material such as a metal or a metal alloy. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof.

[0077] The memory device may include an under-bump metallization (UBM) layer 160 formed on the third interconnect structure BS and an electrical connection metal 170 formed on the UBM layer 160. In some embodiments, the wafer 10 may be physically connected and / or electrically connected to an external device via the UBM layer 160 and the electrical connection metal 170. The UBM layer 160 may be formed by a known metallization method using a known conductive material such as a metal. The electrical connection metal 170 may include a low melting point metal, such as a solder, such as tin-aluminum-copper (Sn-Al-Cu). The electrical connection metal 170 may have a single-layer or multi-layer structure. For example, the multi-layer structure may include a copper pillar and a solder, and the single-layer structure may include tin-silver solder or copper. The number, spacing, configuration, etc. of the electrical connection metal 170 are not limited.

[0078] Figure 2is a cross-sectional schematic diagram of a memory device according to an embodiment of the present invention. Figure 3 yes Figure 2 FIG. 1 is a cross-sectional schematic diagram of an embodiment of a wafer 10 a in FIG. Figure 4 yes Figure 2 FIG. 1 is a cross-sectional schematic diagram of an embodiment of a wafer 10 b in FIG. Figure 5 yes Figure 2 FIG. 1 is a cross-sectional schematic diagram of an embodiment of a wafer 10c in FIG. Figure 2 The wafer stack 10 ′ shown includes a first wafer 10 a, a second wafer 10 b, and a third wafer 10 c, wherein the first wafer 10 a, the second wafer 10 b, and the third wafer 10 c are Figure 1 The wafers 10 shown are substantially the same, so the same or similar components are designated by the same or similar component numbers and are not described again.

[0079] Please refer to Figure 2 The memory device includes a wafer stack 10' and a carrier wafer 20' carrying the wafer stack 10'. The wafer stack 10' includes a first wafer 10a and a second wafer 10b stacked on the first wafer 10a. The memory device may include a dynamic random-access memory (DRAM).

[0080] Please refer to Figure 2 and Figure 3 The first wafer 10a includes a first substrate 100, a first front-side interconnect structure FS1, a plurality of first components (such as Figure 3 D1 and D2 shown), a second front side interconnect structure FS2 and a first back side interconnect structure BS1. The first substrate 100 includes a front side surface S1 and a back side surface S2 opposite to each other. The first front side interconnect structure FS1 is arranged on the front side surface S1 of the first substrate 100. The first element is arranged in the first substrate 100 and / or the first front side interconnect structure FS1, wherein the first front side interconnect structure FS1 includes a plurality of first wiring layers 1Wf1 configured to be closest to the first element. The second front side interconnect structure FS2 is arranged on the first front side interconnect structure FS1. The first back side interconnect structure BS1 is arranged on the back side surface S2 of the first substrate 100 and includes a plurality of second wiring layers 1Wb1 configured to be closest to the first element. Each first element includes a first front side electrical connection path through the first wiring layer 1Wf1 and a first back side electrical connection path through the second wiring layer 1Wb1.

[0081] Please refer to Figure 2 and Figure 4 The second wafer 10b includes a second substrate 100, a third front-side interconnect structure FS1, a plurality of second components (eg Figure 4D1 and D2 shown), a fourth front side interconnect structure FS2 and a second back side interconnect structure BS2. The second substrate 100 is disposed on the second front side interconnect structure FS2 and includes a front side surface S1 and a back side surface S2 opposite to each other. The third front side interconnect structure FS1 is disposed on the front side surface S1 of the second substrate 100. The second element is disposed in the second substrate 100 and / or the third front side interconnect structure FS1, wherein the third front side interconnect structure FS1 includes a plurality of third wiring layers 1Wf2 configured to be most adjacent to the second element. The fourth front side interconnect structure FS2 is disposed on the third front side interconnect structure FS1. The second back side interconnect structure BS2 is disposed on the back side surface S2 of the second substrate 100 and includes a plurality of fourth wiring layers 1Wb2 configured to be most adjacent to the second element. Each second element includes a second front side electrical connection path through the third wiring layer 1Wf2 and a second back side electrical connection path through the fourth wiring layer 1Wb2.

[0082] Please refer to Figures 2 to 4 The second front-side interconnect structure FS2 includes a redistribution layer RDL2 connected to the second back-side electrical connection path (the path through the fourth wiring layer 1Wb2). In this way, the first element (eg Figure 3 D1 or D2 shown) can be connected to the redistribution layer RDL2 through the first front side electrical connection path (path through the first wiring layer 1Wf1), while the second element (eg Figure 4 D1 or D2 shown) can be connected to the redistribution layer RDL2 through a second back-side electrical connection path (through a path of the fourth wiring layer 1Wb2), so that the wafer stack 10' can adopt relaxed design rules to achieve a design including more components, or it can enable the wafer stack 10' to adopt relaxed design rules to achieve a design with a smaller horizontal area while maintaining the existing number of components. The redistribution layer RDL2 may include conductive materials such as metals or metal alloys. The metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or alloys thereof.

[0083] In some embodiments, Figure 3 and Figure 4 As shown, the first backside interconnect structure BS1 and the second backside interconnect structure BS2 may include first through vias TSV1 that pass through the first substrate 100 of the first wafer 10a and the second substrate 100 of the second wafer 10b and contact the first element of the first wafer 10a and the second element of the second wafer 10b, respectively.

[0084] In some embodiments, Figure 3 and Figure 4As shown, the first backside interconnect structure BS1 and the second backside interconnect structure BS2 may include second through-holes TSV2 that pass through the first substrate 100 and the first frontside interconnect structure FS1 of the first wafer 10a and the second substrate 100 and the third frontside interconnect structure FS1 of the second wafer 10b and contact the first wiring layer 1Wf1 and the third wiring layer 1Wf2 respectively.

[0085] In some embodiments, Figure 3 As shown, the second front-side interconnect structure FS2 may include a front-side pad 122 that is in direct contact with the fourth wiring layer 1Wb2. That is, the first wafer 10a and the second wafer 10b can be bonded to each other in a hybrid bond (hybrid bond). For example, the front-side pad 122 of the first wafer 10a is in direct contact with the fourth wiring layer 1Wb2 of the second wafer 10b (i.e., metal-to-metal bonding), and the dielectric layer 110 (e.g., the dielectric layer 110 of the first wafer 10a) is in direct contact with the fourth wiring layer 1Wb2 of the second wafer 10b. Figure 3 ) and the dielectric layer 130 of the second wafer 10b (as shown Figure 4 as shown) in direct contact (i.e., dielectric-to-dielectric bonding).

[0086] In some embodiments, Figure 4 As shown, the second wafer 10b may include a through-hole TSV3 penetrating the third front-side interconnect structure FS1, the second substrate 100, and the second back-side interconnect structure BS2, and the through-hole TSV3 contacts one of the fourth wiring layers 1Wb2. In some embodiments, the through-hole TSV3 electrically connects one of the fourth wiring layers 1Wb2 to the wiring layer 2Wf formed in the fourth front-side interconnect structure FS2, that is, the second back-side interconnect structure BS2 may be connected to the wiring layer 2Wf in the fourth front-side interconnect structure FS2 through the through-hole TSV3 without being connected to the wiring layer 2Wf in the fourth front-side interconnect structure FS2 via the third front-side interconnect structure FS1. In some embodiments, Figure 3 or Figure 4 The through via TSV3 shown is formed after forming the first element or the second element, and thus can be referred to as a middle through via (TSV-middle).

[0087] like Figure 2 As shown, the carrier wafer 20 ′ may include a front-end-of-line (FEOL) structure and a back-end-of-line (BEOL) structure formed on the front-end-of-line (FEOL) structure.

[0088] The front-end manufacturing process structure FEOL may include a base substrate 200, a plurality of components 202, and a component layer 204 in which the plurality of components 202 are formed. The base substrate 200 may include a semiconductor substrate or an SOI substrate. In some embodiments, the base substrate 200 may include the same or similar material as the substrate 100. The components 202 may include active components and / or passive components. The component layer 204 may include components (e.g., components 202) formed therein and a dielectric layer covering the components.

[0089] The back-end manufacturing process structure BEOL may include a dielectric layer 212 and interconnect lines 220 formed in the dielectric layer 212, a front-side pad 230, and a redistribution layer RDL1. In some embodiments, the redistribution layer RDL1 is connected to the first device (eg, Figure 3 The first backside electrical connection path (eg, the path through the second wiring layer 1Wb1) of the first wafer 10a is connected. In this way, the first element (eg, Figure 3 D1 or D2) shown can be connected to the redistribution layer RDL1 through a first back-side electrical connection path (a path through the first wiring layer 1Wb1), so that the memory device can adopt relaxed design rules to achieve a design including more components, or enable the memory device to adopt relaxed design rules to achieve a design with a smaller horizontal area while maintaining the existing number of components.

[0090] The dielectric layer 212 may include a single layer or multiple layers of dielectric layers, but the present invention is not limited thereto. The dielectric layer 212 may include dielectric materials such as oxides (e.g., silicon oxide) or nitrides (e.g., silicon nitride). The interconnection line 220 may include a single layer or multiple layers of wiring layers or redistribution layers and through holes connecting the wiring layers or redistribution layers. The interconnection line 220 and / or the redistribution layer RDL1 may include conductive materials such as metals or metal alloys. The metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0091] The top surface of the front side pad 230 can be exposed to the surface of the back-end manufacturing process structure BEOL facing the first wafer 10a, so that the carrier wafer 20' and the first wafer 10a can be bonded to each other in a hybrid bonding manner. For example, the front side pad 230 of the carrier wafer 20' and the first wiring layer 1Wb1 of the first wafer 10a are in contact with each other (i.e., metal-to-metal bonding), and the dielectric layer 212 and the dielectric layer 130 are in contact with each other (i.e., dielectric-to-dielectric bonding).

[0092] In some embodiments, please refer to Figure 2 , Figure 4 and Figure 5, the third wafer 10c is stacked on the second wafer 10b, wherein the second front-side interconnect structure FS2 in the second wafer 10b includes a redistribution layer RDL3 connected to the back-side electrical connection path (path through the wiring layer 1Wb3) of the third wafer 10c. In this way, the components in the second wafer 10b (e.g. Figure 4 D1 or D2 shown) can be connected to the redistribution layer RDL3 through the front-side electrical connection path (path through the wiring layer 1Wf2), and the components in the third wafer 10c (eg Figure 5 D1 or D2 shown) can be connected to the redistribution layer RDL3 through a back-side electrical connection path (through the path of the wiring layer 1Wb3), so that the wafer stack 10' can adopt a relaxed design rule to achieve a design including more components, or it can enable the wafer stack 10' to adopt a relaxed design rule to achieve a design with a smaller horizontal area while maintaining the existing number of components. The redistribution layer RDL3 may include conductive materials such as metals or metal alloys. The metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or their alloys.

[0093] In summary, in the memory device of the above embodiment, the third interconnect structure including the second wiring layer is arranged on the back side of the substrate, so that the first element and the second element include not only the first electrical connection path on the front side of the substrate (through the first wiring layer), but also the second electrical connection path on the back side of the substrate (through the second wiring layer). In other words, some wirings originally arranged in the wiring area on the front side of the wafer are moved to the back side of the wafer, so the density of the interconnection lines formed on the front side of the wafer can be significantly reduced. In this way, the memory device can adopt relaxed design rules (for example, interconnection lines with high density and fine line width are optional but not necessary) to achieve a design including more elements while maintaining the existing horizontal area.

Claims

1. A memory device, comprising: a substrate including a first surface and a second surface opposite to each other; a first interconnect structure disposed on the first surface of the substrate; first elements and second elements disposed in the substrate and / or the first interconnect structure, wherein the first interconnect structure includes a plurality of first wiring layers configured to be proximal to the first elements and the second elements; a second interconnect structure, disposed on the first interconnect structure; as well as a third interconnect structure disposed on the second surface of the substrate and comprising a plurality of second wiring layers arranged to be proximate to the first element and the second element, The first element and the second element each include a first electrical connection path passing through the first wiring layer and a second electrical connection path passing through the second wiring layer.

2. A memory device as described in claim 1, wherein the substrate includes a cell region and a peripheral region adjacent to the cell region, the first element and / or the second element is arranged in the peripheral region and is electrically connected to the memory array in the cell region through the first electrical connection path and / or the second electrical connection path.

3. The memory device of claim 2, wherein the first element and / or the second element comprises a sense amplifier or a word line driver. 4 . The memory device of claim 3 , wherein the first element is connected to the second element through the first electrical connection path and / or the second electrical connection path. 5 . The memory device of claim 1 , wherein the third interconnect structure comprises a first via penetrating the substrate and contacting the first element and / or the second element. 6 . The memory device of claim 5 , wherein the third interconnect structure comprises a second via penetrating the substrate and the first interconnect structure and contacting the first wiring layer.

7. A memory device comprising: The first wafer includes: A first substrate including a front surface and a back surface opposite to each other; A first front-side interconnect structure disposed on the front-side surface of the first substrate; a plurality of first elements disposed in the first substrate and / or the first front-side interconnect structure, wherein the first front-side interconnect structure comprises a plurality of first wiring layers configured to be most adjacent to the first elements; a second front-side interconnect structure disposed on the first front-side interconnect structure; and a first backside interconnect structure disposed on the backside surface of the first substrate and comprising a plurality of second wiring layers arranged to be most adjacent to the first element, wherein each of the first elements comprises a first front-side electrical connection path through the first wiring layer and a first back-side electrical connection path through the second wiring layer; and A second wafer is stacked on the first wafer and comprises: a second substrate disposed on the second front-side interconnect structure and comprising a front-side surface and a back-side surface opposite to each other; a third front-side interconnect structure disposed on the front-side surface of the second substrate; a plurality of second elements disposed in the second substrate and / or the third front-side interconnect structure, wherein the third front-side interconnect structure includes a plurality of third wiring layers configured to be most adjacent to the second elements; a fourth front-side interconnection structure, disposed on the third front-side interconnection structure; and a second backside interconnect structure disposed on the backside surface of the second substrate and comprising a plurality of fourth wiring layers configured to be most adjacent to the second element, wherein each of the second elements comprises a second front side electrical connection path through the third wiring layer and a second back side electrical connection path through the fourth wiring layer, and The second front-side interconnect structure includes a redistribution layer in communication with the second back-side electrical connection path.

8. The memory device of claim 7, wherein the redistribution layer is in communication with the first front-side electrical connection path.

9. The memory device of claim 7, wherein the first backside interconnect structure and the second backside interconnect structure include first vias penetrating the first substrate and the second substrate, respectively, and contacting the first element and the second element, respectively.

10. The memory device of claim 9, wherein the first backside interconnect structure and the second backside interconnect structure include second through holes passing through the first substrate and the first frontside interconnect structure and through the second substrate and the third frontside interconnect structure and contacting the first wiring layer and the third wiring layer, respectively.

11. The memory device of claim 10, wherein the second front-side interconnect structure comprises a front-side pad in direct contact with the fourth wiring layer. 12 . The memory device of claim 11 , wherein the second wafer comprises through vias penetrating the third front-side interconnect structure, the second substrate, and the second back-side interconnect structure, and the through vias contact one of the fourth wiring layers.

Images