Embedded flash memory structure and manufacturing method thereof

Abstract

The invention discloses an embedded flash memory structure and a manufacturing method thereof. The embedded flash memory structure comprises a semiconductor substrate, a clearing gate located on the semiconductor substrate, two floating gates located on the semiconductor substrate on two sides of the clearing gate respectively, two word lines located on the outer sides of the two floating gates respectively, and two metal control gates located on the two floating gates respectively, wherein at least one side of the metal control gate is provided with a sacrificial layer, and the hard mask layer is arranged between the metal control gate and the clearing gate or between the metal control gate and the word line.

Description

Technical Field

[0001] The present invention relates to an embedded flash memory structure, and more particularly to an embedded flash memory structure with a metal control gate and a manufacturing method thereof. Background Art

[0002] Embedded flash memory is a flash memory integrated with logic elements, and the two are formed on a common integrated circuit chip. Since there is no need for interconnection structures between different chips, it can improve the performance of the elements, and because the flash memory and logic elements share the same manufacturing process steps, the manufacturing cost can also be reduced.

[0003] In the integration of embedded flash memory and high-k metal gate (HKMG) logic manufacturing process, due to gate height considerations, the control gate in the original memory structure will be removed and the programming of the memory will be controlled by the source line instead. However, such a design requires a higher voltage to be applied to the erase gate, which is likely to cause the gate oxide layer to break down and affect the electrical properties of the device. Furthermore, in such a design, the contact originally connected to the control gate will be changed to be connected to the floating gate with a lower height. Its integration in the original HKMG manufacturing process is likely to make the formed contact unable to touch the floating gate and cause a short circuit. For this reason, the technical personnel of the present invention need to improve the integration and structure of the existing embedded flash memory and (HKMG) logic manufacturing process to solve the above problems. Summary of the invention

[0004] In view of the problems encountered in the prior art, the present invention proposes a novel embedded flash memory structure and manufacturing method, which is characterized in that a high-k metal gate (HKMG) logic manufacturing process is used to manufacture the control gate of the memory, while taking into account the gate height consideration in the manufacturing process integration.

[0005] One aspect of the present invention is to provide a novel embedded flash memory, the structure of which includes a semiconductor substrate, a clear gate located on the semiconductor substrate, two floating gates located on both sides of the clear gate, two word lines located outside the two floating gates, and two metal control gates located on the two floating gates, wherein at least one side of the metal control gate has a sacrificial layer, and the sacrificial layer is between the metal control gate and the clear gate or between the metal control gate and the word line.

[0006] Another aspect of the present invention is to provide a method for manufacturing an embedded flash memory structure, the steps of which include: providing a semiconductor substrate having a memory cell region and a logic element region; forming a floating gate and a sacrificial layer on the floating gate on the memory cell region of the semiconductor substrate; performing a first photolithography process to carve out a control gate groove in the sacrificial layer; performing a first deposition process to form a polysilicon layer on the semiconductor substrate on both sides of the floating gate and in the control gate groove; performing a first planarization process to remove the polysilicon layer outside the control gate groove, thereby forming a dummy control gate in the control gate groove and forming a clearing layer inside the floating gate. The invention relates to a method for forming a gate; forming a dummy gate on the logic element area; forming a contact hole etch stop layer and an interlayer dielectric layer on the dummy control gate and the dummy gate; performing a second planarization process to remove part of the interlayer dielectric layer and the contact hole etch stop layer until the interlayer dielectric layer is no longer on the top surface of the contact hole etch stop layer; performing an etching process to simultaneously remove the dummy gate and the dummy control gate, thereby forming a gate groove on the semiconductor substrate in the logic element area and exposing the original control gate groove on the storage cell area; and simultaneously filling metal into the gate groove and the control gate groove to form a metal gate and a metal control gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 13 A cross-sectional schematic diagram of a manufacturing process of an embedded flash memory structure in a preferred embodiment of the present invention;

[0008] Figures 14 to 16 A cross-sectional schematic diagram of a manufacturing process of an embedded flash memory structure in another embodiment of the present invention;

[0009] Fig.17 It is a cross-sectional schematic diagram of an embedded flash memory structure in a preferred embodiment of the present invention.

[0010] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0011] Explanation of symbols

[0012] 100 Semiconductor substrate

[0013] 100a Storage unit area

[0014] 100b High voltage component area

[0015] 100c Logic element area

[0016] 102 Shallow Trench Isolation Structure

[0017] 104 Gate Oxide

[0018] 106 Field Oxide Layer

[0019] 108 Floating Gate

[0020] 110 Sacrificial Layer

[0021] 111 Inter-gate dielectric layer

[0022] 112 Next door

[0023] 114 Photoresist

[0024] 116 Control gate groove

[0025] 118 Polysilicon layer

[0026] 118a Dummy control gate

[0027] 118b Clearance

[0028] 118c word line

[0029] 118d Gate

[0030] 119 Oxide layer

[0031] 120 Overlay

[0032] 122 Silicon nitride layer

[0033] 124 Silicon oxide layer

[0034] 126 Photoresist

[0035] 127 Oxide layer

[0036] 128 dummy gate

[0037] 130 Photoresist

[0038] 132 Source / Drain

[0039] 134 Contact Etch Stop Layer

[0040] 136 Interlayer Dielectric Layer

[0041] 138 Control gate groove

[0042] 140 Gate groove

[0043] 142 Metal control grid

[0044] 144 Metal Gate

[0045] 146 Word line groove

[0046] 148 Clearing the grid groove

[0047] 150 Metal word line

[0048] 152 Metal Removal Grid

[0049] 154 Contacts

[0050] P1 Photolithography Process

[0051] P2 Chemical Mechanical Planarization Process

[0052] P3 Photolithography Process

[0053] P4 Photolithography Process

[0054] P5 Chemical Mechanical Planarization Process

[0055] P6 Photolithography Process DETAILED DESCRIPTION

[0056] Now, the exemplary embodiments of the present invention will be described in detail below, and the features described will be shown with reference to the accompanying drawings so that the reader can understand and achieve the technical effects. The reader will understand that the description in the text is only by way of example and is not intended to limit the present invention. The various embodiments of the present invention and the various features that do not conflict with each other in the embodiments can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention are understandable to those skilled in the art and are intended to be included in the scope of the present invention.

[0057] Readers should be able to easily understand that the meanings of "on", "over" and "above" in this case should be interpreted in a broad manner, so that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intervening feature or layer, and "on" or "above" not only means "on" or "above" something but also includes the meaning of being "on" or "above" something with no intervening features or layers (i.e., directly on something). In addition, spatially related terms such as "under", "below", "lower", "over", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or feature and another or more elements or features, as shown in the accompanying drawings.

[0058] As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0059] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (where contacts, interconnects and / or vias are formed) and one or more dielectric layers.

[0060] The reader can generally understand the term at least in part from the usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an", "the", or "said" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0061] The reader can further understand that when the words "include" and / or "contain" are used in this specification, they specify the existence of the stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0062] Now the following will refer to Figures 1 to 13The following is a cross-sectional diagram of the manufacturing process of an embedded flash memory (eFlash) structure in the preferred embodiment of the present invention. The relative positions of the components involved in the manufacturing process of the present invention in the vertical direction and the connection relationship between them are illustrated in the form of a cross-sectional diagram. The manufacturing method of the present invention is generally applied to the integration of the logic manufacturing process of embedded flash memory and high-k metal gate (HKMG), but is not limited to this. It should be noted that for the sake of simplicity, only half of the memory structure will be drawn in the figure, and the complete memory structure will be shown in the last Fig.17 There will be detailed instructions.

[0063] First, please refer to Figure 1 . At the beginning of the manufacturing process, a semiconductor substrate 100 is provided as a foundation for setting up the semiconductor element of the present invention. The material of the semiconductor substrate 100 is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, such as a III-V silicon-coated substrate (such as GaN-on-silicon) or a silicon-on-insulator (SOI) substrate, or other doping types of substrates, but are not limited thereto. The semiconductor substrate 100 may include a memory cell area 100a, a high-voltage component area 100b, and a logic component area 100c, which are respectively used to set up components with different functions such as memory, high-voltage components, core components, and input / output components. In an embodiment of the present invention, the substrate height of the logic component area 100c may be higher than the substrate heights of the memory cell area 100a and the high-voltage component area 100b, such as a fin structure. A shallow trench isolation (STIs) 102 is formed in the semiconductor substrate 100. The material of the STIs 102 may be silicon oxide, and is used to divide and isolate different active regions. A gate oxide layer 104 is formed on the semiconductor substrate 100 as a barrier layer between the gate and the semiconductor substrate 100. The thickness of the gate oxide layer 104 on the high voltage component region 100b is greater than the thickness of the gate oxide layer 104 on the memory cell region 100a. A field oxide layer 106 may also be formed on the memory cell region 100a as a barrier layer between the subsequent erase gate and the source line.

[0064] Re-reference Figure 1. In an embodiment of the present invention, a floating gate 108 is pre-formed on the memory cell region 100a, which is located on both sides of the field oxide layer 106 (the figure shows the structure of only one side) and is blocked by a gate oxide layer 104 between the semiconductor substrate 100. The floating gate 108 may be made of polysilicon, and a sacrificial layer 110 may be formed thereon as a layer structure for subsequently forming a dummy control gate. There is an inter-gate dielectric layer 111 blocking the sacrificial layer 110 and the floating gate 108, such as a silicon oxide layer. The material of the sacrificial layer 110 and the inter-gate dielectric layer 111 has etching selectivity, such as silicon nitride, and its pattern is similar to that of the floating gate 108 in the direction perpendicular to the substrate. A spacer 112 is also formed on the outside of the floating gate 108 and the sacrificial layer 110 as a blocking structure between the floating gate 108 and the sacrificial layer 110 and the word line. In the embodiment of the present invention, the sacrificial layer 110 is also formed on the logic device region 100c but not on the high voltage device region 100b, so that different layer structures can be formed on the logic device region 100c and the high voltage device region 100b in subsequent manufacturing processes.

[0065] Please refer to Figure 2 . After providing the above structure, a photolithography process P1 is then performed to form a predetermined control gate groove 116 in the sacrificial layer 110 on the memory cell area 100a. The specific steps of the photolithography process P1 include first forming a photoresist 114 on the entire semiconductor substrate 100, and defining the control gate pattern through exposure, development and other steps, and then performing an etching process using the photoresist 114 as a mask to remove the sacrificial layer 110 exposed from the groove pattern until the inter-gate dielectric layer 111 below is exposed, thereby forming a control gate groove 116. This control gate groove 116 will be used as a accommodating space for a dummy control gate in subsequent manufacturing processes. It should be noted that in the embodiment of the present invention, since the control gate groove 116 is formed by a photolithography process rather than a self-alignment process, the sacrificial layer 110 will remain on at least one side of the control gate groove 116, and the control gate grooves 116 on both sides of the clear gate 118b may not be symmetrical with the clear gate 118b as the center line.

[0066] Please refer to Figure 3. After the control gate groove 116 is formed, a deposition process is then performed to sequentially form a polysilicon layer 118 and an oxide layer 119 on the semiconductor substrate 100. The polysilicon layer 118 can be formed by low pressure chemical vapor deposition (LPCVD) or chemical vapor deposition (CVD), and the oxide layer 119 can be formed by CVD. As shown in the figure, the polysilicon layer 118 will cover the sacrificial layer 110 of the logic element area 100c, the gate oxide layer 104 of the high voltage element area 100b, and the field oxide layer 106, sacrificial layer 110 and spacer 112 of the memory cell area 100a, and its thickness in the vertical direction must be large enough to fill the control gate groove 116. The thinner oxide layer 119 is formed on the polysilicon layer 118 in a conformal manner. Furthermore, since the logic element region 100c and the memory cell region 100a have a relatively protruding sacrificial layer structure, the polysilicon layer 118 and the oxide layer 119 formed on the two regions are also higher than the portion on the high voltage element region 100b. Since there is no sacrificial layer 110, the high voltage element region 100b is filled with the polysilicon layer 118.

[0067] Please refer to Figure 4 . After the polysilicon layer 118 and the oxide layer 119 are formed, a chemical mechanical planarization (CMP) process P2 is then performed to planarize the surface of the semiconductor substrate 100. As shown in the figure, the CMP process P2 will remove the oxide layer 119, the polysilicon layer 118, the sacrificial layer 110 and the spacer 112 structures above a certain height. In this way, the polysilicon layer 118 on the logic element area 100c will be completely removed and part of the sacrificial layer 110 will be removed, the high-voltage element area 100b will be filled with the polysilicon layer 118, and the polysilicon layer 118 on the memory cell area 100a will form a dummy control gate 118a located in the control gate groove 116 and a clear gate 118b located on the field oxide layer 106. After the CMP process P2, the top surfaces of the layer structures on the logic element area 100c, the high-voltage element area 100b and the memory cell area 100a are flush. In the embodiment of the present invention, an etching process may be performed first to remove the oxide layer 119 on the non-high voltage device region 100 b , and then a CMP process P2 may be performed. After the CMP process P2 , an etching back process may be performed to adjust the height of the above-mentioned flush surface.

[0068] Please refer to Figure 5. After the CMP process P2, a cover layer 120, a silicon nitride layer 122 and a silicon oxide layer 124 are sequentially formed on the same plane. The cover layer 120 can achieve the purpose of shielding a specific area through the relationship between the different heights of each area in the subsequent manufacturing process, and the silicon nitride layer 122 and the silicon oxide layer 124 are used as anti-reflection layer structures in the subsequent photolithography process. The cover layer 120, the silicon nitride layer 122 and the silicon oxide layer 124 can also be used as a hard mask structure to protect the high-voltage component area 100b and the storage unit area 100a in the subsequent photolithography process. The above-mentioned layer structures can be deposited by the CVD process.

[0069] Please refer to Figure 6 . After the cover layer 120, the silicon nitride layer 122 and the silicon oxide layer 124 are formed, a photolithography process P3 is then performed to remove the sacrificial layer 110, the cover layer 120, the silicon nitride layer 122 and the silicon oxide layer 124 on the logic element area 100c. The specific steps of the photolithography process P3 include first forming a photoresist 126 on the entire silicon oxide layer 124, and exposing the entire logic element area through exposure, development and other steps, and then using the photoresist 126 as a mask to perform an etching process to remove the silicon oxide layer 124, the silicon nitride layer 122, the cover layer 120 and the sacrificial layer 110 on the logic element area until the oxide layer 127 and the shallow trench isolation structure 102 below are exposed. In this way, the production of logic elements on the logic element area 100c can begin.

[0070] Please refer to Figure 7 . After removing the layer structure on the logic element area 100c, a dummy gate 128 is then formed on the logic element area 100c. The step of forming the dummy gate 128 may include removing the oxide layer 127 on the logic element area 100c, forming a gate oxide layer and a polysilicon layer on the logic element area 100c, patterning the polysilicon layer to form a dummy gate 128, forming spacers on both sides of the dummy gate 128, and forming a lightly doped drain (LDD) and other structures in the semiconductor substrate 100 of the logic element area 100c. Since the components of the above-mentioned logic element and its related manufacturing process are prior art and are not the focus of the present invention, the detailed description thereof will be omitted herein, and only 128 is marked in the figure to represent the dummy gate.

[0071] Please refer to Figure 8. After the dummy gate 128 is formed, a photolithography process P4 is then performed to pattern the polysilicon layer 118, the capping layer 120, the silicon nitride layer 122, and the silicon oxide layer 124 on the high-voltage component area 100b, thereby forming a gate 118d of the high-voltage component on the high-voltage component area 100b. It should be noted that in the embodiment of the present invention, the photolithography process P4 will also pattern the polysilicon layer 118 on the storage cell area 100a, thereby forming a word line 118c of the embedded flash memory. The specific steps of the photolithography process P4 include first forming a photoresist 130 on the entire semiconductor substrate 100. The photoresist 130 generally covers the entire logic component area 100c, and forms a gate pattern on the high-voltage component area 100b through exposure, development and other steps. The photoresist 130 also covers the clear gate 118b, the floating gate 108, the spacer 112, and the predetermined word line 118c on the memory cell area 100a. Then, the photoresist 130 is used as a mask to perform an etching process to remove the silicon oxide layer 124, the silicon nitride layer 122, the cap layer 120, the polysilicon layer 118, and the gate oxide layer 104 exposed from the photoresist 130, until the semiconductor substrate 100 and the shallow trench isolation structure 102 below are exposed, so as to form the gate 118d on the high-voltage device area 100b and the word line 118c on the memory cell area 100a. From the above embodiment, it can be seen that the gate 118d on the high-voltage device area 100b, the word line 118c on the memory cell area 100a, the dummy control gate 118a, and the clear gate 118b of the present invention are all formed from the original polysilicon layer 118.

[0072] Please refer to Fig. 9. After the gate 118d and the word line 118c are formed, the photoresist 130 is then removed, and an ion implantation process is performed to dope the semiconductor substrate 100 to form a source / drain 132. The source / drain 132 is formed in the semiconductor substrate 100 on both sides of the dummy gate 128, on both sides of the gate 118d, and outside the word line 118c. In some embodiments, a silicon germanium (SiGe) epitaxial structure may be first formed in the semiconductor substrate 100 and then doped to form the source / drain 132. Thereafter, the silicon nitride layer 122 and the silicon oxide layer 124 as an anti-reflective layer are removed, and a contact etch stop layer (CESL) 134 and an interlayer dielectric layer (ILD) 136 are sequentially formed on the surface of the semiconductor substrate 100 by a deposition process. The material of the contact etch stop layer (CESL) 134 may be silicon nitride, which may be conformally formed on the substrate surface by CVD or other suitable processes. In addition to being an etching stop layer, the contact etch stop layer 134 can also achieve a local strained silicon effect on the contacted components. The material of the interlayer dielectric layer 136 can be porous silicon oxide, which can be formed by a deposition process with good gap filling capability, such as high aspect ratio process (HARP), high density plasma chemical vapor deposition (HDP-CVD), and spin coating. It should be noted that at this stage, only the cover layer 120 remains on the structures of the high voltage component area 100b and the logic component area 100c. The cover layer 120 on the logic component area 100c has been Figure 6 However, since the semiconductor substrate 100 in the logic element region 100 c is higher, the top surface heights of the contact etching stop layers 134 deposited in the three regions are substantially the same.

[0073] Please refer to Fig.10 . After the contact etch stop layer 134 and the interlayer dielectric layer 136 are formed, a CMP process P5 is then performed to flatten the surface of the semiconductor substrate 100. As shown in the figure, the CMP process P5 will remove the interlayer dielectric layer 136 and the contact etch stop layer 134 above a certain height, so that the interlayer dielectric layer 136 on the contact etch stop layer 134 above the dummy gate 128, the gate 118d and the flash memory structure will be removed, and the remaining interlayer dielectric layer 136 will fill the space between the dummy gate 128, the gate 118d and the flash memory structure. After this CMP process P5, the contact etch stop layer 134 above the dummy gate 128, the gate 118d and the flash memory structure will be flush with the surrounding interlayer dielectric layer 136.

[0074] Please refer to Fig.11. After the CMP process P5, a photolithography process P6 is then performed to remove the contact etch stop layer 134 and a portion of the cover layer 120 on the dummy control gate 118a of the memory cell area 100a. The purpose of this step is to make the layer structure thickness on the dummy gate 128 of the logic element area 100c and the dummy control gate 118a of the memory cell area 100a the same, for example, only the contact etch stop layer 134 is left on the dummy gate 128, and only a thin cover layer 120 is left on the dummy control gate 118a, so that the dummy gate 128 and the dummy control gate 118a on the two areas can be removed simultaneously in the subsequent process of removing the dummy gate.

[0075] Please refer to Fig.12 . After the photolithography process P6, the photoresist is then removed, and a removal process is performed to simultaneously remove the dummy gate 128 on the logic element area 100c and the dummy control gate 118a on the storage cell area 100a. This removal process can be a dry etching process, a wet etching process, a back etching process, or one or more other available processes for polysilicon materials, such as a wet etching process using ammonia as an etching solution. The layer structures such as the contact etch stop layer 134 and the covering layer 120 remaining on the original dummy gate 128 and the dummy control gate 118a can also be removed in this process. The gate 118d on the high-voltage element area 100b is not affected by the above-mentioned removal process because it is blocked by the contact etch stop layer 134 and the thicker covering layer 120. After the dummy gate 128 and the dummy control gate 118 a are removed, a gate groove 140 and a control gate groove 138 are formed at their original positions, respectively, which can accommodate the metal gate and metal control gate structures to be formed subsequently.

[0076] Please refer to Fig.13 After the gate groove 140 and the control gate groove 138 are formed, a metal gate replacement (RMG) process is then performed to form a metal gate 144 and a metal control gate 142 in the gate groove 140 and the control gate groove 138, respectively. The specific steps of the RMG process may include first forming a high-k dielectric layer in the groove, and the material thereof may include but is not limited to HfO X ,HfSiO X ,HfSiON,ZrO2,HfZrO X ,AlO X or TiO XThen, metal layers such as work function metal (select appropriate metal materials according to the required work function), barrier metal (barrier, such as Ti, Ta), and low resistance metal (such as Al) are formed in the groove. The above-mentioned various metal layers can be multi-layer metal layers, which can be distributed in a U-shape along the groove surface, or fill the entire groove, or a combination of the two. In addition, the present invention is not limited to the high-k last manufacturing process. In other embodiments, such as the high-k first manufacturing process, the high dielectric constant dielectric layer can also be formed in the previous Figure 7 The dummy gate 128 is formed in advance in the step of forming the dummy gate 128 , so that the high-k dielectric layer is only present on the logic element region 100 c .

[0077] Due to the presence of the capping layer 120, the top surface of the metal control gate 142 formed on the memory cell region 100a may be higher than the top surface of the surrounding sacrificial layer 110 and flush with the capping layer 120. Since the detailed structure of the metal gate element and its related manufacturing process are prior art, the detailed description will be omitted herein, and only the reference numerals 142 and 144 are used to represent the metal control gate and the metal gate including the above components, respectively.

[0078] Now the following will refer to Figures 14 to 16 The manufacturing process of an embedded flash memory structure in another embodiment of the present invention is described. The difference between the embedded flash memory structure and the aforementioned embodiment is that the word lines and clear gates of the embedded flash memory structure are also integrated and manufactured using the HKMG manufacturing process.

[0079] First, please refer to Fig.14 The preparatory steps of this embodiment are similar to Fig.10 The previous steps are similar, and the steps are also performed to complete the CMP process P5. The difference is that the predetermined height of the CMP process P5 is lower than Fig.10 The flush height of the embodiment enables the contact etch stop layer 134 located above the dummy gate 128, the gate 118d and the flash memory structure to be completely removed, and even a portion of the dummy gate 128 with a higher height will be removed. In addition, in this embodiment, the height of the gate 118d on the high-voltage component area 100b is not the same height as the word line 118c on the memory cell area 100a formed at the same time, but is lower than its height. In this way, after the CMP manufacturing process P5, a portion of the cover layer 120 will remain on the gate 118d, which can be used as a barrier layer in the subsequent step of removing the polysilicon layer to prevent the gate 118d on the high-voltage component area 100b from being removed.

[0080] Please refer to Fig.15After the CMP process P5, a removal process is then directly performed to remove the exposed polysilicon layer in each region, including the dummy gate 128 on the logic element region 100c and the word line 118c, dummy control gate 118a and clear gate 118b on the memory cell region 100a. Since the previous CMP process P5 directly polishes the dummy gate 128 and the dummy control gate 118a to be exposed, this embodiment does not need to be performed as described above. Fig.11 Generally, a photolithography process P6 is performed to adjust the thickness of the cover layer 120. The gate 118d on the high voltage device region 100b is not affected by the removal process because it is blocked by the remaining cover layer 120. In this way, after the dummy gate 128, the word line 118c, the dummy control gate 118a and the clear gate 118b are removed, the original positions will form a gate groove 140, a word line groove 146, a control gate groove 138 and a clear gate groove 148, which can respectively accommodate the metal gate, metal word line, metal control gate structure and metal clear gate structure to be formed later.

[0081] Please refer to Fig.16 After the gate groove 140, the word line groove 146, the control gate groove 138 and the clear gate groove 148 are formed, Fig.13 In the embodiment, the RMG process is then performed to integrate the metal gate 144, the metal word line 150, the metal control gate 142 and the metal clear gate 152 in the gate groove 140, the word line groove 146, the control gate groove 138 and the clear gate groove 148 respectively. The above-mentioned metal structures may include the aforementioned high-k dielectric layer, work function metal layer, barrier metal, low-resistance metal, etc., and their top surfaces are flush with the remaining sacrificial layer 110 on the memory cell 100a. The various metal layers mentioned above may be multi-layer metal layers, which may be distributed in a U-shape along the groove surface, or fill the entire groove, or a combination of the two. In addition, the present invention is not limited to the high-k last manufacturing process. In other embodiments, such as the high-k first manufacturing process, the high-k dielectric layer may also be previously Figure 7 The dummy gate 128 is formed in advance, so that only the logic element region 100c has a high dielectric constant dielectric layer. Since the details of the above metal gate and its related manufacturing process are prior art and not the focus of the present invention, the detailed description will be omitted in the text, and the metal structures including the above components will be represented by reference numerals 144, 150, 142, and 152 in the figure.

[0082] Now please refer to Fig.17, which is a cross-sectional schematic diagram of an embedded flash memory structure according to a preferred embodiment of the present invention. According to the manufacturing process shown in the above embodiment, the present invention also proposes a novel embedded flash memory structure, as shown in the figure, the structure includes a semiconductor substrate 100, a clear gate 118b located on the semiconductor substrate 100, and a field oxide layer 106 is provided between the clear gate 118b and the semiconductor substrate 100, two floating gates 108 are respectively located on the semiconductor substrate 100 on both sides of the clear gate 118b, and a gate oxide layer 104 is provided between the floating gate 108 and the semiconductor substrate 100, and two word lines 118c are respectively provided on the two floating gates 108. On the outside, there is a gate oxide layer 104 between the word line 118c and the semiconductor substrate 100, and there is a spacer 112 between the word line 118 and the floating gate 108, and two metal control gates 142 are respectively located on the two floating gates 108, wherein at least one side of the metal control gate 142 has a sacrificial layer 110, and the sacrificial layer 110 is between the metal control gate 142 and the clear gate 118b or between the metal control gate 142 and the word line 118c, and the two metal control gates 142 may not be symmetrical with the clear gate 118b as the center line. There is an inter-gate dielectric layer 111 between the sacrificial layer 110 and the metal control gate 142 and the floating gate 108. In addition, a contact etch stop layer 134 may be provided on the outside of the two word lines 118c, and an interlayer dielectric layer 136 may be covered on the contact etch stop layer 134 and the entire embedded flash memory structure. The interlayer dielectric layer 136 may have contacts 154 connected to the clear gate 118b, metal control gate 142, word line 118c and other components of the embedded flash memory structure to electrically connect these components to the back-end (BEOL) circuit.

[0083] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An embedded flash memory structure, comprising: Semiconductor substrate; A clear gate is located on the semiconductor substrate; Two floating gates are respectively located on the semiconductor substrate at two sides of the clear gate; two word lines, respectively located outside the two floating gates; and Two metal control gates are respectively located on the two floating gates, wherein at least one side of the metal control gate has a sacrificial layer, and the sacrificial layer is between the metal control gate and the clear gate or between the metal control gate and the word line. 2 . The embedded flash memory structure as claimed in claim 1 , wherein the sacrificial layer is made of silicon nitride. 3 . The embedded flash memory structure as claimed in claim 1 , wherein a top surface of the metal control gate is higher than a top surface of the sacrificial layer. 4 . The embedded flash memory structure as claimed in claim 1 , wherein the word line is a metal word line, the clear gate is a metal clear gate, and top surfaces of the metal word line, the metal clear gate and the metal control gate are flush.

5. The embedded flash memory structure as claimed in claim 1, wherein the semiconductor substrate has a memory cell region and a logic element region, the metal control gate is located on the memory cell region, and a top surface of the metal control gate is flush with a top surface of the metal gate on the logic element region.

6. The embedded flash memory structure as claimed in claim 5, wherein the semiconductor substrate further comprises a high voltage device region, the high voltage device region comprises a polysilicon gate, a top surface of the polysilicon gate is flush with a top surface of the clear gate and a top surface of the word line on the memory cell region, but is lower than a top surface of the metal control gate and a top surface of the metal control gate. 7 . The embedded flash memory structure as claimed in claim 1 , wherein the two metal control gates are not symmetrical with the clear gate as a center line.

8. A method for manufacturing an embedded flash memory structure, comprising: Providing a semiconductor substrate having a memory cell region and a logic element region; forming a floating gate and a sacrificial layer on the floating gate on the memory cell region of the semiconductor substrate; Performing a first photolithography process to form a control gate groove in the sacrificial layer; Performing a first deposition process to form a polysilicon layer on the semiconductor substrate at both sides of the floating gate and in the control gate groove; Performing a first planarization process to remove the polysilicon layer outside the control gate groove, thereby forming a dummy control gate in the control gate groove and a clear gate inside the floating gate; forming a dummy gate on the logic element region; forming a contact hole etching stop layer and an interlayer dielectric layer on the dummy control gate and the dummy gate; Performing a second planarization process to remove a portion of the interlayer dielectric layer and the contact hole etch stop layer until the interlayer dielectric layer is no longer on the top surface of the contact hole etch stop layer; Performing an etching process to simultaneously remove the dummy gate and the dummy control gate, thereby forming a gate groove on the semiconductor substrate in the logic element area and exposing the original control gate groove on the memory cell area; as well as At the same time, metal is filled into the gate groove and the control gate groove to form a metal gate and a metal control gate.

9. The method for manufacturing an embedded flash memory structure as described in claim 8, wherein the second planarization process does not expose the dummy control gate, and a covering layer is provided between the dummy control gate and the contact hole etch stop layer, and further comprises performing a second photolithography process after the second planarization process to remove the contact hole etch stop layer and a portion of the covering layer located on the dummy control gate. 10 . The method for manufacturing an embedded flash memory structure as claimed in claim 8 , further comprising performing a third photolithography process to pattern the polysilicon layer after the dummy gate is formed, so as to form a word line located outside the floating gate.

11. The method for manufacturing an embedded flash memory structure as claimed in claim 10, wherein the semiconductor substrate further has a high voltage device region, and the step of patterning the polysilicon layer by the third photolithography process simultaneously forms the word line located on the memory cell region and the gate located on the high voltage device region.

12. The method for manufacturing an embedded flash memory structure as claimed in claim 11, wherein the second planarization process exposes the dummy gate, the dummy control gate, the word line and the clear gate, and the etching process simultaneously removes the dummy gate, the dummy control gate, the word line and the clear gate, so that the gate groove is formed on the semiconductor substrate in the logic element area and the word line groove and the clear gate groove are formed on the semiconductor substrate in the memory cell area, and the original control gate groove on the memory cell area is exposed.

13. The method for manufacturing an embedded flash memory structure as claimed in claim 12, further comprising simultaneously filling metal into the gate groove, the word line groove, the control gate groove and the clear gate groove to form the metal gate, the metal control gate, the metal word line and the metal clear gate.

Images