Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming an initial groove in the substrate, wherein a wall corner surface is arranged between the side wall surface and the bottom surface of the initial groove; forming a first epitaxial layer on the side wall surface, the bottom surface and the wall corner surface of the initial groove to form a groove, the first epitaxial layer having a first crystal growth rate on the side wall surface, a second crystal growth rate on the bottom surface and a third crystal growth rate on the wall corner surface, the first crystal growth rate and the second crystal growth rate are both greater than the third crystal growth rate; the second epitaxial layer is formed in the groove, so that the groove of which the side wall is relatively vertical to the bottom is formed, the shape of the groove is optimized, and the performance of the formed device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the further development of semiconductor technology, after the characteristic size of transistors is reduced to the nanoscale, the proportional reduction technology faces increasingly severe challenges, such as mobility degradation, source-drain leakage, hot carrier effect, etc. Among them, mobility degradation is the main difficulty affecting the speed improvement of integrated circuits. By improving the mobility of carriers in the channel, the mobility degradation caused by factors such as Coulomb interaction caused by high channel doping, increased effective electric field strength caused by thinning of gate dielectrics, and enhanced interface scattering can be compensated.

[0003] Strained silicon technology introduces strain, i.e. stress change, to the channel layer in the design of device structure and materials to change the lattice structure of the channel layer substrate, thereby increasing the mobility of carriers in the channel layer and improving device performance. Direct epitaxy of channel materials with stress in the channel layer will become a development trend. Germanium silicon materials have become a hot topic in the research of new channel materials due to their high carrier mobility, higher device reliability and compatibility with existing silicon-based processes.

[0004] However, the technology of SiGe channel devices still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an initial groove in the substrate, wherein the initial groove has a corner surface between the side wall surface and the bottom surface; forming a first epitaxial layer on the side wall surface, the bottom surface and the corner surface of the initial groove to form a groove, the first epitaxial layer having a first growth rate on the side wall surface, a second growth rate on the bottom surface, and a third growth rate on the corner surface, the first growth rate and the second growth rate are both greater than the third growth rate; forming a second epitaxial layer in the groove.

[0007] Optionally, the formation process of the first epitaxial layer includes a first epitaxial growth process; the process parameters of the first epitaxial growth process include: the reaction gas includes CH3Cl and H2, wherein the flow rate range of CH3Cl is 5sccm to 200sccm, and the flow rate of H2 is 100sccm to 150sccm. 2 The flow rate range is 10sccm to 500sccm, and the gas pressure range is 2mTorr to 1Torr.

[0008] Optionally, the method for forming the initial groove includes: forming a hard mask layer on the surface of the substrate, the hard mask layer having an opening, the opening exposing a portion of the substrate surface; using the hard mask layer as a mask, etching the substrate to form the initial groove.

[0009] Optionally, the material of the hard mask layer includes one or more of amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0010] Optionally, the hard mask layer has a thickness ranging from 5 nm to 150 nm.

[0011] Optionally, while forming the first epitaxial layer, an amorphous material layer is formed on the surface of the hard mask layer and the sidewalls of the opening; before forming the second epitaxial layer, the method further includes: etching the amorphous material layer until the amorphous material layer on the sidewalls of the opening is removed.

[0012] Optionally, the process of etching the amorphous material layer includes an isotropic dry etching process; and the isotropic dry etching process includes a remote plasma dry etching process.

[0013] Optionally, the method for etching the amorphous material layer includes several cyclic processes, each cyclic process including an oxidation process and an etching process after the oxidation process.

[0014] Optionally, the etching process includes one or a combination of an isotropic dry etching process and a wet etching process; the isotropic dry etching process includes an atomic layer etching process.

[0015] Optionally, the method for forming the second epitaxial layer includes: forming a second epitaxial material layer in the groove, wherein a top surface of the second epitaxial material layer is higher than a top surface of the hard mask layer; and planarizing the second epitaxial material layer to form the second epitaxial layer.

[0016] Optionally, the formation process of the second epitaxial material layer includes a second epitaxial growth process; the process parameters of the second epitaxial growth process include: the reaction gas includes SiH 4 ,GeH 4 and H 2 , the SiH 4 The flow rate range is 50sccm to 3000sccm, the GeH 4 The flow rate range is 50sccm to 3000sccm, the H 2 The flow rate range is 10sccm to 500sccm, and the gas pressure range is 5mTorr to 2Torr.

[0017] Optionally, the material of the second epitaxial layer includes silicon germanium.

[0018] Optionally, the material of the first epitaxial layer is the same as that of the substrate; the material of the first epitaxial layer includes single crystal silicon.

[0019] Optionally, the thickness of the first epitaxial layer is in the range of To 10nm.

[0020] Optionally, after forming the initial groove and before forming the first epitaxial layer, the method further includes: cleaning the initial groove.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first epitaxial layer is formed on the side wall surface, the bottom surface and the corner surface of the initial groove to form a groove, the first epitaxial layer has a first crystal growth rate on the side wall surface, a second crystal growth rate on the bottom surface, and a third crystal growth rate on the corner surface, the first crystal growth rate and the second crystal growth rate are both greater than the third crystal growth rate, the first epitaxial layer reduces the curvature of the corner surface, is conducive to forming a groove with a side wall that is more vertical relative to the bottom, optimizes the morphology of the groove, and improves the performance of the formed device.

[0023] Furthermore, while forming the first epitaxial layer, an amorphous material layer is formed on the surface of the hard mask layer and the side walls of the opening; before forming the second epitaxial layer, the amorphous material layer is also etched until the amorphous material layer on the side walls of the opening is removed, thereby avoiding the situation where abnormal crystal growth of the second epitaxial layer near the interface between the amorphous material layer and the crystalline material layer causes stacking fault defects to be introduced, thereby improving the quality of forming the second epitaxial layer and further improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 5 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0025] Figures 6 to 10 is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0026] Figures 11 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0027] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0028] As described in the background art, the performance of the semiconductor structure formed by the existing germanium silicon channel device technology needs to be improved. Now, the formation process of a semiconductor structure is explained and analyzed.

[0029] Figures 1 to 5 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0030] Please refer to Figure 1 , providing a substrate 101, wherein the substrate 101 includes a first region I and a second region II adjacent to the first region I; forming a mask layer 102 on the substrate 101, wherein the mask layer 102 exposes the first region I.

[0031] Please refer to Figure 2 The substrate 101 is etched by a first dry etching process using the mask layer 102 as a mask to form a first groove 103 in the substrate 101 . A corner surface A is formed at the bottom of the side wall of the first groove 103 .

[0032] Please refer to Figure 3 , continue to etch the first groove 103 using a second dry etching process, remove or reduce the corner surface A, so as to form a second groove 104; after forming the second groove 104, remove the mask layer 102.

[0033] Please refer to Figure 4 , an epitaxial layer 105 is formed in the second groove 104 .

[0034] Please refer to Figure 5 , the epitaxial layer 105 and the substrate 101 are etched to form a first fin 106 in the first region I and a second fin 107 in the second region II.

[0035] In the above method, the first region I is used to form a P-type device, the second region II is used to form an N-type device, and a PN interface is formed between the first region I and the second region II. The material of the first fin 106 is germanium silicon, which can improve the channel electron mobility of the P-type device. The material of the second fin 107 is silicon, which is used to form the channel of the N-type device.

[0036] After the first dry etching process, due to the influence of the dry etching process, for example, the byproducts generated in the etching process are accumulated on the sidewalls of the grooves formed by the previous etching, which will hinder further etching and fail to form an ideal groove with a sidewall perpendicular to the bottom. Instead, a first groove 103 with a bottom width smaller than a top width is formed, that is, a corner surface A (such as Figure 2As shown in FIG. 1 ). The second dry etching process is used to remove or reduce the corner surface A. When the corner surface A is consumed, the sidewall of the first groove 103 is also etched laterally. The more the corner surface A is removed, the more the sidewall of the first groove 103 is bent. Figure 3 As shown, the corner surface B of the formed second groove 104 is significantly smaller than the corner surface A, and the difference between the widest and narrowest parts of the sidewall of the second groove 104, that is, the curvature CR, is significantly increased. The second dry etching process needs to strike a balance between consuming the corner surface A and lateral etching of the sidewall of the first groove 103.

[0037] When the feature size of the device is large, such as above the 10 nanometer process node, the CR is controlled within 26 nanometers, and the impact on the formed device is small. However, as the feature size of CMOS technology is further reduced, the fin spacing is further reduced. Near the interface between the first region I and the second region II (i.e., the PN interface), when the corner surface B is large, the bottom of the first fin 106 formed in the first region I is mixed with silicon material (such as Figure 5 When the curvature CR is large, the epitaxial layer 105 will extend laterally to the first region I, which may cause the second fin 107 to be mixed with germanium silicon material. At the same time, the poor morphology of the second groove 104 will also lead to irregular PN interface. The smaller the characteristic size of the device, the greater the impact on the device performance. Therefore, the morphology of the second groove 104 needs to be further improved.

[0038] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, wherein a first epitaxial layer is formed on the side wall surface, the bottom surface and the corner surface of the initial groove to form a groove, the first epitaxial layer has a first crystal growth rate on the side wall surface, a second crystal growth rate on the bottom surface, and a third crystal growth rate on the corner surface, the first crystal growth rate and the second crystal growth rate are both greater than the third crystal growth rate, the first epitaxial layer reduces the curvature of the corner surface, which is conducive to forming a groove with a side wall that is more vertical relative to the bottom, optimizing the morphology of the groove, and improving the performance of the formed device.

[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 6 to 10 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0041] Please refer to Figure 6 , providing a substrate 201.

[0042] In this embodiment, the material of the substrate 201 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0043] Please refer to Figure 7 An initial groove 202 is formed in the substrate 201, and a corner surface D is provided between the side wall surface and the bottom surface of the initial groove 202.

[0044] The method for forming the initial groove 202 includes: forming a hard mask layer 203 on the surface of the substrate 201, wherein the hard mask layer 203 has an opening 204, and the opening 204 exposes a portion of the surface of the substrate 201; using the hard mask layer 203 as a mask, etching the substrate 201 to form the initial groove 202.

[0045] The material of the hard mask layer 203 includes one or more of amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0046] The hard mask layer 203 may be a single-layer film or a multi-layer film structure. In this embodiment, the hard mask layer 203 is a single layer, and the material of the hard mask layer 203 is silicon nitride.

[0047] In this embodiment, the process for forming the initial groove 203 includes an anisotropic dry etching process.

[0048] It should be noted that due to the influence of the dry etching process, if the by-products produced during the etching process accumulate on the side walls of the groove formed by the previous etching, it will have a blocking effect on further etching, and it is impossible to form an ideal groove with side walls perpendicular to the bottom. Instead, the initial groove 202 with a bottom width smaller than the top width is formed, that is, a corner surface D is formed. The subsequent purpose is to improve the morphology of the initial groove 202.

[0049] Please refer to Figure 8 A first epitaxial layer 205 is formed on the side wall surface, the bottom surface and the corner surface D of the initial groove 202 to form a groove 206. The first epitaxial layer 205 has a first growth rate on the side wall surface, a second growth rate on the bottom surface, and a third growth rate on the corner surface D. The first growth rate and the second growth rate are both greater than the third growth rate.

[0050] Here, since the third crystal growth rate of the corner surface D is relatively small, the first epitaxial layer 205 reduces the curvature of the corner surface D, which is conducive to forming a groove 206 with a side wall that is relatively vertical relative to the bottom, optimizing the morphology of the groove 206 and improving the performance of the formed device.

[0051] The material of the first epitaxial layer 205 is the same as that of the substrate 201; the material of the first epitaxial layer 205 includes single crystal silicon. In this embodiment, the first epitaxial layer 205 and the substrate 201 are both single crystal silicon.

[0052] Depending on the crystal direction along which the crystal grows, there are different growth rates. <100> and crystal orientation <110> The generation rate is greater than that along the crystal direction <111> In this embodiment, the sidewall surface of the initial groove 202 is <110> Crystal orientation, bottom surface <100> The crystal direction of the corner surface D is <111> Therefore, during the formation of the first epitaxial layer 205 , the crystal growth rate on the corner surface D is lower than the crystal growth rate on the side wall and the bottom.

[0053] In this embodiment, the thickness of the first epitaxial layer 205 is in the range of The thickness of the first epitaxial layer 205 is selected within a range to avoid being too low to have no effect and to avoid being too high to affect the growth of the subsequent second epitaxial layer.

[0054] In this embodiment, the formation process of the first epitaxial layer 205 includes a first epitaxial growth process.

[0055] In this embodiment, the process parameters of the first epitaxial growth process include: the reaction gas includes CH 3 Cl and H 2 , where CH 3 The flow rate of Cl ranges from 5 sccm to 200 sccm, and H 2 The flow rate range is 10sccm to 500sccm, and the gas pressure range is 2mTorr to 1Torr.

[0056] In this embodiment, after forming the initial groove 202 and before forming the first epitaxial layer 205, the process further includes: cleaning the initial groove 202. The cleaning process is used to remove impurities on the surface of the substrate 201 to facilitate the epitaxial growth of crystals.

[0057] In this embodiment, while forming the first epitaxial layer 205, an amorphous material layer (not shown in the figure) is formed on the surface of the hard mask layer 203 and the sidewall of the opening. Specifically, the material of the amorphous material layer is amorphous silicon.

[0058] It should be noted that the cleaning process is likely to cause lateral etching of the hard mask layer 203, exposing part of the substrate 201 at the bottom of the hard mask layer 203, resulting in the first epitaxial layer 205 being formed at the position of region E, which is likely to cause poor lateral growth of the second epitaxial layer subsequently grown in the groove 206; at the same time, due to the growth of the amorphous material layer on the surface of the hard mask layer 203, there are two materials, amorphous silicon and crystalline silicon, at the position of region E. In the subsequent crystal growth process of the second epitaxial layer, the second epitaxial layer material nucleates on the amorphous material layer and the surface of the first epitaxial layer 205, which is likely to cause stress, thereby causing stacking faults in the second epitaxial layer, affecting the quality of the second epitaxial layer. Therefore, the technical solution of the present invention also provides another embodiment, which reduces the probability of lateral growth and stacking faults of the second epitaxial layer on the basis of optimizing the groove morphology.

[0059] Subsequently, a second epitaxial layer is formed in the groove 206. In this embodiment, the method for forming the second epitaxial layer is described in detail in detail. Fig. 9 and Fig.10 .

[0060] Please refer to Fig. 9 A second epitaxial material layer 207 is formed in the groove 206 , and a top surface of the second epitaxial material layer 207 is higher than a top surface of the hard mask layer 203 .

[0061] In this embodiment, the formation process of the second epitaxial material layer 207 includes a second epitaxial growth process.

[0062] In this embodiment, the process parameters of the second epitaxial growth process include: the reaction gas includes SiH 4 ,GeH 4 and H 2 , the SiH 4 The flow rate range is 50sccm to 3000sccm, the GeH 4 The flow rate range is 50sccm to 3000sccm, the H 2 The flow rate range is 10sccm to 500sccm, and the gas pressure range is 5mTorr to 2Torr.

[0063] In this embodiment, the material of the second epitaxial material layer 207 includes germanium silicon. The second epitaxial material layer 207 is used to form an epitaxial layer.

[0064] Please refer to Fig.10 , planarize the second epitaxial material layer 207 to form the second epitaxial layer 208 .

[0065] In this embodiment, the planarization process includes a mechanochemical polishing process.

[0066] As mentioned above, the technical solution of the present invention also provides another embodiment, which reduces the probability of lateral growth and stacking fault defects of the second epitaxial layer on the basis of optimizing the groove morphology. Figures 11 to 16 .

[0067] please Figures 11 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention.

[0068] Please refer to Fig.11 , providing a substrate 301.

[0069] In this embodiment, the material of the substrate 301 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0070] Please refer to Fig.12 An initial groove 302 is formed in the substrate 301, and a corner surface F is provided between the side wall surface and the bottom surface of the initial groove 302.

[0071] The method for forming the initial groove 302 includes: forming a hard mask layer 303 on the surface of the substrate 301, wherein the hard mask layer 303 has an opening 307, and the opening 307 exposes a portion of the surface of the substrate 301; using the hard mask layer 303 as a mask, etching the substrate 301 to form the initial groove 302.

[0072] In this embodiment, the method for forming the hard mask layer 303 includes: forming a hard mask material layer (not shown in the figure) on the surface of the substrate 301; forming a patterned layer (not shown in the figure) on a portion of the surface of the hard mask material layer; and etching the hard mask material layer using the patterned layer as a mask.

[0073] In this embodiment, the patterned layer includes a spin-coated organic carbon layer, a silicon-containing anti-reflective coating layer located on the spin-coated organic carbon layer, and a photoresist layer located on the silicon-containing anti-reflective coating layer.

[0074] The material of the hard mask layer 303 includes one or more of amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0075] The hard mask layer 303 may be a single-layer film or a multi-layer film structure.

[0076] In this embodiment, the hard mask layer 303 is a three-layer film structure. Specifically, the hard mask layer 303 includes a first silicon oxide film layer 304 , a silicon nitride film layer 305 located on the first silicon oxide film layer 304 , and a second silicon oxide film layer 306 located on the silicon nitride film layer 305 .

[0077] In this embodiment, the thickness of the hard mask layer 303 ranges from 5 nm to 150 nm. Selecting a multi-layer film structure and a thicker mask layer is conducive to reducing the probability of exposing the top surface of the substrate 301 due to the lateral etching of the hard mask layer 303 in the subsequent cleaning process, thereby reducing the probability of poor lateral growth of the second epitaxial layer.

[0078] In this embodiment, the formation process of the initial groove 302 includes an anisotropic dry etching process. The anisotropic etching process is beneficial to improving the morphology of the initial groove 302, but due to the influence of the dry etching process, the sidewall and the bottom of the initial groove 302 form a corner surface F, and the subsequent purpose is to improve the morphology of the initial groove 302.

[0079] Please refer to Fig.13 A first epitaxial layer 308 is formed on the side wall surface, the bottom surface and the corner surface F of the initial groove 302 to form a groove 309. The first epitaxial layer 308 has a first growth rate on the side wall surface, a second growth rate on the bottom surface, and a third growth rate on the corner surface F. The first growth rate and the second growth rate are both greater than the third growth rate.

[0080] Here, since the third crystal growth rate of the corner surface F is relatively small, the first epitaxial layer 308 reduces the curvature of the corner surface F, which is conducive to forming a groove 309 with a side wall that is relatively vertical relative to the bottom, optimizing the morphology of the groove 309 and improving the performance of the formed device.

[0081] In this embodiment, after forming the initial groove 302 and before forming the groove 309 , the patterned layer on the surface of the hard mask layer 303 is removed.

[0082] The material of the first epitaxial layer 308 is the same as that of the substrate 301; the material of the first epitaxial layer 308 includes single crystal silicon. In this embodiment, the first epitaxial layer 308 and the substrate 301 are both single crystal silicon.

[0083] Depending on the crystal direction along which the crystal grows, there are different growth rates. <100> and crystal orientation <110> The generation rate is greater than that along the crystal direction <111> In this embodiment, the sidewall surface of the initial groove 202 is <110> Crystal orientation, bottom surface <100> The crystal direction of the corner surface F is <111> Therefore, during the formation of the first epitaxial layer 308 , the crystal growth rate on the corner surface F is lower than the crystal growth rate on the side wall and the bottom.

[0084] In this embodiment, the thickness of the first epitaxial layer 308 is in the range of The thickness of the first epitaxial layer 308 is selected within a range to avoid being too low to be effective and too high to affect the growth space of the subsequent second epitaxial layer.

[0085] In this embodiment, the formation process of the first epitaxial layer 308 includes a first epitaxial growth process.

[0086] In this embodiment, the process parameters of the first epitaxial growth process include: the reaction gas includes CH 3 Cl and H 2 , where CH 3 The flow rate of Cl ranges from 5 sccm to 200 sccm, and H 2 The flow rate range is 10sccm to 500sccm, and the gas pressure range is 2mTorr to 1Torr.

[0087] In this embodiment, after forming the initial groove 302 and before forming the first epitaxial layer 309, the initial groove 302 is cleaned. The cleaning process is used to remove impurities on the surface of the substrate 301, which is beneficial to the epitaxial growth of the crystal.

[0088] In this embodiment, the second silicon oxide film layer 306 is removed simultaneously during the cleaning process.

[0089] In this embodiment, while forming the first epitaxial layer 308 , an amorphous material layer 310 is formed on the surface of the hard mask layer 303 and the sidewalls of the opening 307 .

[0090] In this embodiment, the material of the amorphous material layer 310 is amorphous silicon.

[0091] In this embodiment, in order to reduce the probability of stacking fault defects in the second epitaxial layer, before forming the second epitaxial layer, please refer to Fig.14 .

[0092] Please refer to Fig.14, the amorphous material layer 310 is etched until the amorphous material layer 310 on the sidewall of the opening 307 is removed.

[0093] Here, the amorphous material layer 310 on the side wall of the opening 307 is removed to avoid the situation where the second epitaxial layer near the interface between the amorphous material layer and the crystalline material layer grows abnormally and introduces stacking fault defects, thereby improving the quality of forming the second epitaxial layer and further improving the performance of the device.

[0094] The process of etching the amorphous material layer 310 includes an isotropic dry etching process; the isotropic dry etching process includes a remote plasma dry etching process. In the process of etching the amorphous material layer 310, the first epitaxial layer 308 will also be etched. The isotropic dry etching process can reduce the impact on the curvature of the corner surface F.

[0095] The process parameters of the remote plasma dry etching process include: the etching gas includes a halogen gas, and the halogen gas includes Cl 2 NF 3 , HBr and SF 6 A combination of one or more of the following, wherein the etching gas further comprises H 2 , Ar, He or a combination of one or more thereof, wherein Cl 2 Flow rate range is 100sccm to 1000sccm, NF 3 The flow rate range is 10sccm to 500sccm, H 2 The flow rate range is 10sccm to 500sccm, the Ar flow rate range is 100sccm to 1000sccm, the He flow rate range is 100sccm to 1000sccm, the HBr flow rate range is 100sccm to 1000sccm, the SF6 flow rate range is 5sccm to 200sccm, and the power range is 100W to 5000W.

[0096] In this embodiment, the etching selectivity ratio of the process of etching the amorphous material layer to the first epitaxial layer 308 and the amorphous material layer 310 is 1:1.

[0097] In another embodiment, the method for etching the amorphous material layer includes several cyclic processes, each of which includes an oxidation process and an etching process after the oxidation process. The several cyclic processes are conducive to improving etching uniformity and controlling the accuracy of etching rate.

[0098] In another embodiment, the etching process includes one or a combination of an isotropic dry etching process and a wet etching process; the isotropic dry etching process includes an atomic layer etching process. The atomic layer etching process is beneficial to improving etching uniformity and controlling the accuracy of etching rate.

[0099] Subsequently, a second epitaxial layer is formed in the groove 309. In this embodiment, the method for forming the second epitaxial layer is described in detail in detail in detail. Fig.15 and Fig.16 .

[0100] Please refer to Fig.15 A second epitaxial material layer 311 is formed in the groove 309 , and a top surface of the second epitaxial material layer 311 is higher than a top surface of the hard mask layer 303 .

[0101] Specifically, the top surface of the second epitaxial material layer 311 is higher than the top surface of the silicon nitride film layer 305 .

[0102] In this embodiment, the formation process of the second epitaxial material layer 311 includes a second epitaxial growth process.

[0103] In this embodiment, the process parameters of the second epitaxial growth process include: the reaction gas includes SiH 4 ,GeH 4 and H 2 , the SiH 4 The flow rate range is 50sccm to 3000sccm, the GeH 4 The flow rate range is 50sccm to 3000sccm, the H 2 The flow rate range is 10sccm to 500sccm, and the gas pressure range is 5mTorr to 2Torr.

[0104] In this embodiment, the material of the second epitaxial material layer 311 includes germanium silicon. The second epitaxial material layer 311 is used to form an epitaxial layer.

[0105] Please refer to Fig.16 , planarizing the second epitaxial material layer 311 to form the second epitaxial layer 312 .

[0106] In this embodiment, specifically, the second epitaxial material layer 311 and the silicon nitride film layer 305 are planarized until the first silicon oxide film layer 304 is exposed.

[0107] In this embodiment, the planarization process includes a mechanochemical polishing process.

[0108] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an initial groove in the substrate, wherein a corner surface is provided between a side wall surface and a bottom surface of the initial groove; Forming a first epitaxial layer on the sidewall surface, the bottom surface and the corner surface of the initial groove to form a groove, wherein the first epitaxial layer has a first crystal growth rate on the sidewall surface, a second crystal growth rate on the bottom surface, and a third crystal growth rate on the corner surface, and the first crystal growth rate and the second crystal growth rate are both greater than the third crystal growth rate; A second epitaxial layer is formed in the recess.

2. The method for forming a semiconductor structure according to claim 1, wherein: The formation process of the first epitaxial layer includes a first epitaxial growth process; the process parameters of the first epitaxial growth process include: the reaction gas includes CH3Cl and H2, wherein the flow range of CH3Cl is 5sccm to 200sccm, the flow range of H2 is 10sccm to 500sccm, and the gas pressure range is 2mTorr to 1Torr.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the initial groove comprises: forming a hard mask layer on the surface of the substrate, wherein the hard mask layer has an opening, and the opening exposes a portion of the substrate surface; using the hard mask layer as a mask, etching the substrate to form the initial groove.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the hard mask layer includes one or more of amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

5. The method for forming a semiconductor structure according to claim 3, wherein: The thickness of the hard mask layer is in a range of 5 nm to 150 nm.

6. The method for forming a semiconductor structure according to claim 3, wherein: While forming the first epitaxial layer, forming an amorphous material layer on the surface of the hard mask layer and the sidewall of the opening; Before forming the second epitaxial layer, the method further includes: etching the amorphous material layer until the amorphous material layer on the sidewall of the opening is removed.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process of etching the amorphous material layer includes an isotropic dry etching process; the isotropic dry etching process includes a remote plasma dry etching process.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for etching the amorphous material layer includes several cyclic processes, each of which includes an oxidation process and an etching process after the oxidation process.

9. The method for forming a semiconductor structure according to claim 8, wherein: The etching process includes one of an isotropic dry etching process and a wet etching process or a combination of the two; the isotropic dry etching process includes an atomic layer etching process.

10. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the second epitaxial layer includes: forming a second epitaxial material layer in the groove, wherein the top surface of the second epitaxial material layer is higher than the top surface of the hard mask layer; and planarizing the second epitaxial material layer to form the second epitaxial layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The formation process of the second epitaxial material layer includes a second epitaxial growth process; the process parameters of the second epitaxial growth process include: the reaction gases include SiH4, GeH4 and H2, the flow range of SiH4 is 50sccm to 3000sccm, the flow range of GeH4 is 50sccm to 3000sccm, the flow range of H2 is 10sccm to 500sccm, and the gas pressure range is 5mTorr to 2Torr.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second epitaxial layer includes silicon germanium.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first epitaxial layer is the same as that of the substrate; the material of the first epitaxial layer includes single crystal silicon.

14. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first epitaxial layer is in the range of To 10nm.

15. The method for forming a semiconductor structure according to claim 1, wherein: After forming the initial groove and before forming the first epitaxial layer, the method further includes: cleaning the initial groove.

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