Logic gate transistor, new structure logic gate and data operation method thereof

Abstract

The invention relates to a logic gate transistor, a new-structure logic gate and a data operation method of the new-structure logic gate. The logic gate transistor comprises a gate stack and at least one channel control region which are located in a semiconductor layer; wherein the gate stack comprises a gate electrode and a gate dielectric, the gate electrode controls the semiconductor layer, and the gate dielectric is sandwiched between the gate electrode and the semiconductor layer; a memory effect material in the gate dielectric; a channel electrode is arranged in a channel control area, the channel electrode and a channel form a junction capacitor, and when a logic function is achieved, one function of the channel electrode is to extract voltage from the channel. The logic gate with the novel structure provides a thought of reducing the area of a required circuit and reducing the energy consumption of equipment, can realize a bionic function and a storage and calculation integrated function, and has a good application prospect.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices, and in particular relates to a logic gate transistor, a new structure logic gate and a data operation method thereof. Background Art

[0002] The in-depth development of advanced integrated circuits in the post-Moore era requires core semiconductor devices to make important breakthroughs in new working mechanisms and new material applications. Field effect transistors that replace traditional gate insulating dielectrics with ferroelectric materials have unique intrinsic potential regulation and non-volatile storage of polarized charges, as well as good CMOS integration compatibility. They show low power consumption and high-density integration potential in large-scale logic and storage circuits, new in-memory logic, and brain-like intelligent computing circuits, to meet the needs of developing ultra-low power new principle device technology in the post-Moore era.

[0003] Many existing semiconductor devices have relatively simple functions. For example, they cannot realize logic gate and storage functions at the same time. In addition, the existing logic gate structure occupies a large area, so the storage density is low. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a logic gate transistor, a new structure logic gate and a data operation method thereof, which expands the functions of semiconductor devices and can realize the logic gate and storage functions at the same time. The existing COMS process technology can fully realize or be compatible with the new structure of the present invention. Similarly, the triode process can also propose a new structure for adding a channel electrode, such as Figure 8 shown.

[0005] The present invention provides a logic gate transistor, comprising:

[0006] a gate stack and at least one channel control region in the semiconductor layer;

[0007] Wherein, the gate stack includes a gate electrode and a gate dielectric, the gate electrode controls the semiconductor layer, and the gate dielectric is sandwiched between the gate electrode and the semiconductor layer;

[0008] One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides are used as insulating layer addition layers, insulating layer materials, insulating layer addition materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials to realize logic polymorphism and storage polymorphism;

[0009] A channel electrode is provided in the channel control region.

[0010] The semiconductor substrate and the doped region serve as a source region and a drain region of the logic transistor respectively.

[0011] The at least one channel control region includes a single channel control region at least partially surrounding the gate stack.

[0012] The at least one channel control region is composed of any layer selected from a conductor, a semiconductor, or a stack of a conductor and a semiconductor.

[0013] Optionally, the ferroelectric material is H3S, NbN, LaH 10 、BaTiO3、PbZr x Ti 1-x O3、BiFeO 3、 CIPS (CuIn x P (3-x) S y , such as CuInP2S6), HZO (HfZrO x ), MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 、YBCO(YBa2Cu3O 7-x , such as YBa2Cu3O7), BFMO (BiFe 1-x MnxO3, such as BiFe 0.9 Mn 0.1 O3), PCMO(Pr 1-x CaxMnO3, such as Pr 0.7 Ca 0.3 MnO3), LBCO(La 2-x BaxCuO4, such as La 1.9 Ba 0.1 CuO4), SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx)4As4 (e.g. CaKFe4As4), NdFe 1-x MxDV 0.85 (e.g. NdFeAsO 0.85 ) etc.

[0014] Optionally, the phase change material is VO2, Ge 15 Sb 85 , Ga 36 Sb 64、Fe3O4、NbO2、PEG((C2H4O)n)、Alloys of indium(In) and tin(Sn)、C 60 , C 70 etc.;RMS(Re x Mo 1-x S2)、GST((GeTe) x (Sb2Te3) y ,AIST((Ag 1-x In x )(Sb 1- x Te x )2, such as Ag5In5Sb 60 Te 30 ), GSST (e.g. Ge2Sb2Se1Te4, Ge2Sb2Se4Te1), Gd5 (Si1Ge 1-X )4 (e.g. Gd5Si2Ge2), LaFe 13-x Si x (e.g. LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (For example, La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (e.g. Ge2Sb2Te5), Sb2Te3, GSB((GeSn) x (Sb) y (e.g. GeSnSb), AST((AlSb2) x (Te) y , such as Al 1.5 Sb3Te), TASG(Ti 48 As 30 Si 12 Ge 10 ) one or more of the following.

[0015] Optionally, the magnetoelectric material is ZrTiO4, Fe2O3, Fe3O4, SrBaTiO3, Sr 1-x Ba x TiO3、Bi4Ge3O 12 、BaTiO3、Ba 0.8 Sr 0.2 TiO3, NiO, NiZnFe2O4, LiNbO3, BTO-PZT, BaFe12 O 19 , Cr2O3, BiFeO3, BiMnO3 and LuFe2O4, FCSB(Fe 90 Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(Pb(Zr 1-y Ti y )O3) x , such as Pb(Mg x Nb 1-x )O3-PbZrO3-PbTiO3), PMN-PT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(PbTiO3) x , such as Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3).

[0016] Optionally, the quantum effect material is one or more of YBCO, PbLaTiO3, CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), iron, nickel, cobalt and other magnetic materials.

[0017] Optionally, the resistive switching effect material is ZrO2, TiO2, Ta2O5, BiFeO3, SrRuO3, SrZrO3, Fe3O4, ZnFe2O4, BaTiO3, Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3, Ba(Sr 0.7 Ba 0.3 )TiO3, In2O3-SnO2, Cu2ZnSnSe4, polystyrene (PS), La1-xSrxMnO3, (Pb,Fe)NbO3CuO x (such as CuO 0.5 )、MoS 2-x O4 (such as MoS2O4), HfO x (such as HfO2), WO X (such as WO2), PCMO(Pr 1-x Ca x MnO3, such as Pr 0.7 Ca 0.3 MnO3), LSMO(La x Sr 1-xMnO3, such as La 0.5 Sr 0.5 MnO3), LCMO(La x Ca 1-x MnO3, such as La 0.7 Ca 0.3 MnO3) and the like.

[0018] Optionally, the storage effect material is Fe3O4, Fe2O3, CoFe (cobalt-iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI3, polycarbonate, Si3N4, SiO2, SiO x N y , Se, BaFe 12 O 19 , NiFe, AgCl, AgBr, Ge2Sb2Te5, GeSbTe, Al2O3 / Fe, FeAlO x , polyaniline (PANI) or more.

[0019] Optionally, the superconducting material is H2S, CeCu2Si, CeTIn5, CePt3Si, Ba 0.6 K 0.4 Fe2As2, LaNiC2, LaNiGa2, CaPtAs, Y3Fe5O 12 / Al, 2H-MX2 (M=transition metals; 10-x Cu x (PO4)6, (Li,Fe)OHFeSe, CuInCo2Te4, YBa2Cu3O7 (yttrium alloy copper oxide), Ba(Fe1-xCox)2As2, Pb, MgB2, CuInSe2, LaFeAsO, Ba(Fe,Co)2As2, BSCCO, GdBCO, IBi2Sr2Ca2Cu3O 10 (BSCCO), T l2 One or more of Ba2CuO6, YBa2Fe3Se5.

[0020] Optionally, the semiconductor effect material is one or more of Si, In2Se3, GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al2Se3, AlAs, InAs, SiGe, and CdSe.

[0021] Optionally, the perovskite material is CsPbBr3, MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti x O9, such as SrBiTiO9), BLT (Bi 4-x La x Ti3O 12 , for example, Bi 3.5 La 0.5 Ti3O 12 )、PZT(PbZr 1-x T ix O3. For example, PbZr 0.7 Ti 0.3 O3), Cs 1-x FA x PbBr3, such as Cs 0.8 FA 0.2 One or more of PbBr3, CH3NH3PbX3 (such as CH3NH3PbBr3, CH3NH3PbI3).

[0022] Optionally, the two-dimensional material is one or more of GaS, h-BN, As2Te3, Bi2S3, 2H-WS2, GaSe, GeS, GeSe, HfS2, HfSe2, In2Se3, MoS2, 2H-MoS2, MoTe2, MoSe2, MoSSe, MoWS2, MoWSe2, ReS2, ReSe2, Sb2Te3, SnS2, SnSe2, 1T-TaS2, WSe2, ZrSe2, ZrSe3, and ACS.

[0023] Preferably, the channel electrode is composed of any metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, or any alloy thereof, or any stack thereof. The purpose of the channel electrode is to form a junction capacitor with the connection part, or to extract the local voltage of the connection area, or to regulate the connection area.

[0024] Preferably, a channel electrode is provided in the channel control region, and the channel electrode is separated from the source and the drain; and the at least one channel control region is composed of any stack selected from a conductor, a semiconductor, or a conductor and a semiconductor.

[0025] Preferably, the at least one channel control region is composed of a single layer or a stack of any ferroelectric material, or a stack of any ferroelectric material and a conductor, and the ferroelectric material serves as a gate dielectric between the conductor and the semiconductor layer.

[0026] Optionally, the step of forming the at least one channel control region includes: depositing a conductive material in the at least one second trench to fill the at least one second trench; and etching back the conductive material to form the at least one channel control region, wherein the at least one channel control region is located in the lower portion of the at least one second trench and is separated from the doped region.

[0027] Optionally, the step of forming the at least one channel control region includes: depositing a conductive material in the lower portion of the at least one second trench to form the at least one channel control region, wherein the at least one channel control region is located in the lower portion of the at least one second trench and is separated from the doping region.

[0028] Optionally, the channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

[0029] Optionally, the method further includes: forming a first insulating layer on an upper portion of the at least one second trench.

[0030] Optionally, it also includes: forming a second insulating layer on the doped region; and forming a source electrode, a gate electrode and a channel electrode on the second insulating layer, respectively, wherein the source electrode, the gate electrode and the channel electrode are respectively connected to the doped region, the gate conductor and the channel control region.

[0031] Optionally, the method further includes: forming a source electrode on the second surface of the semiconductor substrate; or forming a source electrode on the surface of the second insulating layer, wherein the source electrode is connected to the semiconductor substrate.

[0032] Optionally, the semiconductor substrate and the doping region are of one doping type of N-type and P-type, and the semiconductor layer is of the other doping type of the N-type and the P-type.

[0033] The present invention also provides a new structure logic gate, which is constructed by multiple logic gate transistors to form one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, and an XNOR gate.

[0034] The present invention also provides an array of logic gates with a new structure, wherein the array unit includes the structure described above, including:

[0035] The drain is connected to the second bit line; the target word line control terminal includes at least one of the first word line and the second word line; the target word line control terminal is used to turn on the transistor; the input gate is connected to at least one of the word lines in a common line, or the multiple gates are connected to the multiple word lines; the channel electrode and the first bit line are connected in a common line; the target word line control terminal is used to achieve the same or different output current control, charge storage, and channel control area channel electrode output voltage extraction of the transistor.

[0036] The present invention also provides a data operation method of a new structure logic gate, comprising:

[0037] In a write operation, a gate voltage is applied via a selected word line among a plurality of word lines, and a first bit line and a second bit line are connected to a control region electrode and a drain, respectively; and a drain voltage is applied via a selected second bit line among a plurality of second bit lines to turn on a selected logic gate transistor, and a control region voltage is extracted from the selected logic gate transistor via a selected first bit line among a plurality of first bit lines to extract a logic state of the selected logic gate transistor; and

[0038] In a read operation, a gate voltage is applied via a selected word line among multiple word lines, and a drain voltage is applied via a selected second bit line among multiple second bit lines to put a selected logic gate transistor into an on state, and, in a case where the multiple first bit lines are disconnected, the drain current of the selected logic transistor is detected via a selected second bit line among the multiple second bit lines to obtain a logic state of the selected logic gate transistor, and, in a case where the multiple first bit lines are connected, a control region voltage of the extraction logic transistor is detected via a selected second bit line among the multiple second bit lines to obtain a logic state of the selected logic gate transistor.

[0039] The present invention can realize all logic gates, and common logic gates include "AND" gate, "OR" gate, "NOT" gate, "XOR" (also known as: exclusive OR), etc. Logic gates can be used in combination to realize more complex logic operations. The new single transistor has a planar transistor structure and a vertical transistor structure, wherein the channel control region extends to the channel region through the opening of the gate, thereby forming a junction capacitance with the channel region. The transistor charges and discharges the junction capacitance formed by the control region and the channel by applying the voltage of the electrode such as the channel control region voltage, and can realize the data storage function, wherein the gate and the control gate voltages are different.

[0040] Basic logic gates are the most basic building blocks in digital circuits and are used to process and manipulate binary signals. The following are common basic logic gates: AND gate, OR gate, NOT gate, XOR gate, XNOR gate, NOR gate, NAND gate; these basic logic gates are the basis of digital circuit design and computer composition, and can be combined to build more complex digital circuits and logic functions.

[0041] The structure of the present invention can be implemented using existing process lines or adjusted based on existing process steps. The channel electrode and control region materials can be semiconductor materials, conductor materials, or a combination of several materials. The actual preparation process may vary depending on factors such as the manufacturer, device size, and process technology. The structure of the present invention can be adjusted based on the subject of the patent.

[0042] The transistor of the present invention can be illustrated by a three-dimensional structure diagram or a two-dimensional structure diagram.

[0043] Beneficial Effects

[0044] The new structure logic gate of the present invention provides a way to reduce the required circuit area and reduce the energy consumption of the device. When realizing the logic function, one function of the channel electrode is to extract the voltage from the channel. This structure can also realize the bionic function and the storage and calculation integrated function, and has a good application prospect;

[0045] The present invention can realize a variety of logic gates, including but not limited to the following: AND gate, OR gate, NOT gate, XOR gate, XNOR gate, NOR gate, and NAND gate; the present invention is based on the above basic logic gates can be used in combination to build various complex digital circuits and logic functions. The following are some common circuits and functions that can be implemented using basic logic gates: Multiplexer: Use AND gate, OR gate and NOT gate combination to realize the function of multiple input signals selecting an output signal. Decoder: Use AND gate and NOT gate combination to realize the function of converting binary code into corresponding output signal. Encoder: Use AND gate and NOT gate combination to realize the function of encoding multiple input signals into binary output. Adder: Use AND gate, OR gate and XOR gate combination to realize the function of adding binary numbers. Counter: Use AND gate, OR gate and trigger combination to realize the function of counting input pulses. Memory: Use trigger combination to realize data storage and reading functions, such as registers, RAM (random access memory), etc. Sequential Logic Circuit: A circuit that uses a combination of triggers and basic logic gates to implement state conversion between storage and memory, such as timing controllers and state machines. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a vertical three-dimensional structural schematic diagram of the logic gate transistor of the present invention;

[0047] Figure 2 A NOT gate (a) of the transistor of the present invention and a dual-input gate (b) of the transistor of the present invention;

[0048] Figure 3A -C is the functional test result of the transistor logic gate of the present invention;

[0049] Figure 4 The single-transistor device structure can realize the NOT logic gate;

[0050] Figure 5 Schematic diagram of a triode structure with a channel electrode added; wherein 101 is a metal layer, 102 is a ferroelectric material, 103 is a gate insulating layer, 104 is a drain, 105 is a source, 106 is a substrate, and 107 is a control gate;

[0051] Figure 6 The storage mechanism of a single transistor made of ferroelectric materials;

[0052] Figure 7a A schematic diagram of a random access storage test result provided by an embodiment of the present invention;

[0053] Figure 7b Another schematic diagram of random access storage test results provided by an embodiment of the present invention;

[0054] Figure 8 It is a schematic diagram of the structure of a ferroelectric single transistor dual-input gate device;

[0055] Fig. 9 A schematic diagram of a new structure of a triode with a channel electrode added;

[0056] Fig.10 FIG. 1 is a schematic circuit diagram of a memory array according to a first embodiment of the present invention. DETAILED DESCRIPTION

[0057] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0058] In this application, the term "semiconductor structure" refers to the collective name of the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. In addition, the terms "semiconductor substrate" and "semiconductor layer" should be interpreted in the broadest sense, including any one of a silicon wafer, an epitaxial layer, and a doped region.

[0059] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "above" another layer or another region, it may mean being directly on the other layer or another region, or having other layers or regions between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" the other layer or another region. If it is to describe the situation of being directly on another layer or another region, this article will use expressions such as "directly on..." or "on and adjacent to...".

[0060] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing techniques and technologies, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, various parts of the semiconductor device can be made of materials known to those skilled in the art.

[0061] The present invention may be embodied in various forms, some examples of which will be described below.

[0062] Depend on Figure 1-2 As shown, this embodiment provides a logic gate transistor, including: a gate stack located in a semiconductor layer and at least one channel control region; wherein the gate stack includes a gate conductor and a gate dielectric, the gate conductor controls the semiconductor layer, and the gate dielectric is sandwiched between the gate conductor and the semiconductor layer; new materials such as ferroelectric materials, phase change materials, perovskite materials, oxide materials, sulfide materials or magnetoelectric materials located in the gate dielectric can realize storage functions; and a channel electrode is arranged in the middle of the channel control region.

[0063] The channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a self-assembly process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

[0064] One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides are used as insulating layer additional layers, insulating layer materials, insulating layer additional materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials.

[0065] Optionally, the ferroelectric material is H3S, NbN, LaH 10 、BaTiO3、PbZr x Ti 1-x O3, BiFeO3, CIPS (CuIn x P (3-x) S y , such as CuInP2S6), HZO (HfZrO x ), MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 、YBCO(YBa2Cu3O 7-x , such as YBa2Cu3O7), BFMO (BiFe 1-x MnxO3, such as BiFe 0.9 Mn 0.1 O3), PCMO(Pr 1-x CaxMnO3, such as Pr 0.7 Ca 0.3 MnO3), LBCO(La 2-x BaxCuO4, such as La 1.9 Ba 0.1 CuO4), SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx)4As4 (e.g. CaKFe4As4), NdFe 1-x MxDV 0.85 (e.g. NdFeAsO 0.85 ) etc.

[0066] Optionally, the phase change material is VO2, Ge 15 Sb 85 , Ga 36 Sb 64 、Fe3O4、NbO2、PEG((C2H4O)n)、Alloys of indium(In) and tin(Sn)、C 60 , C 70 etc.;RMS(Re x Mo 1-x S2)、GST((GeTe) x (Sb2Te3) y ,AIST((Ag 1-x In x )(Sb 1- x Te x)2, such as Ag5In5Sb 60 Te 30 ), GSST (e.g. Ge2Sb2Se1Te4, Ge2Sb2Se4Te1), Gd5 (Si1Ge 1-X )4 (e.g. Gd5Si2Ge2), LaFe 13-x Si x (e.g. LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (For example, La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (e.g. Ge2Sb2Te5), Sb2Te3, GSB((GeSn) x (Sb) y (e.g. GeSnSb), AST((AlSb2) x (Te) y , such as Al 1.5 Sb3Te), TASG(Ti 48 As 30 Si 12 Ge 10 ) one or more of the following.

[0067] Optionally, the magnetoelectric material is ZrTiO4, Fe2O3, Fe3O4, SrBaTiO3, Sr 1-x Ba x TiO3、Bi4Ge3O 12 、BaTiO3、Ba 0.8 Sr 0.2 TiO3, NiO, NiZnFe2O4, LiNbO3, BTO-PZT, BaFe 12 O 19 , Cr2O3, BiFeO3, BiMnO3 and LuFe2O4, FCSB(Fe 90 Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(Pb(Zr 1-y Ti y )O3) x , such as Pb(Mgx Nb 1-x )O3-PbZrO3-PbTiO3), PMN-PT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(PbTiO3) x , such as Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3).

[0068] Optionally, the quantum effect material is one or more of YBCO, PbLaTiO3, CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), iron, nickel, cobalt and other magnetic materials.

[0069] Optionally, the resistive switching effect material is ZrO2, TiO2, Ta2O5, BiFeO3, SrRuO3, SrZrO3, Fe3O4, ZnFe2O4, BaTiO3, Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3, Ba(Sr 0.7 Ba 0.3 )TiO3, In2O3-SnO2, Cu2ZnSnSe4, polystyrene (PS), La1-xSrxMnO3, (Pb,Fe)NbO3CuO x (such as CuO 0.5 )、MoS 2-x O4 (such as MoS2O4), HfO x (such as HfO2), WO X (such as WO2), PCMO(Pr 1-x Ca x MnO3, such as Pr 0.7 Ca 0.3 MnO3), LSMO(La x Sr 1-x MnO3, such as La 0.5 Sr 0.5 MnO3), LCMO(La x Ca 1-x MnO3, such as La 0.7 Ca 0.3 MnO3) and the like.

[0070] Optionally, the storage effect material is Fe3O4, Fe2O3, CoFe (cobalt-iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI3, polycarbonate, Si3N4, SiO2, SiO x N y , Se, BaFe 12 O 19 , NiFe, AgCl, AgBr, Ge2Sb2Te5, GeSbTe, Al2O3 / Fe, FeAlO x , polyaniline (PANI) or more.

[0071] Optionally, the superconducting material is H2S, CeCu2Si, CeTIn5, CePt3Si, Ba 0.6 K 0.4 Fe2As2, LaNiC2, LaNiGa2, CaPtAs, Y3Fe5O 12 / Al, 2H-MX2 (M=transition metals; 10-x Cu x (PO4)6, (Li,Fe)OHFeSe, CuInCo2Te4, YBa2Cu3O7 (yttrium alloy copper oxide), Ba(Fe1-xCox)2As2, Pb, MgB2, CuInSe2, LaFeAsO, Ba(Fe,Co)2As2, BSCCO, GdBCO, IBi2Sr2Ca2Cu3O 10 (BSCCO), T l2 One or more of Ba2CuO6, YBa2Fe3Se5.

[0072] Optionally, the semiconductor effect material is one or more of Si, In2Se3, GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al2Se3, AlAs, InAs, SiGe, and CdSe.

[0073] Optionally, the perovskite material is CsPbBr3, MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti xO9, such as SrBiTiO9), BLT (Bi 4-x La x Ti3O 12 , for example, Bi 3.5 La 0.5 Ti3O 12 )、PZT(PbZr 1-x T ix O3. For example, PbZr 0.7 Ti 0.3 O3), Cs 1-x FA x PbBr3, such as Cs 0.8 FA 0.2 One or more of PbBr3, CH3NH3PbX3 (such as CH3NH3PbBr3, CH3NH3PbI3).

[0074] Optionally, the two-dimensional material is one or more of GaS, h-BN, As2Te3, Bi2S3, 2H-WS2, GaSe, GeS, GeSe, HfS2, HfSe2, In2Se3, MoS2, 2H-MoS2, MoTe2, MoSe2, MoSSe, MoWS2, MoWSe2, ReS2, ReSe2, Sb2Te3, SnS2, SnSe2, 1T-TaS2, WSe2, ZrSe2, ZrSe3, and ACS.

[0075] A channel control region is formed on the side and / or bottom of the channel region in the semiconductor substrate. The channel control region is, for example, composed of any stack selected from a conductor, a semiconductor, or a conductor and a semiconductor. Preferably, the channel control region is composed of any metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, or any alloy thereof, or any stack thereof, for example, the channel control region is composed of Pt. The channel control region is in direct contact with the channel region to form a junction capacitor, such as a Schottky junction capacitor. In the on-state of the logic gate transistor, a suitable voltage is applied via the gate electrode, the drain electrode, the source electrode, and the channel electrode, and through the joint action, the charge is stored and released in the junction capacitor, thereby realizing the write operation of the logic gate transistor. In the on-state of the logic gate transistor, the drain current Ids (i.e., the channel current) of the logic gate transistor is obtained under predetermined bias conditions to characterize the storage state of the charge.

[0076] like Figure 1The working principle of a ferroelectric single transistor with a channel electrode added is shown: The working principle of the transistor involves a heterojunction between the control gate (CG) and the channel. The CG material and the channel material have different work functions, so the contact between them causes directional movement of electrons and holes. When different operating voltages are applied to the transistor, directional movement of charges occurs at the interface between the CG and the channel.

[0077] When VCG=0V, the transistor is in the read state of the memory. At this time, the CG is in contact with the channel and the Fermi level remains consistent. When VCG>0V, the transistor is in the write state of the memory. In this case, the electrons in the conduction band of the channel material will move to the conduction band of the CG material, and the holes in the valence band of the CG material will move to the valence band of the channel material. When VCG<0V, the transistor is in the erase state of the memory. This process is opposite to the write state, that is, the electrons in the conduction band of the CG material will move to the conduction band of the channel material, and the holes in the valence band of the channel material will move to the valence band of the CG material. The charge transfer process between the CG and the channel under different working states can realize the change of the memory state.

[0078] One possible implementation method of the embodiment of the present invention is based on a single transistor with a channel electrode added, and logic gates can be implemented with different input voltages; the classification and characteristics of the logic gates are shown in the following table;

[0079]

[0080] like Figure 2 As shown in a, the present invention realizes NOT gate logic based on adding a channel electrode single transistor.

[0081] like Figure 2 As shown in b, the present invention realizes AND gate, OR gate, NOR gate and NAND gate logic based on adding a channel electrode dual-input single transistor.

[0082] like Figure 3A As shown, in the single transistor dual input gate device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor dual input NAND gate device structure is obtained through experimental measurement. The experiment shows that the single transistor dual input gate device structure can successfully realize the NAND logic gate. By introducing an additional logic gate as the second input. As shown in the logic NAND gate truth table of Table A, only when input 1 and input 2 are logic 1, the output will be logic 0. The measured data is shown in Table B. The single transistor dual input gate device structure can effectively realize the NAND logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage V DS =0.8V and source voltage VSS=0V.

[0083] like Figure 3BAs shown, in the single transistor dual input gate AND device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor dual input AND gate device structure is obtained through experimental measurement. The experiment shows that the AND logic gate can be successfully realized by using a single transistor dual input gate device structure. By introducing an additional logic gate as the second input. As shown in the logic AND gate truth table of Table A, only if input 1 and input 2 are logic 1, the output will be logic 1. The measured data is shown in Table B. The single transistor dual input gate device structure can effectively realize the AND logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage VDS = 6V and the source voltage VSS = 0V.

[0084] like Figure 3C As shown, in the single transistor dual input gate OR device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor dual input OR gate device structure is obtained through experimental measurement. The experiment shows that the OR logic gate can be successfully realized by using a single transistor dual input gate device structure. By introducing an additional logic gate as the second input. As shown in the logic OR gate truth table of Table A, as long as input 1 or input 2 is logic 0, the output will be logic 0. The measured data is shown in Table B. The single transistor dual input gate device structure can effectively realize the OR logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage VDS = 6V and the source voltage VSS = 0V.

[0085] like Figure 4 As shown in the single transistor NOT gate device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor NOT gate device structure is obtained through experimental measurement. The experiment shows that the single transistor device structure can successfully implement the NOT logic gate. As shown in the logic NOT gate truth table in A, the input and output logic are opposite. The measured data is shown in B in the figure. The single transistor device structure can effectively implement the NOT logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage V DS ≤1V and source voltage VSS=0V.

[0086] like Figure 5 The figure shows the structure of a single transistor made of ferroelectric material with a channel electrode added, which can realize logic gates with the same input voltage.

[0087] like Figure 6 The figure shows the storage mechanism of a single transistor made of ferroelectric material with a channel electrode added; Fig.10 Shown is a memory array circuit of a single transistor made of ferroelectric material with a channel electrode added.

[0088] like Figure 7aDue to the addition of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, etc., the transistor can have two states of storing 0 and storing 1. Then the logical states 0 and 1 given when the transistor stores 0 are different from the logical states 0 and 1 when the transistor stores 1, so polymorphic storage can be achieved.

[0089] like Figure 7b Due to the addition of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, etc., the transistor can have two new storage states of 0 and 1 after adding a channel electrode to introduce the junction capacitance of the channel and the channel electrode and having a charge storage effect. Therefore, the logic states 0 and 1 given by the new storage 0 of the transistor and the logic states 0 and 1 when the transistor stores 1 are different, and are also different from the states when the storage is not regulated by the channel electrode before, so multi-state storage can be achieved. By regulating the storage state of the transistor through the channel electrode, more multi-state storage can be achieved.

[0090] By adding ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, and organically combining channel electrodes to control the storage state of the transistor, more states of storage can be achieved than with devices that only have ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, and storage effect materials without channel electrodes, or only have channel electrodes without ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, and storage effect materials.

[0091] like Figure 8 The figure shows a schematic diagram of the structure of a single transistor dual-input gate device. A logic gate can be implemented based on the ferroelectric single transistor dual-input gate device, which is described in detail below.

[0092] Implement logic NAND gate and logic NOR gate; no voltage is applied to the channel electrode Control Gate, and the dual input terminal V is set in_1 、V in_2 Input voltage, output V out It can realize the logic NAND gate. After the voltage is applied to the channel electrode ControlGate, the dual input terminal V in_1 、V in_2 With the same input voltage, after adding the channel electrode CG and changing V ds Voltage, the regulation state becomes multi-state, the output terminal V can be regulated out Can implement a logical NOR gate.

[0093] Realize the logic AND gate (AND) and logic OR gate (OR); when no voltage is applied to the channel electrode Control Gate, set the input voltage of the dual input terminals Vin_1 and Vin_2, and the output terminal Vout can realize the logic AND gate (AND). After the voltage is applied to the channel electrode Control Gate, set the dual input terminals Vin_1 and Vin_2 to the same input voltage, add the channel electrode CG, and change the Vds voltage, the control state becomes multi-state, and the adjustable output terminal Vout can realize the logic OR gate (OR).

[0094] Realize logical exclusive OR gate (XOR) and logical exclusive OR gate (XNOR); when no voltage is applied to the channel electrode Control Gate, set the input voltage of the dual input terminals Vin_1 and Vin_2, and the output terminal Vout can realize the logical exclusive OR gate (XOR). After the voltage is applied to the channel electrode Control Gate, set the dual input terminals Vin_1 and Vin_2 to the same input voltage, add the channel electrode CG, and change the Vds voltage, the control state becomes multi-state, and the adjustable output terminal Vout can realize the logical exclusive OR gate (XNOR).

[0095] like Fig. 9 The figure shows a schematic diagram of a new structure of a triode with a channel electrode added. The above is just a typical process flow for the preparation of a channel electrode transistor. The new structure can be implemented using existing process lines or adjusted based on existing process steps. The control area material can be a semiconductor material, a conductor material, or a combination of several materials. The actual preparation process may vary depending on factors such as the manufacturer, device size, and process technology.

[0096] The drain is connected to the second bit line; the target word line control terminal includes at least one of the first word line and the second word line; the target word line control terminal is used to turn on the transistor; the input gate is connected to at least one of the word lines in a common line, or the multiple gates are connected to the multiple word lines; the channel electrode and the first bit line are connected in a common line; the target word line control terminal is used to achieve the same or different output current control, charge storage, and channel control area channel electrode output voltage extraction of the transistor.

[0097] Fig.10 A schematic diagram of a memory cell in a memory array performing a write operation is shown.

[0098] The memory device includes a word line driver module, a bit line driver module, and a memory array. The word line driver module is connected to the gate of the memory transistor 10 via a word line WL, the bit line driver module is connected to the channel electrode of the memory transistor 10 via a bit line BL1, and is connected to the drain of the memory transistor 10 via a bit line BL2.

[0099] In a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 50V, and the drain voltage Vds is 0.05 to 50V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 25V, and the drain voltage Vds is 0.05 to 25V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 15V, and the drain voltage Vds is 0.05 to 15V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 10V, and the drain voltage Vds is 0.05 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 5V, and the drain voltage Vds is 0.05 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 2.5V, and the drain voltage Vds is 0.05 to 2.5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.8V, and the drain voltage Vds is 0.05 to 2V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.5V, and the drain voltage Vds is 0.05 to 1.5V.

[0100] Further, in a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 50V, the drain voltage Vds is 0.05 to 50V, and the control region voltage Vc is -50 to 50V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 25V, the drain voltage Vds is 0.05 to 25V, and the control region voltage Vc is -20 to 20V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 15V, the drain voltage Vds is 0.05 to 15V, and the control region voltage Vc is -10 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 10V, the drain voltage Vds is 0.05 to 10V, and the control region voltage Vc is -10 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 5V, the drain voltage Vds is 0.05 to 5V, and the control region voltage Vc is -5 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 2.5V, the drain voltage Vds is 0.05 to 2.5V, and the control region voltage Vc is -5 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.8 V, the drain voltage Vds is 0.05 to 2 V, and the control region voltage Vc is -2 to 2 V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.5 V, the drain voltage Vds is 0.05 to 1.5 V, and the control region voltage Vc is -2 to 2 V.

[0101] Furthermore, the write operation includes, for example, data erasure and data programming. In data erasure, the control region voltage Vc of the storage transistor 10 is, for example, 1.5V, and the junction capacitance of the storage transistor 10 is discharged to release the charge. In data programming, the control region voltage Vc of the storage transistor 10 is, for example, -1.5V, so that the voltage difference of the gate voltage Vgs relative to the control region voltage Vc exceeds a predetermined value, and the junction capacitance of the storage transistor 10 is charged to store the charge. The write operation can change the storage state of the storage transistor 10, for example, the erase state of the storage transistor 10 is a high resistance state, which is used to represent the digital value 0, and the write state is a low resistance state, which is used to represent the digital value 1.

[0102] In the read operation, a gate voltage Vgs is provided via the word line WL, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. The channel electrode of the storage transistor 10 is in a suspended state due to the disconnection of the bit line BL1. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in the read operation, the gate voltage Vgs of the storage transistor 10 is 1.2V, and the drain voltage Vds is 2V.

[0103] Further, the read operation includes detecting the drain current Ids of the storage transistor 10. In the write operation of the storage transistor 10, the storage state of the storage transistor 10 is related to the resistance state. Even if the same bias conditions, that is, the same gate voltage, drain voltage and source voltage are used, the drain current of the storage transistor in different storage states is different.

[0104] Therefore, by comparing the drain current Ids with the current reference Iref, the storage state of the storage transistor 10 can be determined according to the size of the drain current Ids. For example, when the drain current of the storage transistor 10 is greater than the current reference Iref, the digital value stored in the storage transistor 10 is determined to be 1, and when the drain current of the storage transistor 10 is less than or equal to the current reference Iref, the digital value stored in the storage transistor 10 is determined to be 0. There can be multiple current references Iref, thereby realizing multi-state storage.

[0105] Therefore, the channel electrode output voltage V CG Compared with the voltage reference Vref, the channel electrode output voltage V CG The size of can determine the storage state of the transistor 10. For example, when the channel electrode output voltage of the transistor 10 is greater than the voltage reference Vref, it is determined that the digital value output by the transistor 10 is 1. CG When the voltage Vref is less than or equal to the voltage reference Vref, the digital value of the logic output of the transistor 10 is determined to be 0. There may also be multiple voltage references Vref to implement multi-state logic.

[0106] The semiconductor device body of the inversion mode resistive field effect transistor of the above-mentioned channel electrode can adopt a transistor structure, and specifically, the channel electrode can be set by a conductive electrode layer, a resistive memory layer stack structure or a common transistor structure, a FINFET (fin field effect transistor) structure, a FLASH (flash memory) structure or a GAA structure, while the source region and the drain region can adopt an n / p type ion implantation structure or a NiGe alloy structure.

[0107] A semiconductor device provided by the present invention can simultaneously perform the functions of storing information and switching in a formed storage array, and realizes the integration of storage function and switch control function in one transistor.

Claims

1. A logic gate transistor, characterized in that: include: a gate stack and at least one channel control region in the semiconductor layer; Wherein, the gate stack includes a gate electrode and a gate dielectric, the gate electrode controls the semiconductor layer, and the gate dielectric is sandwiched between the gate electrode and the semiconductor layer; One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides are used as insulating layer addition layers, insulating layer materials, insulating layer addition materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials to realize logic polymorphism and storage polymorphism; A channel electrode is provided in the channel control region; The semiconductor substrate and the doped region serve as a source region and a drain region of the logic gate transistor respectively.

2. The logic gate transistor according to claim 1, characterized in that: The at least one channel control region includes a single channel control region at least partially proximate to the gate stack.

3. The logic gate transistor according to claim 1, characterized in that: The at least one channel control region is composed of any layer selected from a conductor, a semiconductor, or a stack of a conductor and a semiconductor.

4. The logic gate transistor according to claim 3, characterized in that: A channel electrode is arranged in the channel control region, and the channel electrode is separated from the source electrode and the drain electrode; the at least one channel control region is composed of any stack selected from a conductor, a semiconductor, or a conductor and a semiconductor.

5. The logic gate transistor according to claim 3, characterized in that: The at least one channel control region is composed of a single layer or a stack of any ferroelectric material, or a stack of any ferroelectric material and a conductor, and the ferroelectric material serves as a gate dielectric between the conductor and the semiconductor layer.

6. The logic gate transistor according to claim 1, characterized in that: The channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

7. A new structure logic gate, characterized in that: One of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate is constructed by using a plurality of logic gate transistors as described in any one of claims 1 to 6.

8. An array of logic gates of a new structure, characterized in that: The array unit comprises a structure as claimed in any one of claims 1 to 7, comprising: The drain is connected to the second bit line; the target word line control terminal includes at least one of the first word line and the second word line; the target word line control terminal is used to turn on the transistor; the input gate is connected to at least one of the word lines in a common line, or the multiple gates are connected to the multiple word lines; the channel electrode and the first bit line are connected in a common line; the target word line control terminal is used to achieve the same or different output current control, charge storage, and channel control area channel electrode output voltage extraction of the transistor.

9. A data operation method of a new structure logic gate, comprising: In a write operation, a gate voltage is applied via a selected word line among a plurality of word lines, and a first bit line and a second bit line are connected to a control region electrode and a drain, respectively; and applying a drain voltage via a selected second bit line among a plurality of second bit lines to turn on a selected logic gate transistor, and extracting a control region voltage to the selected logic gate transistor via a selected first bit line among a plurality of first bit lines to extract a logic state of the selected logic gate transistor; as well as In a read operation, a gate voltage is applied via a selected word line among multiple word lines, and a drain voltage is applied via a selected second bit line among multiple second bit lines to put a selected logic gate transistor into an on state, and, in a case where the multiple first bit lines are disconnected, the drain current of the selected logic transistor is detected via a selected second bit line among the multiple second bit lines to obtain a logic state of the selected logic gate transistor, and, in a case where the multiple first bit lines are connected, a control region voltage of the extraction logic transistor is detected via a selected second bit line among the multiple second bit lines to obtain a logic state of the selected logic gate transistor.

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