A ferroelectric field-effect transistor based on strained silicon technology and its fabrication method

Abstract

This invention discloses a ferroelectric field-effect transistor (FeFET) based on strained silicon technology and its fabrication method. The ferroelectric field-effect transistor includes: a Si substrate of a first doping type; a drain and a source region of a second doping type, located at both ends of the Si substrate, with their upper surfaces flush with the upper surface of the Si substrate; a SiO2 insulating layer located on the Si substrate and in contact with the drain and source regions; an HZO ferroelectric dielectric layer located on the SiO2 insulating layer; a gate electrode located on the HZO ferroelectric dielectric layer; a source electrode and a drain electrode located on a portion of the drain region and a portion of the source region, respectively; a SiN layer located on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode, and the drain electrode. This invention can further improve the ferroelectric characteristics and storage capacity of the FeFET.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a ferroelectric field-effect transistor based on strained silicon technology and its fabrication method. Background Technology

[0002] Currently, the development of microelectronics is at a critical juncture of theoretical and technological transformation. It is no longer simply pursuing the reduction of feature size, but rather focusing on overcoming power consumption and improving computing power, developing new materials, devices, processes, architectures, and packaging technologies, and promoting the continuous innovation and development of information technology.

[0003] Semiconductor memories are currently the most mainstream data storage and exchange carriers, and are core components ensuring the normal operation of systems. Among next-generation memories, non-volatile ferroelectric memories fabricated using integrated circuit processing technology, utilizing the dielectric properties and ferroelectric switching effect of ferroelectric thin films, hold significant application potential. Hafnium dioxide (HfO2)-based ferroelectric materials retain their ferroelectric properties even at very thin thicknesses (around 10 nm), overcoming the size miniaturization challenges faced by traditional ferroelectric materials. They offer numerous advantages in the field of ferroelectric memory, but still suffer from the same problems as traditional ferroelectric materials, such as wake-up effects, poor durability, fatigue effects, and imprinting effects. To address these issues and develop high-performance HfO2-based ferroelectric memories, significant breakthroughs in materials and processes are urgently needed. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a ferroelectric field-effect transistor based on strained silicon technology and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, embodiments of the present invention provide a ferroelectric field-effect transistor based on strained silicon technology, the ferroelectric field-effect transistor comprising:

[0006] First type of doped Si substrate;

[0007] The drain and source regions of the second doping type are located inside both ends of the Si substrate, and their upper surfaces are flush with the upper surface of the Si substrate.

[0008] A SiO2 insulating layer is located on the Si substrate and is in contact with the drain region and the source region;

[0009] The HZO ferroelectric dielectric layer is located on the SiO2 insulating layer;

[0010] The gate electrode is located on the HZO ferroelectric dielectric layer;

[0011] The source electrode and the drain electrode are located on a portion of the drain region and a portion of the source region, respectively.

[0012] The SiN layer is located on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the drain electrode, and the source electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode. The SiN layer possesses intrinsic tensile stress and undergoes horizontal compression under the influence of chemical bonds. Through the contact between the SiN layer and the source and drain regions, the compressive force generated by this compression, under the principle of lattice adaptation, will cause the source and drain regions to contract, resulting in the channel and the ferroelectric layer being stretched and generating tensile stress.

[0013] In one embodiment of the present invention, when the first doping type is P-type, the second doping type is N-type.

[0014] In one embodiment of the present invention, the thickness of the SiO2 insulating layer is 1 nm to 3 nm.

[0015] In one embodiment of the present invention, the HZO ferroelectric dielectric layer is composed of alternating HfO2 thin films and ZrO2 thin films; the thickness of the HZO ferroelectric dielectric layer is 10 nm to 12 nm.

[0016] In one embodiment of the present invention, the thickness of the SiN layer is 100nm to 200nm.

[0017] Secondly, embodiments of the present invention provide a method for fabricating a ferroelectric field-effect transistor based on strained silicon technology, the method comprising:

[0018] Select a Si substrate of the first doping type;

[0019] A first type of doped ion implantation is performed at both ends of the Si substrate to form a second type of doped source region and a second type of doped source region and drain region;

[0020] A SiO2 insulating layer is grown on a Si substrate excluding the source region and the drain region; wherein the SiO2 insulating layer is in contact with the drain region and the source region;

[0021] An HZO ferroelectric layer is deposited on the SiO2 insulating layer;

[0022] A gate electrode is deposited on the HZO ferroelectric dielectric layer;

[0023] A source electrode and a drain electrode are deposited on a portion of the source region and a portion of the drain region, respectively;

[0024] SiN layers are grown on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, above the source and drain electrodes, and on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode. The SiN layer possesses intrinsic tensile stress and undergoes horizontal compression under the influence of chemical bonds. Through the contact between the SiN layer and the source and drain regions, the compressive force generated by this compression, under the principle of lattice adaptation, causes the source and drain regions to contract, resulting in the channel and the HZO ferroelectric layer being stretched and generating tensile stress.

[0025] In one embodiment of the present invention, when the first doping type is P-type, the second doping type is N-type.

[0026] In one embodiment of the present invention, a SiO2 insulating layer is grown on a Si substrate excluding the source region and the drain region, comprising:

[0027] Using a dry oxygen process, a SiO2 insulating layer with a thickness of 1 nm to 3 nm is grown on a Si substrate excluding the source region and the drain region.

[0028] In one embodiment of the present invention, an HZO ferroelectric dielectric layer is deposited on the SiO2 insulating layer, comprising:

[0029] An HZO ferroelectric dielectric layer with a thickness of 10 nm to 12 nm was deposited on the SiO2 insulating layer using atomic layer deposition (ALD). The specific process included: the temperature range inside the ALD equipment was 280℃ to 300℃; TDMAHf and TDMAZr were used as precursors for Hf and Zr, respectively; and water vapor was introduced as an oxygen source. An HZO film was obtained by alternately depositing HfO2 and ZrO2 films, and the thickness of the HZO film was controlled to reach 10 nm to 12 nm by controlling the number of alternating deposition cycles of HfO2 and ZrO2 films, thus forming the HZO ferroelectric dielectric layer.

[0030] In one embodiment of the present invention, a SiN layer is grown on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode, comprising:

[0031] A SiN layer with a thickness of 100 nm to 200 nm is grown on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode using plasma-enhanced chemical vapor deposition (PECVD). The specific process includes: a PECVD equipment with a temperature range of 200℃ to 500℃, a pressure range of 400 mTorr to 1700 mTorr, a high-frequency power source with a frequency of 13.5 MHz, a power variation range of 20 W to 300 W, and a SiH4 to NH3 gas flow rate ratio of 0.2 to 2.0.

[0032] The beneficial effects of this invention are:

[0033] The ferroelectric field-effect transistor based on strained silicon technology proposed in this invention is a novel structure of ferroelectric field-effect transistor. It innovatively introduces uniaxial tensile stress by covering the source region, drain region and gate electrode with SiN layer, and finally achieves better FeFET ferroelectric characteristics and better storage capacity than ordinary ferroelectric field-effect transistors, opening up a new technical path for further improving the performance of ferroelectric field-effect transistors.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a ferroelectric field-effect transistor based on strained silicon technology provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic flowchart of a method for fabricating a ferroelectric field-effect transistor based on strained silicon technology according to an embodiment of the present invention;

[0037] Figures 3a to 3g This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the corresponding structure during the preparation process.

[0038] Explanation of reference numerals in the attached figures:

[0039] 1-Si substrate of the first doping type; 2-Drain region of the second doping type; 3-Source region of the second doping type; 4-SiO2 insulating layer; 5-HZO ferroelectric dielectric layer; 6-Gate electrode; 7-SiN layer; 8-Source electrode; 9-Drain electrode. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0041] Compared to traditional MOSFETs, FeFETs simply use a ferroelectric thin film material instead of SiO2 as the gate dielectric. Essentially, FeFETs utilize the polarization state of ferroelectric transistors to regulate the channel conduction state, thereby switching between logic 0 and logic 1 states. The difference in threshold voltage VTH between the ferroelectric transistors corresponding to logic 1 and 0 is called the FeFET hysteresis loop storage window. A larger hysteresis loop storage window means it's easier to distinguish between logic 1 and 0, and the stored data is less likely to be lost, thus improving the device's storage capacity.

[0042] Strained silicon (SSI) technology is an advanced fabrication process that introduces strain into silicon-based materials. By stretching or compressing the silicon material, the SSI slightly distorts its lattice, thereby altering the electronic motion characteristics of the silicon material and improving device performance. Although HfO2-based FeFETs have many advantages in the memory field, they still suffer from problems such as wake-up effects, poor durability, fatigue effects, and imprinting effects. To address these issues, high-performance HfO2-based FeFETs have been developed. Stress modulation techniques can be used to control the ferroelectric properties of HfO2-based FeFETs. Studies show that the magnitude of tensile stress is positively correlated with the remanent polarization of the ferroelectric thin film. Introducing tensile stress into the ferroelectric thin film increases its hysteresis loop storage window, improving the storage capacity of the FeFET and effectively enhancing its various performance characteristics. While existing stress modulation techniques can be achieved by changing electrode and substrate materials, stress modulation technology for FeFETs using strained silicon is still in its early stages.

[0043] Based on the above research, this invention proposes to introduce strained silicon technology into the fabrication process of HfO2-based FeFETs, which can further improve the ferroelectric properties and storage capacity of FeFETs. Specifically:

[0044] Firstly, please see Figure 1 This invention provides a ferroelectric field-effect transistor based on strained silicon technology, the ferroelectric field-effect transistor comprising:

[0045] Si substrate 1 of the first doping type;

[0046] The drain region 2 and source region 3 of the second doping type are located inside both ends of the Si substrate 1, and their upper surfaces are flush with the upper surface of the Si substrate 1.

[0047] The SiO2 insulating layer 4 is located on the Si substrate 1 and is in contact with the drain region 2 and the source region 3;

[0048] HZO ferroelectric layer 5 is located on SiO2 insulating layer 4;

[0049] Gate electrode 6 is located on HZO ferroelectric dielectric layer 5;

[0050] Source electrode 8 and drain electrode 9 are located on a portion of the drain region and a portion of the source region, respectively.

[0051] SiN layer 7 is located on the remaining portion of drain region 2, the remaining portion of source region 3, gate electrode 6, source electrode 8, drain electrode 9, and on the sidewalls of SiO2 insulating layer 4, HZO ferroelectric dielectric layer 5, gate electrode 6, source electrode 8, and drain electrode 9. SiN layer 7 has intrinsic tensile stress and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between SiN layer 7 and source region 3 and drain region 2, under the action of lattice adaptation principle, the compressive force generated by this compression will drive source region 3 and drain region 2 to contract, so that the channel and ferroelectric layer are stretched and tensile stress is generated.

[0052] In this embodiment of the invention, when the first doping type is P-type, the second doping type is N-type. At this time, the substrate is a P-type Si substrate 1, the drain region 2 is an N-type doped drain region 2, and the source region 3 is an N-type doped source region 3.

[0053] In this embodiment of the invention, the thickness of the SiO2 insulating layer 4 is 1 nm to 3 nm. SiO2 is chosen as the material for the insulating layer because SiO2 and Si have good interfacial properties.

[0054] In this embodiment of the invention, the HZO ferroelectric dielectric layer 5 is composed of alternating HfO2 thin films and ZrO2 thin films; the number of cycles of the alternating HfO2 thin films and ZrO2 thin films is determined by the thickness of the HZO ferroelectric dielectric layer 5, and preferably the thickness of the HZO ferroelectric dielectric layer 5 is 10nm to 12nm.

[0055] In this embodiment of the invention, the gate electrode 6 is made of TaN and has a thickness of 90 nm to 100 nm. Here, the SiO2 insulating layer 4, the HZO ferroelectric dielectric layer 5, and the gate electrode 6 constitute a stacked gate structure.

[0056] In this embodiment of the invention, the thickness of the SiN layer 7 is 100nm to 200nm.

[0057] In this embodiment of the invention, the remanent polarization intensity of the HfO2 thin film in the HZO ferroelectric dielectric layer 5 increases with the increase of uniaxial tensile stress. Introducing uniaxial tensile stress into the HfO2 thin film causes the FeFET hysteresis loop storage window to increase with the increase of uniaxial tensile stress, which is beneficial to the existence of ferroelectricity of the HfO2 thin film and improves the storage capacity of the FeFET. The stress in the HfO2 thin film originates from various factors, such as: lattice mismatch between Si substrate 1 and epitaxial film, the difference in thermal expansion coefficients between epitaxial film and Si substrate 1, and phase transition. In strained silicon process technology, uniaxial tensile stress can be introduced by covering the device surface with SiN layer 7. The basic principle is: based on the lattice mismatch between materials, when the device covered with SiN layer 7 cools from the deposition temperature to the measurement temperature, both SiN layer 7 and Si substrate 1 will shrink with the cooling, but the degree of shrinkage of the two is different.

[0058] A SiN layer 7 with uniaxial tensile stress is covered on the source region 3, drain region 2, and gate electrode 6 of the FeFET. Through contact with the source region 3 and drain region 2 in the Si substrate 1, the source region 3 and drain region 2 shrink under the action of the lattice mismatch principle, and the channel is stretched, resulting in uniaxial tensile stress inside the channel. At the same time, the Si substrate 1 material in the FeFET is in direct contact with the stacked gate material, and the HfO2 film is constrained by the Si substrate 1 material, generating internal stress, which in turn affects the ferroelectricity of the HfO2 film.

[0059] Furthermore, the presence of channel tensile stress also affects the polarization switching characteristics of ferroelectric materials. The polarization switching characteristics of ferroelectric materials influence the write / erase speed of their corresponding memory devices. When a positive write voltage is applied to the gate electrode 6, an inversion layer forms on the channel surface, creating a current path between the source region 3 and the drain region 2, corresponding to the device's write process. When a negative erase voltage is applied to the gate electrode 6, an accumulation layer forms on the channel surface, cutting off the current path between the source region 3 and the drain region 2, corresponding to the device's erase process.

[0060] In FeFETs, the ferroelectric polarized surface charge influences the semiconductor's surface potential through Coulomb coupling, thereby regulating the carrier concentration in the FeFET channel. For example, in this embodiment of the invention, when the FeFET is an N-type FeFET, electrons provide carriers for the conductive channel in the FeFET inversion mechanism. Mobility is a physical quantity in solid-state physics used to describe the speed at which electrons / holes move within a semiconductor under the influence of an electric field. The introduction of channel tensile stress increases electron mobility, thereby improving the write / erase speed of the FeFET.

[0061] In summary, the ferroelectric field-effect transistor based on strained silicon technology proposed in this embodiment of the invention is a novel structure for ferroelectric field-effect transistors. It innovatively introduces uniaxial tensile stress by covering the source region 3, drain region 2, and gate electrode 6 with a SiN layer 7, ultimately achieving better FeFET ferroelectric characteristics and better storage capacity than ordinary ferroelectric field-effect transistors, thus opening up a new technical path for further improving the performance of ferroelectric field-effect transistors.

[0062] Secondly, please see Figure 2 This invention provides a method for fabricating a ferroelectric field-effect transistor based on strained silicon technology. The fabrication method includes:

[0063] S10. Select a Si substrate of the first doping type 1.

[0064] In this embodiment of the invention, a Si substrate of the first doping type is selected, such as... Figure 3a As shown, the Si substrate 1 underwent organic ultrasonic cleaning in the following order: acetone, anhydrous ethanol, and water. This was to remove organic contaminants from the surface of the Si substrate 1. Following this, it was immersed in diluted hydrofluoric acid (HF:H2O = 1:50) for one minute, and then inorganically cleaned at room temperature to remove the intrinsic oxide layer, thus avoiding any impact on subsequent processes and device performance. The first doping type can be P-type.

[0065] S20. First-type doped ion implantation is performed on both ends of the Si substrate 1 to form a second-type doped source region 3 and a drain region 2.

[0066] In this embodiment of the invention, after cleaning the Si substrate 1 with S10, a patterning process is performed on the Si substrate 1. The source and drain regions are defined through a series of operations including spin coating, baking, contact exposure, development, and fixing. Then, reactive ion etching is used to etch the source region 3 and drain region 2. Specifically, the reactive ion etching process uses chlorine-based atomic groups (Cl2 and BCl3) as etchants. Subsequently, photolithography is used to etch the source and drain regions, and self-aligned first-type doped ion implantation is performed on the source and drain regions to form the second-type doped source region 3 and drain region 2. Figure 3b As shown, the implantation energy and dose during ion implantation were 30 keV and 2 × 10⁻⁶, respectively. 15 cm -2 Finally, rapid thermal annealing is performed at 900℃ in an N2 atmosphere for 1 minute to activate the dopant implantation in source region 3 and drain region 2. Specifically, when the first doping type in S10 is P-type and the second doping type is N-type, self-aligned P+ ion implantation is performed on the source / drain region 2 to form N-type doped source region 3 and N-type doped drain region 2.

[0067] S30. A SiO2 insulating layer 4 is grown on the Si substrate 1, excluding the source region 3 and the drain region 2; wherein the SiO2 insulating layer 4 is in contact with the drain region 2 and the source region 3.

[0068] In this embodiment of the invention, the Si substrate 1, after S20 activation, is cleaned in SPM (H2SO4:H2O = 1:3) and DHF (HF:H2O = 1:50) solutions to remove photoresist and surface oxide layers. Using a dry oxide process, a SiO2 insulating layer 4 with a thickness of 1nm to 3nm is grown on the Si substrate 1, excluding the source region 3 and drain region 2. Figure 3c As shown.

[0069] S40. Deposit an HZO ferroelectric layer 5 on the SiO2 insulating layer 4.

[0070] This invention utilizes atomic layer deposition (ALD) to deposit an HZO ferroelectric layer 5 with a thickness of 10 nm to 12 nm on a SiO2 insulating layer 4. The specific process includes: an ALD equipment with a temperature range of 280°C to 300°C; using TDMAHf (tetra(dimethylamino)hafnium) and TDMAZr (tetra(dimethylamino)zirconium) as precursors for Hf (hafnium) and Zr (zirconium), respectively; and introducing water vapor (H2O) as an oxygen source. An HZO film is obtained by alternately depositing HfO2 and ZrO2 films, and the thickness of the HZO film is controlled to reach 10 nm to 12 nm by controlling the number of alternating deposition cycles of the HfO2 and ZrO2 films, thus forming the HZO ferroelectric layer 5. Figure 3d As shown in the figure. The number of cycles varies depending on the required thickness of the HZO ferroelectric dielectric layer 5. The thickness of the HfO2 film and the ZrO2 film can both be 1 nm in each alternating deposition cycle.

[0071] S50, deposit gate electrode 6 on HZO ferroelectric layer 5.

[0072] This invention utilizes magnetron sputtering deposition to deposit the gate electrode 6. Specifically, the sample is transferred to the chamber of the magnetron sputtering deposition system, and a gate electrode 6 with a thickness of 90 nm to 100 nm is deposited on the HZO ferroelectric layer 5. Figure 3e As shown, for example, the material of the gate electrode 6 can be TaN metal.

[0073] S60. Deposit source electrode 8 and drain electrode 9 on part of source region 3 and part of drain region 2, respectively.

[0074] In this embodiment of the invention, photolithography is used to define the gate pattern region, and reactive ion etching is employed to etch the gate pattern region to expose the source region 3 and the drain region 2. Subsequently, through electron beam evaporation deposition and lift-off processes, for example, 30 nm thick Ni metal is deposited on a portion of the source region 3 and a portion of the drain region 2 to form the source electrode 8 and drain electrode 9, respectively. Figure 3f As shown. Finally, the fabricated device was rapidly annealed at 550℃ in a N2 atmosphere for 30-60 seconds to form ohmic contacts in the source region 3 and the drain region 2, and to allow the HZO thin film to crystallize.

[0075] S70. A SiN layer 7 is grown on the remaining portion of the drain region 2, the remaining portion of the source region 3, the gate electrode 6, the source electrode 8, and the drain electrode 9, as well as on the sidewalls of the SiO2 insulating layer 4, the HZO ferroelectric layer 5, the gate electrode 6, the source electrode 8, and the drain electrode 9. The SiN layer 7 has intrinsic tensile stress and will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between the SiN layer 7 and the source region 3 and the drain region 2, under the action of the lattice adaptation principle, the compressive force generated by this compression will drive the source region 3 and the drain region 2 to contract, so that the channel and the HZO ferroelectric layer 5 are stretched and tensile stress is generated.

[0076] In this embodiment of the invention, a SiN layer 7 is grown on the remaining portion of the drain region 2, the remaining portion of the source region 3, the gate electrode 6, the source electrode 8, and the drain electrode 9, as well as on the sidewalls of the SiO2 insulating layer 4, the HZO ferroelectric layer 5, the gate electrode 6, the source electrode 8, and the drain electrode 9. This includes growing a SiN layer 7 with a thickness of 100 nm to 200 nm on the drain region 2, the source region 3, the gate electrode 6, the source electrode 8, and the drain electrode 9, as well as on the sidewalls of the SiO2 insulating layer 4, the HZO ferroelectric layer 5, the gate electrode 6, the source electrode 8, and the drain electrode 9 using plasma-enhanced chemical vapor deposition. Figure 3g As shown; the specific process includes: the temperature range of the PECVD equipment is 200℃~500℃, the pressure range is 400mTorr~1700mTorr, the frequency of the high-frequency power source is 13.5MHz, the power variation range of the high-frequency power source is 20W~300W, and the flow ratio of SiH4 and NH3 gases is 0.2~2.0. At this time, the deposited SiN layer 7 has intrinsic tensile stress, which will be compressed in the horizontal direction under the action of chemical bonds. Through the contact between SiN layer 7 and source region 3 and drain region 2, under the action of lattice adaptation principle, the compressive force generated by this compression will drive source region 3 and drain region 2 to contract, so that the channel and HZO ferroelectric layer 5 are stretched and tensile stress is generated.

[0077] As for the preparation method embodiment of the second aspect, since it is basically similar to the structural embodiment of the first aspect, the description is relatively simple. For relevant details, please refer to the description of the structural embodiment of the first aspect.

[0078] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0079] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0080] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A ferroelectric field-effect transistor based on strained silicon technology, characterized in that, The ferroelectric field-effect transistor includes: First type of doped Si substrate; The drain and source regions of the second doping type are located inside both ends of the Si substrate, and their upper surfaces are flush with the upper surface of the Si substrate. A SiO2 insulating layer is located on the Si substrate and is in contact with the drain region and the source region; The HZO ferroelectric dielectric layer is located on the SiO2 insulating layer; The gate electrode is located on the HZO ferroelectric dielectric layer; The source electrode and the drain electrode are located on a portion of the drain region and a portion of the source region, respectively. A SiN layer is located on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode. The SiN layer possesses intrinsic tensile stress and undergoes horizontal compression under the influence of chemical bonds. Through the contact between the SiN layer and the source and drain regions, under the principle of lattice adaptation, the compressive force generated by this compression will cause the source and drain regions to contract, resulting in the channel and the ferroelectric layer being stretched and generating tensile stress.

2. The ferroelectric field-effect transistor based on strained silicon technology according to claim 1, characterized in that, When the first doping type is P-type, the second doping type is N-type.

3. The ferroelectric field-effect transistor based on strained silicon technology according to claim 1, characterized in that, The thickness of the SiO2 insulating layer is 1 nm to 3 nm.

4. The ferroelectric field-effect transistor based on strained silicon technology according to claim 1, characterized in that, The HZO ferroelectric dielectric layer is composed of alternating HfO2 thin films and ZrO2 thin films; the thickness of the HZO ferroelectric dielectric layer is 10 nm to 12 nm.

5. The ferroelectric field-effect transistor based on strained silicon technology according to claim 1, characterized in that, The thickness of the SiN layer is 100nm to 200nm.

6. A method for fabricating a ferroelectric field-effect transistor based on strained silicon technology, characterized in that, The preparation method includes: Select a Si substrate of the first doping type; A first type of doped ion implantation is performed at both ends of the Si substrate to form a second type of doped source region and a second type of doped source region and drain region; A SiO2 insulating layer is grown on a Si substrate excluding the source region and the drain region; wherein the SiO2 insulating layer is in contact with the drain region and the source region; An HZO ferroelectric layer is deposited on the SiO2 insulating layer; A gate electrode is deposited on the HZO ferroelectric dielectric layer; A source electrode and a drain electrode are deposited on a portion of the source region and a portion of the drain region, respectively; SiN layers are grown on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode. The SiN layer possesses intrinsic tensile stress and undergoes horizontal compression under the influence of chemical bonds. Through the contact between the SiN layer and the source and drain regions, the compressive force generated by this compression, under the principle of lattice adaptation, will cause the source and drain regions to contract, resulting in the channel and the HZO ferroelectric layer being stretched and generating tensile stress.

7. The method for fabricating a ferroelectric field-effect transistor based on strained silicon technology according to claim 6, characterized in that, When the first doping type is P-type, the second doping type is N-type.

8. The method for fabricating a ferroelectric field-effect transistor based on strained silicon technology according to claim 6, characterized in that, Growing a SiO2 insulating layer on a Si substrate excluding the source and drain regions includes: Using a dry oxygen process, a SiO2 insulating layer with a thickness of 1 nm to 3 nm is grown on a Si substrate excluding the source region and the drain region.

9. The method for fabricating a ferroelectric field-effect transistor based on strained silicon technology according to claim 6, characterized in that, Depositing an HZO ferroelectric layer on the SiO2 insulating layer includes: An HZO ferroelectric dielectric layer with a thickness of 10 nm to 12 nm was deposited on the SiO2 insulating layer using atomic layer deposition (ALD). The specific process included: the temperature range inside the ALD equipment was 280℃ to 300℃; TDMAHf and TDMAZr were used as precursors for Hf and Zr, respectively; and water vapor was introduced as an oxygen source. An HZO film was obtained by alternately depositing HfO2 and ZrO2 films, and the thickness of the HZO film was controlled to reach 10 nm to 12 nm by controlling the number of alternating deposition cycles of HfO2 and ZrO2 films, thus forming the HZO ferroelectric dielectric layer.

10. The method for fabricating a ferroelectric field-effect transistor based on strained silicon technology according to claim 6, characterized in that, Growing a SiN layer on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode and the drain electrode, and on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode and the drain electrode, including: A SiN layer with a thickness of 100 nm to 200 nm is grown on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric layer, the gate electrode, the source electrode, and the drain electrode using plasma-enhanced chemical vapor deposition (PECVD). The specific process includes: a PECVD equipment with a temperature range of 200℃ to 500℃, a pressure range of 400 mTorr to 1700 mTorr, a high-frequency power source with a frequency of 13.5 MHz, a power variation range of 20 W to 300 W, and a SiH4 to NH3 gas flow rate ratio of 0.2 to 2.0.

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