SiC transverse JFET device

Abstract

The invention provides a SiC transverse JFET device, and the device comprises a substrate of a second doping type, and the substrate is grounded; an epitaxial layer of a SIC material of a first doping type formed over the substrate; the first through hole downwards penetrates through the epitaxial layer from the upper surface of the epitaxial layer, and the bottom end of the first through hole enters the substrate; the connection region of the SIC material of the second doping type is filled in the first through hole; the source electrode of the first doping type is formed in the epitaxial layer; the source electrode contact metal compound is formed on the connecting region and is electrically connected with the source electrode; wherein the source contact metal compound is electrically connected with the grounded substrate of the second doping type through the connecting region of the second doping type. The technical problem that the occupied device area is large due to the fact that the source electrode of a traditional SiC transverse JFET device is grounded is solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a SiC lateral JFET device. Background Art

[0002] SiC lateral JFET devices are semiconductor devices that are very suitable for use in the RF and power fields. First of all, as a wide bandgap semiconductor material, SiC has a higher breakdown field strength than Si, so devices with the same breakdown voltage level but a shorter drift region and smaller on-resistance can be achieved in SiC. Secondly, the current of the SiC lateral JFET device is conducted in the SiC body, rather than through the SiC-SiO2 interface like SiC MOS devices, so many problems such as low carrier mobility and poor reliability caused by defects at the interface can be avoided. In addition, SiC material has a high thermal conductivity and has a natural heat dissipation advantage in power applications.

[0003] Figure 1 The figure is a cross-sectional view of a currently disclosed SiC L-JFET device, in which the main body of the device is represented by the following numbers: substrate 101, second epitaxial layer 102, first epitaxial layer 103, drift region 104, drain injection region 105, drain 106, source 107, first source contact region 108, channel region 109, gate 110, second source contact region 111, oxide layer 206, source contact metal compound 201-1, gate contact metal compound 201-2, drain contact metal compound 201-3, gate shielding plate 202, source contact through hole 203-1, gate contact through hole 203-2, drain contact through hole 203-3, source metal layer 204-1, drain metal layer 204-3, and grounding back hole 205.

[0004] For RF application scenarios, such as communication base stations, RF power supplies, microwave heating, etc., due to the high power of the device itself, the device needs to dissipate heat on the back side. At the same time, the existing peripheral circuit architecture design requires that the source of the general RF amplifier device needs to be grounded to the back side of the chip. The device in the existing patent grounds the source through the grounding back hole 205. The process is generally to drill holes from the back side of the wafer by etching until it stops on the source metal layer 204-1, and then deposit metal in the hole. The metal will short-circuit the source metal layer 204-1, thus achieving the purpose of grounding the source of the device. However, doing so will at least have the following problems:

[0005] 1. High process complexity and cost. At present, the common thickness of silicon carbide substrate is 300-400μm. After the front process is completed, the thickness after thinning is also about 200μm. To carve deep holes on such a thick substrate, it will take a long time for the etching machine, and a large process cost will be invested. At the same time, the deep hole processing of such deep silicon carbide requires high efficiency and fast etching speed of 200μm silicon carbide deep holes in the early stage, and it is required to stop in time when etching to the front metal layer with a general thickness of 2-3μm. The etching machine is very demanding, and the uniformity within the surface is difficult to control, resulting in some holes in the wafer not being carved, and some holes have penetrated the metal layer, causing device damage.

[0006] 2. The arrangement of the active area of ​​the device is limited, and metal routing is difficult. It is difficult to achieve a large depth-to-width ratio in silicon carbide deep hole processing. For a hole with a depth of 180μm, the hole size must be at least 50μm×50μm to ensure a relatively uniform hole morphology with steep side walls. Moreover, there will be alignment problems when drilling from the back to the front. In order to ensure that the bottom of the hole can fall on a certain layer of metal on the front, the metal size must be about 20μm larger than the hole size to prevent the hole from falling into the active area outside the metal, causing device failure. This requires that at least 90μm of spacing must be left between the active areas of the device for the back hole, and the size of the active area of ​​the entire device is less than 20μm, which means that the arrangement of the active area of ​​the device will be greatly squeezed by the arrangement of the back hole, resulting in waste of active area space, reduced integration, difficulty in metal wiring and other associated problems.

[0007] Therefore, the source grounding of the traditional SiC lateral JFET device causes the device to occupy a large area, which is a technical problem that technical personnel in this field urgently need to solve.

[0008] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0009] The present application provides a SiC lateral JFET device to solve the technical problem that the source of a conventional SiC lateral JFET device is grounded, resulting in a large device area being occupied.

[0010] The present application provides a SiC lateral JFET device, comprising:

[0011] a substrate of a second doping type, the substrate being grounded;

[0012] an epitaxial layer of SIC material of a first doping type formed on the substrate;

[0013] A first through hole, penetrating the epitaxial layer from the upper surface of the epitaxial layer downwards, and a bottom end of the first through hole enters into the substrate;

[0014] A connection region of the SIC material of the second doping type is filled in the first through hole;

[0015] A source electrode of a first doping type formed in the epitaxial layer;

[0016] A source electrode contacting the metal compound is formed on the connection region and is electrically connected to the source electrode;

[0017] The source contact metal compound is electrically connected to a grounded second doping type substrate through a second doping type connection region.

[0018] Due to the adoption of the above technical solution, this application has the following technical effects:

[0019] By using the first through hole and the connection area filled in the first through hole, the area occupied by the first through hole is small, and the device area utilization rate is high. For the first through hole with a depth of 10μm, the size of the first through hole can be reduced to less than 5μm×5μm. In this way, the difficulty of arranging the first through hole is greatly reduced, leaving enough space for the active area, and at the same time reducing the difficulty of connecting the metal wiring of the front active area electrode, thereby improving the integration of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 This is a cross-sectional view of a currently disclosed SiC L-JFET device;

[0022] Figure 2 Schematic diagram of a SiC lateral JFET device of the present application;

[0023] Figure 3 A schematic diagram of completing step S1 of the preparation process of the SiC lateral JFET device of the present application;

[0024] Figure 4 A schematic diagram of completing step S2 of the preparation process of the SiC lateral JFET device of the present application;

[0025] Figure 5 A schematic diagram of completing step S3 of the preparation process of the SiC lateral JFET device of the present application;

[0026] Figure 6A schematic diagram of completing step S4 of the preparation process of the SiC lateral JFET device of the present application;

[0027] Figure 7 A schematic diagram of completing step S5 of the preparation process of the SiC lateral JFET device of the present application;

[0028] Figure 8 This is a simulation diagram of the SiC lateral JFET device of the present application;

[0029] Fig. 9 This is an Id-Vg curve diagram of the SiC lateral JFET device of the present application.

[0030] Reference numerals:

[0031] Substrate 101, second epitaxial layer 102, first epitaxial layer 103, drift region 104,

[0032] Drain injection region 105, drain 106,

[0033] Source 107, first source contact region 108, channel region 109,

[0034] Gate 110, second source contact region 111,

[0035] Connection area 112,

[0036] Oxide layer 206,

[0037] The source contacts the metal compound 201 - 1 , and the gate contacts the metal compound 201 - 2 .

[0038] Drain contact metal compound 201-3,

[0039] The gate shielding plate 202,

[0040] Source contact through hole 203-1, gate contact through hole 203-2, drain contact through hole 203-3,

[0041] Source metal layer 204 - 1 , drain metal layer 204 - 3 , and ground back hole 205 . DETAILED DESCRIPTION

[0042] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0043] Embodiment 1

[0044] like Figure 2 As shown, the SiC lateral JFET device of the present application includes:

[0045] A substrate 101 of a second doping type, wherein the substrate 101 is grounded;

[0046] An epitaxial layer of a first doping type SIC material is formed on the substrate 101;

[0047] A first through hole, penetrating the epitaxial layer from the upper surface of the epitaxial layer downwards, and a bottom end of the first through hole enters into the substrate 101;

[0048] A connection region 112 of a second doping type SIC material is filled in the first through hole;

[0049] A source electrode 107 of a first doping type, formed in the epitaxial layer;

[0050] A source contact metal compound 201 - 1 is formed on the connection region 112 and is electrically connected to the source 107 ;

[0051] The source contact metal compound 201 - 1 is electrically connected to the grounded second doping type substrate 101 through the second doping type connection region 112 .

[0052] In the SiC lateral JFET device of the present application, the epitaxial layer of the first doping type SIC material formed on the substrate 101 is a necessary structure of the SiC lateral JFET device. The first through hole penetrates the epitaxial layer from the upper surface of the epitaxial layer downward, and the bottom end of the first through hole enters into the substrate 101. That is, the starting point of the etching to form the first through hole is the upper surface of the epitaxial layer, and the end point is to enter into the substrate 101. The etching to form the first through hole only needs to penetrate the thickness of the epitaxial layer of the SIC material and enter deeper into the substrate 101. The thickness of the epitaxial layer is generally only a few microns, so the depth of the etching to form the first through hole is very small.

[0053] The connection region 112 of the second doping type SIC material is formed by filling the first through hole with the second doping type polycrystalline SIC material, and the lower end of the connection region 112 enters the substrate 101. In this way, the grounded second doping type substrate 10 is connected to the second doping type connection region 112.

[0054] The depth of the first through hole is small, and correspondingly, the diameter of the first through hole is also small, so that the area occupied by the first through hole is also small.

[0055] The second doping type substrate uses an N-type low-resistance substrate 101 , that is, the majority carriers of the substrate 101 are electrons and the substrate 101 has more electrons.

[0056] The N-type substrate 101 and the N-type second doping type connection area 112 are both N-type, and most carriers are electrons. In this way, by controlling the doping concentration of the substrate 101 and the connection area 112, the connection between the N-type substrate 101 and the N-type connection area 112 can have better electrical connection and lower resistance.

[0057] Since the substrate 101 is grounded, the zero potential of the grounded substrate 101 has been connected to the source contact metal compound 201-1 through the N-type substrate 101, the N-type connection area 112 and the source contact metal compound 201-1, that is, the zero potential has been connected to the inside of the SiC lateral JFET device of the present application and in the middle position in the thickness direction, which provides conditions for the SiC lateral JFET device of the present application to be grounded from the front.

[0058] In addition, the source contact metal compound 201-1 is electrically connected to the source 107 (the two can be directly connected to achieve electrical connection, or the source 107 can be electrically connected to the source 107). Figure 2 As shown, electrical connection is achieved through the first source contact region 108 , that is, the source 107 is also connected to zero potential.

[0059] In this way, the structure of the SiC lateral JFET device of the present application realizes the grounding of the source from the front side, and it is no longer necessary to penetrate the entire thickness of the device, and further, it is no longer necessary to adopt the TSV through-hole process.

[0060] The advantages of the SiC lateral JFET device of this application are:

[0061] (1) Simple process: The TSV through hole is eliminated and the TSV process is no longer needed. Instead, the first through hole and the connection area 112 filled in the first through hole and the low-resistance substrate need to be used. There is no need to etch deep holes, and only the epitaxial layer of the first doping type SiC material needs to be etched, which generally does not exceed 10μm. Therefore, there is no need to set a separate Stop layer. The etching process of the first through hole is simple, the process steps are simple, and the process difficulty is low.

[0062] (2) Small area of ​​the first through hole: The first through hole and the connection area 112 filled in the first through hole are used, and the area occupied by the first through hole is small, and the device area utilization rate is high. For the first through hole with a depth of 10μm, the size of the first through hole can be reduced to less than 5μm×5μm. In this way, the difficulty of arranging the first through hole is greatly reduced, leaving enough space for the active area, and at the same time reducing the difficulty of connecting the metal wiring of the front active area electrode, thereby improving the integration of the device.

[0063] That is, the hole depth and hole diameter of the first through hole are both small, which is convenient for preparation.

[0064] (3) Low material cost: The SiC lateral JFET device of the present application adopts low-resistance substrate on a large scale, which is lower in cost than high-resistance substrate.

[0065] In implementation, the substrate 101 is a single crystal low-resistance substrate 101;

[0066] The connection region 112 is a connection region of a polycrystalline SIC material. The connection between the bottom end of the connection region 112 and the substrate 101 satisfies the following conditions to achieve good source grounding:

[0067] The doping concentration of the substrate 101 is 1×10 20 cm -3 Above; the doping concentration of the connection region 112 is greater than or equal to the doping concentration of the substrate.

[0068] The substrate 101 needs to be a low-resistance substrate, and the lower the resistivity, the better, that is, the higher the concentration of the second doping type, the better.

[0069] The substrate and the epitaxial layer are both single crystal, and only the connection region 112 is polycrystalline.

[0070] The connection area 112 is polycrystalline. The principle is that the properties of polycrystalline SiC material and single crystal SiC material are different as follows:

[0071] 1. It is very difficult to grow single crystal SiC materials epitaxially. Epitaxial growth is usually carried out very slowly on a specific crystal orientation plane with atomic-level flatness. There is basically no technology for growing single crystals in large quantities in holes.

[0072] Polycrystalline SiC materials are different. The growth of polycrystalline SiC materials has basically no requirements on the surface shape and crystal orientation of the substrate, and does not even require the substrate to be of the same material. It grows fast, the technology is mature and large-scale, and is widely used in process steps such as hole filling.

[0073] 2. The upper limit of the second doping type doping of polycrystalline SiC materials is higher than that of single-crystal SiC materials. Generally, the doping concentration of polycrystalline SiC materials can easily reach 1×10 20 cm -3 The concentration of the second doping type is of the order of magnitude, or even higher;

[0074] The doping concentration of single-crystal SiC materials is generally only up to 1×10 19 cm -3 .

[0075] Higher doping concentration means it is easier to achieve ohmic contact.

[0076] The connection region 112 and the substrate 101 are both made of SiC material, which is the same material. As long as the doping concentrations of the connection region 112 and the substrate 101 are consistent, the energy level structures of the two are basically consistent, and electrons will no longer encounter a potential barrier when crossing the interface between the two.

[0077] The connection region 112 is sufficiently dense to form a good ohmic contact with the source contact metal compound 201 - 1 thereon, thereby achieving good grounding of the source.

[0078] In implementation, such as Figure 2 As shown, the depth of the connection region 112 entering the substrate 101 ranges from greater than or equal to 0.1 μm to less than or equal to 100 μm.

[0079] This can ensure that the connection region 112 and the substrate 101 have a sufficient contact area.

[0080] In implementation, such as Figure 2 As shown, the epitaxial layer includes:

[0081] A first epitaxial layer of a first doping type, formed on the substrate 101;

[0082] A second epitaxial layer 103 of a first doping type is formed on the first epitaxial layer 102; the source 107 is formed in the second epitaxial layer 103; wherein the doping concentration of the first epitaxial layer 102 is greater than the doping concentration of the second epitaxial layer 103;

[0083] A first source contact region 108 of a first doping type and a second source contact region 111 of a second doping type are arranged side by side on the source 107 , and the source contact metal compound 201 - 1 is located on the first source contact region 108 and the second source contact region 111 ;

[0084] A source contact through hole 203 - 1 formed on the source contact metal compound 201 - 1 ;

[0085] The source metal layer 204 - 1 is formed on the source contact through hole 203 - 1 .

[0086] The grounded second doping type substrate 101, the second doping type connection area 112, the source contact metal compound 201-1, and the source 107 are connected, and the source 107 is grounded. The source contact metal compound 201-1, the source contact through hole 203-1, and the source metal layer 204-1 are connected, so that the source metal layer 204-1 is also grounded. In the case where the source 107 is grounded through the second doping type connection area 112 and the source contact metal compound 201-1, the source contact through hole 203-1 and the source metal layer 204-1 still need to be provided. The grounded source metal layer 204-1 plays a shielding role and a routing role.

[0087] In implementation, such as Figure 2 As shown, the SiC lateral JFET device of the present application also includes:

[0088] A drift region 104 of a second doping type is formed in the first epitaxial layer 102;

[0089] A channel region 109 , located above the source 107 ;

[0090] A gate 110 located on the channel region 109;

[0091] The channel region 109 and the drift region 104 are respectively the channel region 109 and the drift region 104 of independent structures.

[0092] In implementation, such as Figure 2 As shown, there is a first gap between the source 107 and the drift region 104;

[0093] A second gap is provided between the gate 110 and the second source contact region 111 , and between the gate 110 and the drift region 104 ;

[0094] And the PN junction formed by the drift region 104 and the first epitaxial layer 102 , the PN junction formed by the drift region 104 and the source 107 , and the PN junction formed by the drift region 104 and the gate 110 are broken down in the order of arrangement.

[0095] If the PN junction formed by the drift region 104 and the gate 110 is broken down, the gate will be burned out. Therefore, it is necessary to avoid breakdown as much as possible, that is, the PN junction formed by the drift region 104 and the gate 110 is the last to be broken down among the three PN junctions.

[0096] After the drift region 104, the PN junction formed by the drift region 104 and the second epitaxial layer 103, and the PN junction formed by the drift region 104 and the source 107 are broken down, the generated avalanche current will flow out from the drain end under the action of the electric field. The drain end is directly grounded through the substrate, avoiding the occurrence of gate burning and drain burning. The drain end conducts current, making the device more reliable and robust.

[0097] As an example, when the breakdown voltage of the SiC lateral JFET device of the present application is 150 V, the PN junction formed by the drift region 104 and the second epitaxial layer 103, the PN junction formed by the drift region 104 and the source 107, and the PN junction formed by the drift region 104 and the gate 110 have breakdown voltages of 150-200 V, 50-100 V, and 20-30 V, respectively, according to the current simulation results. By adjusting the width of the first gap and the second gap, the breakdown of the latter two PN junctions can be effectively postponed, and the first PN junction can be broken down first.

[0098] If there is a greater demand in the industry, the breakdown voltage of the SiC lateral JFET device of the present application can be adjusted, specifically by adjusting the size of the drift region. The breakdown voltage includes but is not limited to 200V, 500V or 1000V.

[0099] In implementation, such as Figure 2 As shown, the SiC lateral JFET device of the present application also includes:

[0100] Oxide layer 206;

[0101] The drain 106 is located in the drift region 104 and is spaced apart from the gate 110;

[0102] a drain implantation region 105 located below the drain 106;

[0103] A drain contact metal compound 201 - 3 located in the oxide layer and above the drain 106 ;

[0104] a drain contact through hole 203 - 3 located in the oxide layer and above the drain contact metal compound 201 - 3 ;

[0105] A drain metal layer 204 - 3 is located within the oxide layer and above the drain contact via 203 - 3 .

[0106] In implementation, such as Figure 2 As shown, the SiC lateral JFET device also includes:

[0107] A gate contact metal compound 201 - 2 located in the oxide layer and above the gate 110 ;

[0108] A gate contact via 203 - 2 is located in the oxide layer and above the gate contact metal compound 201 - 2 .

[0109] In implementation, such as Figure 2 As shown, the SiC lateral JFET device of the present application also includes:

[0110] A gate shielding plate 202 located in the oxide layer and between the gate 110 and the drain 106;

[0111] a gate shielding plate contact via located in the oxide layer and above the gate shielding plate, the gate shielding plate contact via being connected to the source metal layer 204 - 1;

[0112] The gate shielding plates include L-shaped gate shielding plates and Z-shaped gate shielding plates that are spaced apart from the gate 110 toward the drain 106 .

[0113] In this way, the connection between the gate shielding plate and the source 107 is achieved. The existence of the gate shielding plate can effectively isolate the drain and the gate, significantly reduce the reverse isolation capacitance of the device, and can significantly reduce the parasitic capacitance between the drain 106 and the gate 110, thereby improving the performance of the lateral SiC-JFET device.

[0114] In implementation, such as Figure 2 As shown, the gate shielding plate 202 includes an L-shaped gate shielding plate and a Z-shaped gate shielding plate which are arranged in an interval from the gate 110 to the drain 106 .

[0115] The shape and position of the gate shield plate affect the breakdown voltage, parasitic capacitance and reliability of the device. The specific shape and position should be adjusted according to the device design parameter indicators.

[0116] The preparation process of the SiC lateral JFET device of the present application is described below, including the following steps:

[0117] like Figure 3 As shown, step S1: first grow 102 a heavily doped P-type first epitaxial layer 102 on a heavily doped N-type substrate 101, and then grow 103 a lightly doped P-type second epitaxial layer 103 on this basis; then carve out a first through hole through a deposition and etching process, and then deposit polycrystalline heavily doped silicon carbide in the hole through a deposition and polishing process, and finally form a connection area 112.

[0118] like Figure 4 As shown, step S2: forming an N-type drift region 104, a drain step implantation 105, a drain contact 106, a source 107, a first source contact region 108, a channel region 109, a P-type gate 110, and a second source contact region 111 in the second epitaxial layer 103 through an implantation process.

[0119] like Figure 5 As shown, step S3: on the basis of the above structure, a source contact metal compound 201 - 1 , a gate contact metal compound 201 - 2 , and a drain contact metal compound 201 - 3 are formed.

[0120] like Figure 6 As shown, step S4: based on the above structure, the oxide layer 206, the source contact through hole 203-1, the gate contact through hole 203-2, the drain contact through hole 203-3, and the gate shielding plate 202 are prepared layer by layer through deposition-etching and other processes.

[0121] like Figure 7 As shown, step S5: on the basis of the above, a source metal layer 204 - 1 and a drain metal layer 204 - 3 are prepared by deposition, etching and other processes.

[0122] Figure 8 This is a simulation diagram of the SiC lateral JFET device of the present application.

[0123] Fig. 9 : is the Id-Vg curve of the SiC lateral JFET device of the present application. Fig. 9 As shown, the gate voltage Vg of the SiC lateral JFET device of the present application is lower than a certain value (about -9V), and the device is turned off;

[0124] When the gate voltage Vg is higher than a certain value (about -9V), the drain current Id increases with the increase of the gate voltage Vg. The overall device can be turned on and off and has good gate control capability.

[0125] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0126] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0129] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0130] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A SiC lateral JFET device, characterized in that: include: A substrate (101) of a second doping type, wherein the substrate (101) is grounded; An epitaxial layer of SIC material of a first doping type is formed on a substrate (101); A first through hole, penetrating the epitaxial layer from the upper surface of the epitaxial layer downwards, and the bottom end of the first through hole enters into the substrate (101); A connection region (112) of a second doping type SIC material filled in the first through hole; A source electrode (107) of a first doping type formed in the epitaxial layer; A source contact metal compound (201-1) is formed on the connection area (112) and is electrically connected to the source (107); The source contact metal compound (201-1) is electrically connected to a grounded second doping type substrate (101) via a second doping type connection region (112).

2. The SiC lateral JFET device according to claim 1, characterized in that: The substrate (101) is a single crystal low-resistance substrate (101); The connection region (112) is a connection region of a polycrystalline SIC material, and the connection between the bottom end of the connection region (112) and the substrate (101) satisfies the following conditions: The doping concentration of the substrate (101) is 1×10 20 cm -3 The doping concentration of the connection region (112) is greater than or equal to the doping concentration of the substrate.

3. The SiC lateral JFET device according to claim 2, characterized in that: The depth of the connection area (112) entering the substrate (101) ranges from greater than or equal to 0.1 μm to less than or equal to 100 μm.

4. The SiC lateral JFET device according to claim 1, characterized in that: The substrate (101) is a low-resistance substrate (101); The epitaxial layer is a single crystal epitaxial layer.

5. The SiC lateral JFET device according to any one of claims 1 to 4, characterized in that: The epitaxial layer comprises: A first epitaxial layer (102) of a first doping type, formed on the substrate (101); A second epitaxial layer (103) of a first doping type is formed on the first epitaxial layer (102); the source (107) is formed in the second epitaxial layer (103); wherein the doping concentration of the first epitaxial layer (102) is greater than the doping concentration of the second epitaxial layer (103); A first source contact region (108) of a first doping type and a second source contact region (111) of a second doping type are arranged side by side on the source (107), and the source contact metal compound (201-1) is located on the first source contact region (108) and the second source contact region (111); A source contact through hole (203-1) formed on the source contact metal compound (201-1); A source metal layer (204-1) is formed on the source contact through hole (203-1).

6. The SiC lateral JFET device according to claim 5, characterized in that: Also includes: A drift region (104) of a second doping type is formed in the first epitaxial layer (102); A channel region (109) located above the source (107); A gate (110) located above the channel region (109); The channel region (109) and the drift region (104) are respectively channel regions (109) and drift regions (104) of independent structures.

7. The SiC lateral JFET device according to claim 6, characterized in that: A first gap is provided between the source (107) and the drift region (104); A second gap is provided between the gate (110) and the second source contact region (111), and between the gate (110) and the drift region (104); The PN junction formed by the drift region (104) and the first epitaxial layer (102), the PN junction formed by the drift region (104) and the source (107), and the PN junction formed by the drift region (104) and the gate (110) are broken down in order.

8. The SiC lateral JFET device according to claim 7, characterized in that: Also includes: an oxide layer (206); A drain electrode (106) is located in the drift region (104) and is spaced apart from the gate electrode (110); A drain implantation region (105) located below the drain (106); A drain contact metal compound (201-3) located in the oxide layer and above the drain (106); A drain contact through hole (203-3) located in the oxide layer and above the drain contact metal compound (201-3); A drain metal layer (204-3) is located in the oxide layer and above the drain contact through hole (203-3).

9. The SiC lateral JFET device according to claim 8, characterized in that: Also includes: A gate contact metal compound (201-2) located in the oxide layer and above the gate (110); A gate contact through hole (203-2) is located in the oxide layer and above the gate contact metal compound (201-2).

10. The SiC lateral JFET device according to claim 9, characterized in that: Also includes: A gate shielding plate (202) located within the oxide layer and between the gate (110) and the drain (106); A gate shielding plate contact through hole located in the oxide layer and above the gate shielding plate, the gate shielding plate contact through hole being connected to the source metal layer (204-1); The gate shielding plate comprises an L-shaped gate shielding plate and a Z-shaped gate shielding plate which are arranged at intervals from the gate (110) to the drain (106).

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