Processing dielectric film under bottom of source / drain region

Abstract

The invention discloses processing a dielectric film under the bottom of a source / drain region. A method includes forming a gate stack over a semiconductor region; etching the semiconductor region to form a source / drain recess aside the gate stack; depositing a first dielectric layer, wherein a portion of the first dielectric layer is in the source / drain recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; and etching the second dielectric layer and the first dielectric layer. A first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region. A source / drain region is deposited in the source / drain recess and over the dielectric region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to processing a dielectric film below the bottom of a source / drain region. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a gate stack above a semiconductor region; etching the semiconductor region to form a source / drain recess next to the gate stack; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; and depositing a source / drain region in the source / drain recess and above the dielectric region.

[0005] According to a second aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a protruding feature, the protruding feature comprising: a first sacrificial nanosheet on a bulk semiconductor substrate; a first semiconductor nanosheet on the first sacrificial nanosheet; a second sacrificial nanosheet on the first semiconductor nanosheet; and a second semiconductor nanosheet on the second sacrificial nanosheet; forming a gate stack on the sidewall and top surface of the protruding feature; etching the protruding feature to form a recess, wherein the first bottom of the recess is lower than the second bottom of the first semiconductor nanosheet; depositing a first dielectric layer in the recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching the sidewall portions of the first dielectric layer and the second dielectric layer, leaving a dielectric region at the first bottom of the recess, wherein the dielectric region comprises a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer; and forming a source / drain region on the dielectric region.

[0006] According to a third aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: etching a semiconductor nanosheet to form a source / drain recess, wherein the source / drain recess comprises a first bottom portion, which is lower than a second bottom portion of the semiconductor nanosheet; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess, and the first dielectric layer comprises a first dielectric material; performing a treatment process on the first dielectric layer to convert the first dielectric material into a second dielectric material; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; performing a pre-cleaning process using an etching gas, wherein the etching gas is capable of etching the first dielectric material at a first etching rate, and is capable of etching the second dielectric material at a second etching rate, and wherein the second etching rate is lower than the first etching rate; and growing a semiconductor region in the source / drain recess by an epitaxial process. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1-Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B A cross-sectional view of an intermediate stage in forming a Gate-All-Around (GAA) transistor is shown in accordance with some embodiments.

[0009] Figures 15 to 19A and Fig. 20A A cross-sectional view is shown of an intermediate stage in the formation of a dielectric layer and overlying source / drain regions in accordance with some embodiments.

[0010] Fig.19B , Fig. 20B , Fig.19C and Fig. 20C A cross-sectional view is shown of an intermediate stage in the formation of a dielectric region and overlying source / drain regions in accordance with some embodiments.

[0011] Fig.21 Deposition of a dielectric layer and subsequent post-treatment processes are shown in accordance with some embodiments.

[0012] Fig. 22 A comparison of untreated samples and treated samples according to some embodiments is shown.

[0013] Fig.23 A process flow for forming a GAA transistor according to some embodiments is shown.

[0014] Fig.24 A process flow for forming a dielectric region and overlying source / drain regions is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] A gate all around (GAA) transistor is provided, the GAA transistor having a dielectric region including a treated dielectric layer located below a source / drain region. A method of forming a dielectric region is provided. According to some embodiments, after depositing the dielectric layer in the source / drain recess, a treatment process is performed to improve the quality of (one or more) dielectric layers. The dielectric layer has a stronger resistance to subsequent etching and cleaning processes. Leakage between the source / drain region and the underlying substrate is thereby reduced. Parasitic capacitance between the gate electrode and the source / drain region is also reduced.

[0018] Although the concepts of the present disclosure are discussed using GAA transistors as an example, the embodiments are applicable to other types of transistors, such as fin field effect transistors (FinFETs). The embodiments discussed herein provide examples to enable the manufacture or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that may be made within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0019] Figure 1-Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B FIG. 1 shows a cross-sectional view of an intermediate stage of forming a GAA transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in FIG. Fig.23 The process flow shown.

[0020] refer to Figure 1 , a perspective view of a wafer 10 is shown. The wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., and other substrates and / or structures may be used, such as a semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0021] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. Fig.23 The process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0022] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to be approximately Peace However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0023] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, and vice versa. It will be appreciated that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0024] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the first layer 22A has a thickness in a range between about 4 nm and about 7 nm, while the second layer 22B has a thickness in a range between about 8 nm and about 12 nm.

[0025] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired topmost layer of the multilayer stack 22 is formed. According to some embodiments, the first layer 22A has the same or similar thickness as each other, and the second layer 22B has the same or similar thickness as each other. The first layer 22A may also have the same thickness as the second layer 22B or a different thickness. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0026] According to some embodiments, there may be some pad oxide layer(s) and hard mask layer(s) (not shown) above the multilayer stack 22 . These layers are patterned and used for subsequent patterning of the multilayer stack 22 .

[0027] refer to Figure 2 , the multilayer stack 22, and a portion of the underlying substrate 20 are patterned in (one or more) etching processes to form trenches 23. The corresponding process is Fig.23The process flow 200 is shown as process 204. The trench 23 extends into the substrate 20. The remaining portion of the multilayer stack is referred to as the multilayer stack 22' below. Below the multilayer stack 22', some portions of the substrate 20 are left and are referred to as substrate strip 20' below. The multilayer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, the semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is alternatively referred to as a nanostructure. Portions of the multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0028] In the above-described embodiments, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines photolithography and self-alignment processes, allowing patterns to be created with, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0029] Figure 3 The formation of isolation regions 26 is shown, which are also referred to as shallow trench isolation (STI) regions throughout the specification. Fig.23 The process flow 200 is shown as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process may then be performed to level the top surface of the dielectric material, and the remaining portion of the dielectric material is the STI region 26.

[0030] The STI regions 26 are then recessed so that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI regions 26 to form protruding fins 28. The protruding fins 28 include the multilayer stack 22' and the top portion of the substrate strip 20'. The recessing of the STI regions 26 can be performed by a dry etching process, wherein NF3 and NH3 are used as etching gases, for example. During the etching process, plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI regions 26 is performed by a wet etching process. For example, the etching chemical can include HF.

[0031] refer to Figure 4 , forming a dummy gate stack 30 and a gate spacer 38 on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is Fig.23 The process flow 200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 located on the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrode 34 may be formed, for example, using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used.

[0032] Each dummy gate stack 30 may also include one (or more) hard mask layers 36 located above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbon nitride oxide, or a multilayer thereof. The dummy gate stack 30 may span a single or multiple protruding fins 28, and the STI region 26 between the protruding fins 28. The longitudinal direction of the dummy gate stack 30 is also perpendicular to the longitudinal direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by (one or more) patterning processes.

[0033] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of (one or more) dielectric layers is the gate spacer 38.

[0034] Figure 5A and Figure 5B Shows Figure 4 A cross-sectional view of the structure shown. Figure 5A Shows Figure 4 Referring to the reference section A1-A1 in FIG. 1 , the section cuts through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38 and is perpendicular to the gate length direction. The fin spacer 38 located on the sidewall of the protruding fin 28 is also shown. Figure 5B Shows Figure 4 , which is parallel to the longitudinal direction of the protruding fin 28.

[0035] refer to Fig. 6A and Figure 6B , the portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. Fig.23 The process flow 200 is shown as process 210. For example, a dry etching process can be performed using C2F6; CF4; SO2; a mixture of HBr, Cl2 and O2; a mixture of HBr, Cl2, O2 and CH2F2, etc. to etch the multilayer semiconductor stack 22' and the substrate strip 20' below. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or can be lower than (e.g., Figure 6B The etching may be anisotropic so that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in FIG. Figure 6B shown.

[0036] refer to Fig. 7A and Figure 7B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed from the edges of the corresponding upper and lower nanostructures 22B. Fig.23 The process flow 200 is shown as process 212. The lateral recessing of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than to the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment in which the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using a dipping process, a spraying process, a spin coating process, etc.

[0037] According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process, or a combination of a dry etching process and a wet etching process.

[0038] refer to Fig. 8A and Figure 8B , forming the internal spacer 44. The corresponding process is Fig.23 The process flow 200 is shown as process 214. According to some embodiments, the formation of the inner spacer 44 includes depositing a conformal dielectric layer that extends to the lateral recess 41 ( Figure 7B Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, leaving some portion of the spacer layer in the lateral recess 41. The remaining portion of the spacer layer is referred to as an inner spacer 44.

[0039] refer to Fig.9A and Fig. 9B , a dielectric region 46 and an epitaxial source / drain region 48 are formed in the recess 42. The corresponding process is Fig.23 The process flow 200 shown is shown as process 216. According to some embodiments, the source / drain region 48 can stress the nanostructure 22B used as the channel of the corresponding GAA transistor, thereby improving performance. Depending on whether the resulting transistor is a p-type transistor or an n-type transistor, p-type or n-type impurities can be in-situ doped during the epitaxy process. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown.

[0040] After the recess 42 is filled with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally and may form facets. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other. A void (air gap) may be generated under the merged epitaxial region 48.

[0041] Figure 15-18 , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C The formation of dielectric region 46 and source / drain region 48 (eg, Fig.9A and 9B details shown). Figure 15-18 , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C The process shown is also Fig.24 The process flow 300 is shown as an example, where the process flow 300 shows details of the process 216 shown in the process flow 200 .

[0042] Fig.15 Shows Figure 8B The region 45 in which the recess 42 and the inner spacer 44 have been formed. Next, a dielectric layer 46B is deposited. Fig.24 The process flow 300 is shown as process 302. According to some embodiments, the dielectric layer 46B includes an oxygen-containing dielectric material, such as SiON, SiO, SiOC, etc. The corresponding precursors may include a silicon-containing precursor and an oxygen-containing precursor. The silicon-containing precursor may include bis(diethylamino)silane ((BDEAS)(SiH2[N(CH2CH3)2]2), silane, disilane, etc., or a combination thereof. The oxygen-containing precursor may be selected from CO2, O2, NO2, etc., and a combination thereof. A carrier gas including Ar, He, etc., or a combination thereof may be used.

[0043] Fig.21 An example formation process for depositing dielectric layer 46B according to some embodiments is shown. Deposition of dielectric layer 46B can be performed using atomic layer deposition (ALD), plasma enhanced ALD (PEALD), chemical vapor deposition (CVD), etc. The illustrated example process is performed using PEALD, which includes repeating a plurality of ALD cycles, one of which is shown. The illustrated ALD cycle is repeated.

[0044] The example process uses BDEAS and CO2 as precursors and Ar as a carrier gas, but other precursors and carrier gases may be used. The plasma may be turned on at a certain time to initiate (and accelerate) the reaction and process. Each gas and plasma may be represented by a line, where a line is in a higher position, indicating that the gas is introduced or the plasma is turned on, and a line is in a lower position, indicating that the gas is cut off or the plasma is turned off.

[0045] According to some embodiments, CO2 and Ar are continuously introduced in the ALD cycle. The flow rate of the oxygen-containing precursor (such as CO2) can be in a range between about 1 slm and about 10 slm. BDEAS is pulsed and adsorbed on the wafer 10, and then purged by the subsequently introduced Ar and CO2. The pulsing time (feed time) can be in a range between about 0.5 seconds and about 2.5 seconds. According to some embodiments, after purging BDEAS, the plasma is turned on by applying radio frequency (RF) power to react CO2 with the adsorbed BDEAS to form SiCO. The ALD cycle is repeated until the thickness of the dielectric layer 46B reaches a desired value, for example, the desired value is in a range between about 0.5 nm and about 2.5 nm.

[0046] According to some embodiments, during the deposition of dielectric layer 46B, the wafer temperature of wafer 10 may be in a range between about 75° C. and about 390° C., or may be in a range between about 75° C. and about 100° C. The plasma may be generated using an inductively coupled plasma (ICP) or a capacitively coupled plasma (CCP). The RF on time (for generating the plasma) may be in a range between about 0.2 seconds and about 1.2 seconds, or may be in a range between about 0.2 seconds and about 0.4 seconds. The RF power may be in a range between about 15 watts and about 600 watts.

[0047] After dielectric layer 46B is deposited, as Fig.21 As shown, by turning on the RF power and thus the plasma, a treatment process 47 (also referred to as a post-treatment process) is performed. The treatment process 47 is also shown in FIG. Fig.15 The corresponding process is shown in Fig.24 The process flow 300 shown is shown as process 304. The deposited dielectric layer 46B may be defective and may have dangling bonds. According to some embodiments, the treatment process 47 may attach oxygen atoms to the dangling bonds to repair the defects. The treated dielectric layer 46B thus becomes denser. For example, the density of the dielectric layer 46B may be about 3% to about 5% higher than before the treatment process 47. In addition, due to the elimination of dangling bonds, the etching rate of the dielectric layer 46B is reduced in subsequent etching and cleaning processes. According to some embodiments, the process gas used for the treatment process 47 may be selected from CO2, O2, NO2, etc., or a combination thereof. The flow rate of the process may be in the range of about 1 slm and about 10 slm.

[0048] According to some embodiments, the treatment process can be performed in situ (in the same vacuum environment) with the deposition of dielectric layers 46B and 46A. For example, the treatment process can be performed after a delay time during which CO2 and Ar are continuously introduced. According to some embodiments, the flow rates of CO2 and Ar remain unchanged. According to alternative embodiments, the flow rates of CO2 and Ar can be increased or decreased, and then the treatment process 47 is performed.

[0049] According to alternative embodiments, the treatment process may be performed ex-situ compared to the deposition of dielectric layer 46B. The vacuum environment used for treatment process 47 may be the same (but in a different chamber) or different (with a vacuum break in between) than the vacuum environment used to deposit dielectric layer 46B.

[0050] According to some embodiments, during the treatment process 47, the wafer temperature of the wafer 10 can be in a range between about 75°C and about 390°C, and can be in a range between about 75°C and about 100°C. The plasma can be generated using ICP or CCP. The RF turn-on time (for generating the plasma) can be in a range between about 0.2 seconds and about 1.2 seconds, or can be in a range between about 0.4 seconds and about 0.8 seconds. The post-processing time can also be longer than the RF turn-on time inside the ALD cycle. The RF power of the post-processing can be in a range between about 15 watts and about 600 watts. The RF power used in the post-processing can also be higher than the RF power used during the ALD cycle. For example, the RF power of the post-processing can be in a range between about 400 watts and about 600 watts.

[0051] According to some embodiments, the treatment process 47 is performed by an isotropic treatment process, in which no bias power is applied. According to an alternative embodiment, the post-treatment is performed by an anisotropic treatment process, in which a bias power is applied. The bias power may be less than about 15 watts. To ensure that the portion of the dielectric layer 46B at the bottom corner of the recess 42 is treated, the post-treatment may also be performed by an inclined treatment, and the inclination angle is adjusted so that the ions of the treatment gas can directly reach the bottom corner of the recess 42. For example, Fig.15 Arrows 43 are shown, which indicate the direction in which ions (generated by the treatment process, including oxygen ions) will arrive at the bottom corner portion of dielectric layer 46B. The tilt angle α (the angle of incidence of the ions relative to the vertical direction) is selected to ensure that the ions are not blocked by the upper portion of gate stack 30. The tilt angle α can be greater than zero degrees and less than the tilt angle α shown, and is related to the aspect ratio of recess 42.

[0052] Fig.16 The deposition of dielectric layer 46A is shown. Fig.24This is shown as process 306 in the illustrated process flow 300. Dielectric layer 46A is formed of a material different from the material of dielectric layer 46B. Dielectric layer 46A may have a higher atomic percentage of nitride than dielectric layer 46B, so that in subsequent etching and cleaning processes, the etching selectivity between dielectric layers 46B and 46A is higher. For example, dielectric layer 46A may be formed of, or include, silicon nitride (SiN), SiOCN, SiCN, etc.

[0053] According to some embodiments, due to the topology and characteristics of the deposition process, dielectric layer 46A includes sidewall portions 46A-S, bottom portions 46A-B, and top portions 46A-T, which have different characteristics. For example, in subsequent etching and cleaning processes, sidewall portions 46A-S of dielectric layer 46A have an etching rate ER-S, top portions 46A-T of dielectric layer 46A have an etching rate ER-T, and bottom portions 46A-B of dielectric layer 46A have an etching rate ER-B. The etching rates may have the following relationship: ER-S>ER-T>ER-B. Therefore, sidewall portions 46A-S are easily damaged in subsequent processes.

[0054] Fig.17 FIG. 4 shows etching of dielectric layer 46A according to some embodiments. Fig.24 This is shown as process 308 in the illustrated process flow 300. The etching may be isotropic, and the etching gas or etching solution is selected based on the material of dielectric layers 46A and 46B. During the etching process, dielectric layer 46B is not etched (or is etched but at a lower rate). Since sidewall portions 46A-S are etched faster than top portions 46A-T, there may (or may not) be a portion of top portions 46-T remaining after the etching process.

[0055] Etching may include a dry etching process or a wet etching process. In the dry etching process, a fluorine-containing gas may be used, for example, CF4, NF3, SF6, CHF3, ClF3, or a combination thereof. Other gases may also be added, for example, O2, N2, H2, Ar, NO, etc. In the wet etching process, a chemical solution such as H3PO4 solution may be used.

[0056] At the bottom of recess 42 , some bottom portion 46A-B of dielectric layer 46A remains. This is due in part to the lower etch rate ER-B of bottom portion 46A-B than the etch rate of sidewall portions 46A-S and in part to the high aspect ratio of recess 42 .

[0057] Fig.18The etching of dielectric layer 48B is shown, which may be performed using a chemistry that etches dielectric layer 48B but does not (or etches but at a lower rate) dielectric layer 46A. Fig.24 The process flow 300 is shown as process 310. Etching can also include a dry etching process or a wet etching process. For example, when performing dry etching, the etching gas can include a mixture of NF3 and NH3, a mixture of HF and NH3, or HF. When performing wet etching, a diluted HF solution can be used.

[0058] After the etching process, dielectric region 46 (including remaining portions of dielectric layers 46B and 46A) remains at the bottom of recess 42. At the top of dummy gate stack 30, some portions of dielectric layers 46B and 46A may also (or may not) remain.

[0059] In subsequent processes, such as Fig.19A , Fig.19B and Fig.19C As shown, a pre-cleaning process 49 may be performed to prepare the wafer 10 for a subsequent epitaxial process. Fig.24 The process flow 300 is shown as process 312. According to some embodiments, the pre-cleaning process 49 is performed by a dry etching process, which can remove residues and undesirable chemicals left by the previous process. For example, according to some embodiments, the etching gas may include HF gas. The etching gas may include a gas that is the same (or different) as the gas used to etch the dielectric layer 46B. For example, HF can be used for both etching the dielectric layer 46B and the pre-cleaning process 49.

[0060] According to some embodiments, the process gas used for the pre-cleaning process 49 is capable of etching the material of the dielectric layer 46B. Fig.15 ), the density of dielectric layer 46B is increased and / or dangling bonds of dielectric layer 46B are removed. This causes the etch rate of dielectric layer 46B to be reduced in pre-cleaning process 49. For example, for some pre-cleaning chemistries (e.g., HF), the etch rate of dielectric layer 46B before treatment process 47 will be significantly higher than the etch rate of dielectric layer 46A. If treatment process 47 is not performed, this will result in the sidewall portion of dielectric layer 46B in region 51 being undesirably removed, and a void will be formed in region 51.

[0061] The subsequently deposited epitaxial semiconductor region 48 will fill the gap and may contact the substrate 20. This will result in the source / drain region 48 ( Fig.19A ) and the substrate 20. In addition, the parasitic capacitance between the source / drain region 48 and the subsequently formed gate electrode will increase.

[0062] By post-treating the dielectric layer 46B, the etching rate of the dielectric layer 46B during the pre-cleaning process is reduced. For example, assuming that the process gas used for the pre-cleaning 49 has an etching rate ER-46A for etching the dielectric layer 46A, an etching rate ER-46B1 for etching the dielectric layer 46B that has not been processed by the treatment process 47, and an etching rate ER-46B2 for etching the dielectric layer 46B that has been processed by the treatment process 47, the etching rate ER-46B2 is less than the etching rate ER-46B1, and due to the treatment process 47, the ratio ER-46B2 / ER-46A is reduced to be less than the ratio ER-46B1 / ER-46A. The etching rate ratio ER-46B2 / ER-46B1 may also be less than 1, and may be in the range between about 0.6 and about 1.

[0063] According to some embodiments, treatment process 47 makes the etching rate ER-46B2 of the treated dielectric layer 46B lower than the etching rate ER-46A of the dielectric layer 46A in the pre-cleaning process 49. According to an alternative embodiment, treatment process 47 makes the etching rate ER-46B2 of the treated dielectric layer 46B lower, but still equal to or slightly higher than the etching rate ER-46A of the dielectric layer 46A during the pre-cleaning process. Therefore, in the pre-cleaning process, the sidewall portion of the dielectric layer 46B in the region 51 is not etched or is less etched, and a considerable portion remains. The adverse increase of the leakage current and the adverse increase of the parasitic capacitance are eliminated.

[0064] According to some embodiments, additional treatment process 47′ may be performed at a time after dielectric layer 46A is etched and before dielectric layer 46B is etched. Fig.18 According to some embodiments, additional treatment process 47 may be performed after dielectric layer 46B is etched and before pre-cleaning process 49" ( Fig.19A , Fig.19B and Fig.19C ). The details of the treatment processes 47' and 47" may be substantially the same as the post-treatment process 47 and will not be described in detail herein. The treatment processes 47' and 47" also have the effect of densifying the dielectric layer 46B and removing dangling bonds from the dielectric layer 46B, as well as reducing the etching rate of the dielectric layer 46B in the pre-cleaning process 49. According to some embodiments, at least one or more of the treatment processes 47, 47' and 47" may be performed in any combination to achieve the desired effect, while other processes in the treatment processes 47, 47' and 47" may not be performed.

[0065] According to some embodiments, Fig.19AAs shown, after the pre-cleaning process, the top surface of dielectric region 46 is recessed. This may be due to the fact that the etching rate of dielectric layer 46B is lower than the etching rate of dielectric layer 46A during the pre-cleaning process. Therefore, the top edge 46B-TOP of dielectric layer 46B is higher than the top surface of dielectric layer 46A. The top edge 46B-TOP of dielectric layer 46B may be flush with or lower than the bottom surface 22B-BOT of the bottommost semiconductor nanosheet 22B. According to some embodiments, the top surface of dielectric region 46 is lower than the bottom surface 22B-BOT and is indicated by dashed line 46-TOP'.

[0066] According to an alternative embodiment, Fig.19B As shown, after the pre-cleaning process, dielectric region 46 has a convex top surface. This may be due to the fact that during the pre-cleaning process, the etching rate of dielectric layer 46B is higher than the etching rate of dielectric layer 46A. Therefore, the top edge 46B-TOP of dielectric layer 46B is lower than the top surface of dielectric layer 46A. The top edge 46B-TOP of dielectric layer 46B may also be flush with or lower than bottom surface 22B-BOT. According to some embodiments, the top surface of dielectric region 46 is lower than bottom surface 22B-BOT and is indicated by dashed line 46-TOP'.

[0067] According to other alternative embodiments, Fig.19C As shown, after the pre-cleaning process, dielectric region 46 has a flat top surface. This may be because during the pre-cleaning process, the etching rate of dielectric layer 46B is equal to the etching rate of dielectric layer 46A. Therefore, top edge 46B-TOP of dielectric layer 46B is flush with the top surface of dielectric layer 46A. Top edge 46B-TOP of dielectric layer 46B may also be flush with or lower than bottom surface 22B-BOT. According to some embodiments, the top surface of dielectric region 46 is lower than bottom surface 22B-BOT and is represented by dashed line 46-TOP'.

[0068] exist Fig.19A and Fig.19B In the illustrated embodiment, when dielectric region 46 has top surface 46-TOP′ shown as a dashed line, a height difference ΔH1 ( Fig.19A ) may be equal to or less than about 0.6 nanometers, or equal to or less than (ΔH3) / 2, where ΔH3( Fig.19A ) is the height difference between bottom surface 22B-BOT and the top surface of the main portion of substrate 20 (also the bottom of dielectric region 46). Otherwise, the subsequently formed source / drain regions 48 ( Fig. 20A , Fig. 20B and Fig. 20C) and the parasitic capacitance between the gate electrode 68 will undesirably increase.

[0069] The recessed depth ΔH2 of the top surface of the dielectric region 46 may also be equal to or less than (ΔH3) / 2. Otherwise, the dielectric region 46 may have cracks, and the subsequently formed source / drain regions 48 ( Fig. 20A ) and the substrate 20 will experience leakage current.

[0070] Fig. 20A , Fig. 20B and Fig. 20C The formation of epitaxial source / drain regions 48 is shown. Fig.24 The process flow 300 is shown as process 314 and is shown as process 314 in FIG. Fig.23 This is shown as process 216 in the illustrated process flow 200 . Fig. 20A , Fig. 20B and Fig. 20C Corresponding to Fig.19A , Fig.19B and Fig.19C , and also shows the source / drain region 48. The formation of the source / drain region 48 has been referred to Fig.9A and Fig. 9B A discussion was held.

[0071] Next, a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 are formed. Fig. 20A , Fig. 20B and Fig. 20C These features are also Fig. 10A and Fig. 10B As shown in FIG. 1 and discussed later, a replacement gate stack 70 is also formed and the formation process is performed in Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B The details of the formation of these features will be discussed later. Fig. 10A and FIG. 10B to FIG. 14A and Fig. 14B Have a discussion.

[0072] Fig. 10A and FIG. 10B to FIG. 14A and Fig. 14B Shown is a reference Fig. 20A , Fig. 20B and Fig. 20C Details of some of the features discussed. These figures may have corresponding figure numbers followed by the letters A and B. Figures with the letter A in the figure number indicate that the corresponding figure shows the same Figure 4 The same reference section A2-A2 in FIG. 1 is the same reference section A2-A2 in FIG. The drawings with the letter B in the figure number indicate that the corresponding drawings show the same Figure 4 The reference cross section BB in is the same as the reference cross section.

[0073] Fig. 10A and Fig. 10B FIG. 4 shows a cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. Fig.23 The process flow 200 is shown as process 218. CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0074] The CESL 50 and the ILD 52 are planarized by a planarization process such as a CMP process or a mechanical grinding process. Fig.23 The process flow 200 is shown as process 220. According to some embodiments, the planarization process may remove the hard mask 36 to reveal the dummy gate electrode 34, such as Fig. 10A According to alternative embodiments, the planarization process may reveal the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within process variations.

[0075] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if remaining) are removed in one or more etching processes, thereby forming the recess 58, as shown in FIG. Fig.11A and Fig. 11B The corresponding process is shown in Fig.23 The dummy gate electrode 34 and the dummy gate dielectric 32 are shown as process 222 in the illustrated process flow 200. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process(es). For example, the etching process may be performed using a reactive gas(es) that selectively etches the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than the ILD 52. Each recess 58 exposes and / or covers portions of the multilayer stack 22' that include future channel regions in a subsequently completed transistor.

[0076] The sacrificial layer 22A is then removed to extend the recess 58 between the nanostructures 22B. Fig.23This is shown as process 224 in the illustrated process flow 200. The sacrificial layer 22A may be removed by performing an isotropic etching process (e.g., a wet etching process using an etchant that is selective to the material of the sacrificial layer 22A), while the nanostructures 22B, the substrate 20, and the STI regions 26 remain relatively unetched compared to the sacrificial layer 22A. According to some embodiments in which the sacrificial layer 22A includes, for example, SiGe and the nanostructures 22B include, for example, Si or SiC, the sacrificial layer 22A may be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0077] refer to Fig. 12A and Fig. 12B , forming a gate dielectric 62 and a gate electrode 68, thereby forming a replacement gate stack 70. The corresponding process is Fig.23 The process flow 200 is shown as process 226. According to some embodiments, each gate dielectric 62 includes an interfacial layer and a high-k dielectric layer located on the interfacial layer. The interfacial layer can be formed of silicon oxide or can include silicon oxide, which can be deposited by a conformal deposition process such as ALD or CVD, or by an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the (one or more) high-k dielectric layer may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0078] A gate electrode 68 is also formed. During the formation process, a conductive layer is first formed on the high-k dielectric layer and fills the remaining portion of the recess 58. The gate electrode 68 may include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 68 may include any number of layers, any number of work function layers, and possible filling materials. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B and fill the space between the bottom nanostructure 22B and the substrate strip 20' below. After the recess 58 is filled, a planarization process (e.g., a CMP process or a mechanical grinding process) is performed to remove the material of the gate electrode 68 and the excess portion of the gate dielectric, which is located above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0079] exist Fig.13A and Fig. 13BIn the process shown, the gate stack 70 is recessed so that recesses are formed directly above the gate stack 70 and between the opposing portions of the gate spacers 38. A gate mask 74 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess, and then a planarization process is performed to remove excess portions of the dielectric material that extend above the ILD 52. The corresponding process is Fig.23 This is shown as process 228 in the illustrated process flow 200 .

[0080] like Fig.13A and Fig. 13B As further shown, ILD 76 is deposited over ILD 52 and gate mask 74. Fig.23 The process flow 200 is shown as process 230. An etch stop layer (not shown) may or may not be deposited before forming ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0081] exist Fig.14A and Fig. 14B In the embodiment, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surface of source / drain regions 48 and / or gate stack 70. The recesses may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). Fig. 14B The contact plugs 80A and 80B are shown in the same cross-section, but in various embodiments, the contact plugs 80A and 80B may be formed in different cross-sections to reduce the risk of shorting each other.

[0082] After forming the recess, a silicide region 78 is formed on the source / drain region 48. Fig.23 This is shown as process 232 in the process flow 200. Then, a contact plug 80B is formed on the silicide region 78. In addition, a plug 80A (also referred to as a gate contact plug) is formed in the recess, and the plug 80A is on and in contact with the gate electrode 68. The corresponding process is Fig.23 This is shown as process 234 in the illustrated process flow 200. Transistor 82 is thereby formed.

[0083] Fig. 22Some experimental results obtained from some samples are shown. X represents the V trigger voltage, that is, the voltage required to turn on the parasitic transistor in the structure of the embodiment so that the current is conducted to the substrate 20 as leakage current. An example specification is that the V trigger voltage needs to be greater than 1.6 volts. The Y axis represents the normal quantile of multiple samples. The samples shown in the left half of the figure are obtained from samples where the formation of the dielectric region does not include treatment 47. It is observed that the V trigger voltage of some samples is less than about 1.3 volts, and the V trigger voltage of all samples is less than about 1.45 volts, so these samples do not meet the specification.

[0084] The samples shown in the right half of the figure are obtained from samples where the formation of the dielectric region includes process 47. It is observed that the Vtrigger voltage of all samples is greater than 1.6 volts, and thus these samples meet the specification.

[0085] Embodiments of the present disclosure have several advantageous features. Undesirable etching of corner portions of the bottom dielectric layer is eliminated through a post-processing process during formation of the bottom dielectric layer. Leakage current between the source / drain region and the underlying substrate is reduced or eliminated. Parasitic capacitance between the source / drain region and the gate electrode is also reduced.

[0086] According to some embodiments of the present disclosure, a method includes: forming a gate stack above a semiconductor region; etching the semiconductor region to form a source / drain recess next to the gate stack; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; and depositing a source / drain region in the source / drain recess and above the dielectric region.

[0087] In one embodiment, depositing the first dielectric layer includes depositing an oxygen-containing dielectric layer, and depositing the second dielectric layer includes depositing a nitrogen-containing dielectric layer. In one embodiment, the treatment process is performed using an oxygen-containing process. In one embodiment, the treatment process includes a plasma treatment process. In one embodiment, the method further includes: performing a pre-cleaning process after the dielectric region is formed and before the source / drain region is deposited. In one embodiment, the pre-cleaning process is performed using HF gas.

[0088] In one embodiment, the first dielectric layer is deposited using plasma enhanced atomic layer deposition including a plurality of cycles, and wherein the treatment process includes turning on radio frequency power to generate plasma. In one embodiment, depositing the first dielectric layer includes introducing a process gas as a precursor, and wherein the treatment process is also performed using the process gas to generate plasma.

[0089] In one embodiment, depositing the first dielectric layer includes introducing a first process gas as a precursor, and wherein the treatment process is performed using a second process gas different from the first process gas to generate a plasma. In one embodiment, the treatment process is performed using carbon dioxide (CO2) as the process gas. In one embodiment, the semiconductor region includes a semiconductor nanosheet, wherein the semiconductor nanosheet is included in a protruding feature, the protruding feature including an additional semiconductor nanosheet stacked on the semiconductor nanosheet.

[0090] According to some embodiments of the present disclosure, a method includes: forming a protruding feature, the protruding feature including: a first sacrificial nanosheet on a bulk semiconductor substrate; a first semiconductor nanosheet on the first sacrificial nanosheet; a second sacrificial nanosheet on the first semiconductor nanosheet; and a second semiconductor nanosheet on the second sacrificial nanosheet; forming a gate stack on the sidewalls and top surface of the protruding feature; etching the protruding feature to form a recess, the first bottom of the recess being lower than the second bottom of the first semiconductor nanosheet; depositing a first dielectric layer in the recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching sidewall portions of the first dielectric layer and the second dielectric layer, leaving a dielectric region at the first bottom of the recess, wherein the dielectric region includes a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer; and forming a source / drain region on the dielectric region.

[0091] In one embodiment, the top surface of the dielectric region is lower than the second bottom of the first semiconductor nanosheet. In one embodiment, the top surface of the dielectric region is flush with the second bottom of the first semiconductor nanosheet. In one embodiment, the method further comprises: performing a pre-cleaning process after the dielectric region is formed, wherein the treatment process causes a first bottom portion of the first dielectric layer to have a lower etching rate during the pre-cleaning process than the first dielectric layer before the treatment process.

[0092] In one embodiment, the treating process is performed using an oxygen-containing process gas. In one embodiment, the method further comprises: removing the first sacrificial nanosheet and the second sacrificial nanosheet; and forming a replacement gate stack, wherein the replacement gate stack includes a portion in a space left by the removed first sacrificial nanosheet and the second sacrificial nanosheet.

[0093] According to some embodiments of the present disclosure, a method includes: etching a semiconductor nanosheet to form a source / drain recess, wherein the source / drain recess includes a first bottom that is lower than a second bottom of the semiconductor nanosheet; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess, and the first dielectric layer includes a first dielectric material; performing a treatment process on the first dielectric layer to convert the first dielectric material into a second dielectric material; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; performing a pre-cleaning process using an etching gas, wherein the etching gas is capable of etching the first dielectric material at a first etching rate and is capable of etching the second dielectric material at a second etching rate, and wherein the second etching rate is lower than the first etching rate; and growing a semiconductor region in the source / drain recess by an epitaxial process.

[0094] In one embodiment, the pre-cleaning process causes the dielectric region to have a concave top surface. In one embodiment, the pre-cleaning process causes the dielectric region to have a convex top surface.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0096] Example

[0097] Example 1. A method for forming a semiconductor structure, comprising: forming a gate stack above a semiconductor region; etching the semiconductor region to form a source / drain recess next to the gate stack; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; and depositing a source / drain region in the source / drain recess and above the dielectric region.

[0098] Example 2. The method of Example 1, wherein depositing the first dielectric layer comprises depositing an oxygen-containing dielectric layer, and depositing the second dielectric layer comprises depositing a nitrogen-containing dielectric layer.

[0099] Example 3. The method of Example 1, wherein the treating process is performed using an oxygen-containing process.

[0100] Example 4. The method of Example 1, wherein the treatment process comprises a plasma treatment process.

[0101] Example 5. The method of Example 1, further comprising: performing a pre-cleaning process after forming the dielectric region and before depositing the source / drain region.

[0102] Example 6. The method of Example 5, wherein the pre-cleaning process is performed using HF gas.

[0103] Example 7. The method of Example 1, wherein the first dielectric layer is deposited using plasma enhanced atomic layer deposition comprising a plurality of cycles, and wherein the treatment process comprises turning on radio frequency power to generate a plasma.

[0104] Example 8. The method of Example 7, wherein depositing the first dielectric layer includes introducing a process gas as a precursor, and wherein the treatment process is also performed using the process gas to generate the plasma.

[0105] Example 9. The method of Example 7, wherein depositing the first dielectric layer includes introducing a first process gas as a precursor, and wherein the treatment process is performed using a second process gas different from the first process gas to generate the plasma.

[0106] Example 10. The method of Example 1, wherein the treatment process is performed using carbon dioxide (CO2) as a process gas.

[0107] Example 11. The method of Example 1, wherein the semiconductor region comprises a semiconductor nanosheet, wherein the semiconductor nanosheet is included in a protruding feature comprising an additional semiconductor nanosheet stacked on the semiconductor nanosheet.

[0108] Example 12. A method for forming a semiconductor structure, comprising: forming a protruding feature, the protruding feature comprising: a first sacrificial nanosheet on a bulk semiconductor substrate; a first semiconductor nanosheet on the first sacrificial nanosheet; a second sacrificial nanosheet on the first semiconductor nanosheet; and a second semiconductor nanosheet on the second sacrificial nanosheet; forming a gate stack on the sidewalls and top surface of the protruding feature; etching the protruding feature to form a recess, wherein a first bottom of the recess is lower than a second bottom of the first semiconductor nanosheet; depositing a first dielectric layer in the recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching sidewall portions of the first dielectric layer and the second dielectric layer, leaving a dielectric region at the first bottom of the recess, wherein the dielectric region includes a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer; and forming a source / drain region on the dielectric region.

[0109] Example 13. The method of Example 12, wherein a top surface of the dielectric region is lower than a second bottom portion of the first semiconductor nanosheet.

[0110] Example 14. The method of Example 12, wherein a top surface of the dielectric region is flush with a second bottom portion of the first semiconductor nanosheet.

[0111] Example 15. The method according to Example 12 further includes: performing a pre-cleaning process after forming the dielectric region, wherein the treatment process causes the first bottom portion of the first dielectric layer to have a lower etching rate during the pre-cleaning process than the first dielectric layer before the treatment process.

[0112] Example 16. The method of Example 12, wherein the treating process is performed using an oxygen-containing process gas.

[0113] Example 17. The method according to Example 12 also includes: removing the first sacrificial nanosheet and the second sacrificial nanosheet; and forming a replacement gate stack, wherein the replacement gate stack includes a portion of the space left by the removed first sacrificial nanosheet and the second sacrificial nanosheet.

[0114] Example 18. A method for forming a semiconductor structure, comprising: etching a semiconductor nanosheet to form a source / drain recess, wherein the source / drain recess includes a first bottom that is lower than a second bottom of the semiconductor nanosheet; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess and the first dielectric layer includes a first dielectric material; performing a treatment process on the first dielectric layer to convert the first dielectric material into a second dielectric material; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; performing a pre-cleaning process using an etching gas, wherein the etching gas is capable of etching the first dielectric material at a first etching rate and is capable of etching the second dielectric material at a second etching rate, and wherein the second etching rate is lower than the first etching rate; and growing a semiconductor region in the source / drain recess by an epitaxial process.

[0115] Example 19. The method of Example 18, wherein the pre-cleaning process causes the dielectric region to have a concave top surface.

[0116] Example 20. The method of Example 18, wherein the pre-cleaning process causes the dielectric region to have a convex top surface.

Claims

1. A method for forming a semiconductor structure, comprising: forming a gate stack over the semiconductor region; etching the semiconductor region to form source / drain recesses next to the gate stack; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; and Source / drain regions are deposited in the source / drain recesses and over the dielectric region.

2. The method according to claim 1, wherein: Depositing the first dielectric layer includes depositing an oxygen-containing dielectric layer, and depositing the second dielectric layer includes depositing a nitrogen-containing dielectric layer.

3. The method according to claim 1, wherein: The treatment process is performed using an oxygen-containing process.

4. The method according to claim 1, wherein: The treatment process includes a plasma treatment process.

5. The method according to claim 1, further comprising: After forming the dielectric region and before depositing the source / drain regions, a pre-clean process is performed.

6. The method according to claim 5, wherein: The pre-cleaning process is performed using HF gas.

7. The method according to claim 1, wherein: The first dielectric layer is deposited using plasma enhanced atomic layer deposition including a plurality of cycles, and wherein the treatment process includes turning on radio frequency power to generate a plasma.

8. The method according to claim 7, wherein: Depositing the first dielectric layer includes introducing a process gas as a precursor, and wherein the treatment process is also performed using the process gas to generate the plasma.

9. A method for forming a semiconductor structure, comprising: Prominent features are formed, the prominent features comprising: a first sacrificial nanosheet on a bulk semiconductor substrate; a first semiconductor nanosheet on the first sacrificial nanosheet; a second sacrificial nanosheet on the first semiconductor nanosheet; and a second semiconductor nanosheet on the second sacrificial nanosheet; forming a gate stack on sidewalls and a top surface of the protruding feature; etching the protruding feature to form a recess, wherein a first bottom of the recess is lower than a second bottom of the first semiconductor nanosheet; depositing a first dielectric layer in the recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching sidewall portions of the first dielectric layer and the second dielectric layer, leaving a dielectric region at a first bottom portion of the recess, wherein the dielectric region includes a first bottom portion of the first dielectric layer and a second bottom portion of the second dielectric layer; and Source / drain regions are formed on the dielectric region.

10. A method for forming a semiconductor structure, comprising: Etching the semiconductor nanosheet to form a source / drain recess, wherein the source / drain recess comprises a first bottom portion, the first bottom portion being lower than a second bottom portion of the semiconductor nanosheet; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess and the first dielectric layer comprises a first dielectric material; performing a treatment process on the first dielectric layer to convert the first dielectric material into a second dielectric material; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, wherein a first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain recess to form a dielectric region; performing a pre-cleaning process using an etching gas, wherein the etching gas is capable of etching the first dielectric material at a first etching rate and is capable of etching the second dielectric material at a second etching rate, and wherein the second etching rate is lower than the first etching rate; and A semiconductor region is grown in the source / drain recesses by an epitaxial process.

Images