Power semiconductor device

Abstract

The invention provides a power semiconductor device, a power semiconductor module including the same, a power converter, and a manufacturing method. The power semiconductor device may include a substrate, a first conductive type epitaxial layer disposed on the substrate, and a stepped well structure, in which a lower region of the stepped well structure is narrower than an upper region but wider than an insulating region or a trench region.

Description

Technical Field

[0001] Embodiments relate to semiconductor devices and manufacturing, and in particular, to a power semiconductor module and a power converter including the same. Background Art

[0002] Power semiconductors are one of the key factors in determining the efficiency, speed, durability and reliability of power electronic systems.

[0003] With the recent development of the power electronics industry, since the previously used silicon (Si) power semiconductors have reached their physical limits, research on replacing Si power semiconductors with WBG (Wide Bandgap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) is being actively conducted.

[0004] The band gap energy of WBG power semiconductor devices is approximately three times that of Si power semiconductor devices, resulting in low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation rate (approximately 2 to 2.5 times).

[0005] Due to these characteristics, it can operate in high temperature, high voltage environment, and has high switching speed and low switching loss. Among them, gallium nitride (GaN) power semiconductor devices can be used in low voltage systems, while silicon carbide (SiC) power semiconductor devices can be used in high voltage systems.

[0006] The SiC MOSFET of the power semiconductor device can be expressed as a VDMOSFET (Vertical Diffused MOSFET) with a vertical diffusion structure, or can be simply expressed as a DMOSFET (Double Diffused MOSFET) with a double diffusion structure. Moreover, the SiC MOSFET can be classified into a planar MOSFET and a trench MOSFET according to the channel direction.

[0007] However, there remains a need for improved power semiconductor devices, circuits or other modules incorporating power semiconductor devices, and methods of manufacturing power semiconductor devices. Summary of the invention

[0008] For example, the prior art SiC VDMOSFET includes a shallow P-well structure to facilitate manufacturing in a production line that can ensure withstand voltage. Compared with a deep P-well structure, the shallow P-well structure has the advantages of reducing R JFETThe JFET refers to a pair of P-well region gaps located below the gate electrode. On the other hand, in MOSFET devices used for power semiconductors with high-power switching functions, the robustness of the MOSFET device increases as the short-circuit withstand time (SCWT) of the MOSFET device increases. SCWT refers to the time that the MOSFET device can operate reliably when exposed to a short-circuit current.

[0009] However, compared with Si MOSFET, the conventional SiC VDMOSFET shows superiority in electrical characteristics due to high breakdown voltage and low Ron characteristics, but the SCWT of the conventional SiC VDMOSFET is relatively short, so the robustness of the conventional SiC VDMOSFET is weak.

[0010] The embodiments described herein may address one or more of these challenges. According to some embodiments, a power semiconductor device that addresses the problem of SCWT short, a power semiconductor module including the power semiconductor device, and a power converter are provided.

[0011] A power semiconductor device according to an embodiment may have a substrate and a stepped well.

[0012] The stepped well may have a first region, a second region, and an insulating layer in the first region.

[0013] The first region may have a width W1 , the second region may have a width W3 , and the width W1 may be greater than the width W3 .

[0014] The second region may be located below the first region.

[0015] The insulating layer may be a buried insulating layer having a width W2, and the width W3 may be greater than the width W2.

[0016] Additionally, embodiments may have a source region.

[0017] The source region may have a first portion and a second portion.

[0018] The first portion and the second portion of the source region may be separated by an insulating layer.

[0019] At least the second region of the stepped well may be formed in the first conductivity type epitaxial layer on the substrate.

[0020] Both the first region and the second region of the stepped well may have the second conductivity type, and the source region may have the first conductivity type.

[0021] At least one of the substrate or the epitaxial layer may include silicon carbide (SiC).

[0022] The doping concentration of the second region of the stepped well may be less than or equal to the doping concentration of the first region of the stepped well.

[0023] Additionally, embodiments may have a gate insulating layer disposed on the stepped well, a gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate, and a source electrode disposed on a source region of the device.

[0024] Additionally, embodiments may have an ion implantation region disposed on at least one side of the stepped well.

[0025] The width of the contact region of the source electrode may be greater than the width of the ion implantation region.

[0026] A contact region of the source electrode may be in contact with the source region and the ion implantation region.

[0027] Additionally, embodiments may have multiple stepped wells.

[0028] A first stepped well among the plurality of stepped wells may be separated from a second stepped well among the plurality of stepped wells by an ion implantation region.

[0029] A power converter according to an embodiment may have at least one power semiconductor device as described above.

[0030] According to an embodiment, a method for manufacturing a semiconductor device may have the following steps: forming a first epitaxial layer and a first well on a substrate, wherein the first epitaxial layer has a first conductivity type and the first well has a second conductivity type; forming a source region in the first well, wherein the source region has the first conductivity type; forming an ion implantation region in the first well and passing through the source region, wherein the ion implantation region has the second conductivity type and extends deeper into the first well than the source region; forming one or more junction field effect (JFET) regions on either side of the ion implantation region; forming a trench in the first well; and forming a stepped well structure, the stepped well structure comprising a first well and a second well below the first well.

[0031] Furthermore, embodiments may have the step of applying an insulating layer in the trenches.

[0032] Forming the stepped well structure may have the step of performing ion implantation on the bottom of the trench to generate the second well.

[0033] Forming the stepped well structure may have the steps of performing a plurality of ion implantation steps and performing an activation process.

[0034] The performing a plurality of ion implantation steps may include performing ion implantation on each of four side surfaces of the trench while being tilted and rotated by 90°, and performing at least one ion implantation on the bottom surface.

[0035] The concentration of the second conductive type dopant in the second well may be equal to or less than the concentration of the second conductive type dopant in the first well.

[0036] The width of the second well may be smaller than the width of the first well in the stepped well structure.

[0037] Forming the trench may create a first portion of the source region and a second portion of the source region, an insulating layer may be applied between the first portion and the second portion, and the first epitaxial layer in the region below the first well may not be exposed by formation of the trench.

[0038] The power semiconductor device, the power semiconductor module, and the power converter including the power semiconductor module according to the embodiment have the technical effect of improving SCWT characteristics while minimizing the increase of Ron by designing the stepped second conductive type well 130 positioned deeply.

[0039] For example, according to an embodiment, the stepped second conductive type well 130 may include a second conductive type second-first well 131 disposed on the upper side and a second conductive type second-second well 132 disposed on the lower side. In this case, the width of the second conductive type second-second well 132 disposed on the lower side may be controlled to be smaller than the width of the second conductive type second-first well 131 disposed on the upper side. Therefore, the JFET region may be designed to be further spaced apart in the depth direction of the substrate. Therefore, there is a possibility of preventing R by maintaining a high withstand voltage characteristic. JFET The increase in Ron characteristics can improve the special technical effect of the loss.

[0040] In addition, according to the embodiment, by including the stepped second conductive type well 130 of the second conductive type second-second well 132 positioned deeper, the physical distance between the channel and the bottom surface of the second conductive type well 130 can be increased, so that the electric field concentration in the channel can be reduced. Therefore, there is a technical effect of reducing the channel resistance by improving the short channel effect.

[0041] In addition, according to an embodiment, the stepped second conductive type well 130 may include a second conductive type second-first well 131 and a second conductive type second-second well 132 arranged thereunder with a narrow width, which has a special technical effect of enhancing the SCWT characteristics by designing the second conductive type second-second well 132 to be positioned deeper.

[0042] In this way, the embodiments have a special technical effect of being able to provide a power semiconductor device capable of improving robustness by enhancing SCWT characteristics, a power semiconductor module including the power semiconductor device, and a power converter.

[0043] The technical effects of the embodiments are not limited to those described in this section, but include technical effects that can be understood through the description of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate various non-limiting embodiments of the present invention.In the drawings, like reference numbers indicate identical or functionally similar elements.

[0045] Figure 1 A power converter according to an embodiment is illustrated.

[0046] Figure 2 A cross-sectional view of a power semiconductor device according to an embodiment is illustrated.

[0047] Figure 3A and Figure 3B A cross-sectional view of a power semiconductor device according to an embodiment is illustrated.

[0048] Figure 4A A plan view of a power semiconductor device according to an embodiment is illustrated.

[0049] Figure 4B A partial cross-sectional view of a power semiconductor device according to an embodiment is illustrated.

[0050] FIG. 5A to FIG. 5I A cross-sectional view illustrating a manufacturing process of a power semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0051] Hereinafter, embodiments are described in detail with reference to the accompanying drawings.

[0052] The suffixes "module" and "unit" of the elements used in the following description are given only in consideration of ease of writing this specification, and they themselves do not give particularly important meanings or roles. Therefore, "module" and "unit" can be used interchangeably.

[0053] Terms including ordinal numbers (such as first and second) may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.

[0054] Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0055] In the present application, terms such as “includes,” “has,” or “comprising” are intended to specify the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, without excluding one or more other features, quantities, steps, operations, components, parts, or combinations thereof, or any combination thereof.

[0056] Now refer to Figure 1 According to one or more embodiments, a power converter 1000 is provided.

[0057] The power converter 1000 according to the embodiment may receive DC power from a battery or a fuel cell, convert the DC power into AC power, and supply the AC power to a predetermined load. For example, the power converter 1000 according to the embodiment may include an inverter that receives DC power from a battery, converts the DC power into 3-phase AC power, and supplies the 3-phase AC power to the motor M. In some aspects, the motor M may provide power to an electric vehicle or a fuel cell vehicle.

[0058] Now refer to Figure 1 According to one or more embodiments, a power converter 1000 is provided.

[0059] The power converter 1000 according to the embodiment may include one or more power semiconductor devices 100. The power semiconductor device 100 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), but is not limited thereto. For example, in some embodiments, it may be an insulated gate bipolar transistor (IGBT). According to the embodiment, MOSFETs such as SiCMOSFETs may have various structures. Examples include trench structure MOSFETs, vertical double injection structure MOSFETs (DIMOSFETs), or lateral diffusion structure MOSFETs, etc.

[0060] In some embodiments, the power converter 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f. The power converter 1000 may also have a plurality of diodes (not shown). In some aspects, each of the plurality of diodes may be internally incorporated into each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and each of the plurality of diodes may be provided separately.

[0061] exist Figure 1In the example of , DC power can be converted into AC power by on / off control of the plurality of power semiconductor devices 100a to 100f. For example, in the power converter 1000 according to the embodiment, during a first period of a cycle, the first power semiconductor device 100a can be turned on and the second power semiconductor device 100b can be turned off to supply positive polarity power to the motor M. In addition, during a second period of a cycle, the first power semiconductor device 100a can be turned off and the second power semiconductor device 100b can be turned on to supply negative polarity power to the motor M.

[0062] A group of power semiconductor devices arranged in series in the high voltage line and the low voltage line on the input side may be referred to as an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b may constitute a first arm, and the third power semiconductor device 100c and the fourth power semiconductor device 100d may constitute a second arm. The fifth power semiconductor device 100e and the sixth power semiconductor device 100f may constitute a third arm.

[0063] In an arm, the upper power semiconductor device and the lower power semiconductor device may be controlled not to be turned on at the same time. For example, in a first arm, the first power semiconductor device 100a and the second power semiconductor device 100b may not be turned on at the same time, but may be turned on and off alternately.

[0064] In some embodiments, each of the power semiconductor devices 100a to 100f can receive high power in a cut-off state. For example, when the second power semiconductor device 100b is cut off while the first power semiconductor device 100a is turned on, the input voltage can be applied to the second power semiconductor device 100b as it is. The voltage input to the second power semiconductor device 100b can be a relatively high voltage, and the withstand voltage of each of the power semiconductor devices 100a to 100f can be designed to have a high level to withstand such a high voltage.

[0065] Additionally, in some aspects, each of the power semiconductor devices 100a to 100f can conduct a high current in an on state. The motor M can be driven with a relatively high current, and the high current can be supplied to the motor M through the on power semiconductor devices.

[0066] The high voltage applied to each of the power semiconductor devices 100a to 100f may result in high switching losses. The high current conducted by the power semiconductor devices 100a to 100f may result in high conduction losses. In order to dissipate the heat generated by such switching losses or conduction losses, the power semiconductor devices 100a to 100f may be packaged as a power semiconductor module including a heat sink.

[0067] In some embodiments, the power semiconductor device 100 may be a silicon carbide (SiC) power semiconductor device. In some aspects, it may operate in a high temperature, high voltage environment and may have high switching speed and low switching loss.

[0068] In some embodiments, the power converter 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0069] For example, you can Figure 1 The plurality of power semiconductor devices 100 a to 100 f shown are packaged into one power semiconductor module, or power semiconductor devices constituting the respective arms may be packaged into one power semiconductor module.

[0070] As another example, Figure 1 The first power semiconductor device 100 a , the second power semiconductor device 100 b , the third power semiconductor device 100 c , the fourth power semiconductor device 100 d , and the fifth power semiconductor device 100 e and the sixth power semiconductor device 100 f are packaged into one power semiconductor module.

[0071] In addition, there may be additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f to increase current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module may be greater than six.

[0072] In addition to the transistor-type power semiconductor devices 100a to 100f, the power converter 1000 according to the embodiment may also include a diode-type power semiconductor device. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor device 100b. In addition, these diodes may be packaged together in a power semiconductor module. In addition, a diode may be arranged in each power semiconductor device in the form of an internal diode.

[0073] In some embodiments, the power semiconductor devices constituting each arm may be packaged into one power semiconductor module. For example, the first power semiconductor device 100a and the second power semiconductor device 100b constituting the first arm may be packaged into a first power semiconductor module. The third power semiconductor device 100c and the fourth power semiconductor device 100d constituting the second arm may be packaged into a second power semiconductor module. The fifth power semiconductor device 100e and the sixth power semiconductor device 100f constituting the third arm may be packaged into a third power semiconductor module.

[0074] In addition, there may be an additional power semiconductor device arranged in parallel with each of the power semiconductor devices 100a to 100f to increase the current capacity. In this case, the number of power semiconductor devices included in each power semiconductor module may be more than two. In addition, in addition to the transistor-type power semiconductor devices 100a to 100f, each arm may also include a diode-type power semiconductor device (not shown), and these diodes may also be packaged together in one power semiconductor module. In addition, the diode may be arranged in each power semiconductor device in the form of an internal diode.

[0075] Figure 2 A cross-sectional view of a power semiconductor device (such as device 100) according to an embodiment is illustrated. In some aspects, the device can be used in, for example, a combination of Figure 1 In a circuit or other module such as the power converter 1000 described above.

[0076] A power semiconductor device 100 such as a MOSFET according to an embodiment may include a source electrode 190 disposed above a semiconductor epitaxial layer 120 , a gate electrode 175 , and a drain electrode 105 disposed below the semiconductor epitaxial layer 120 .

[0077] In an embodiment, the source electrode 190 or the gate electrode 175 may include an Al-based metal, and the drain electrode 105 may include a Ti / Ni / Ag metal (which includes a Ti layer, a Ni layer, or an Ag layer), or NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0078] Figure 3A is a cross-sectional view of a power semiconductor device 100 according to an embodiment, and Figure 3B is based on Figure 3A A detailed cross-sectional view of an example power semiconductor device 100 is shown.

[0079] Figure 4A is a plan view of a power semiconductor device 100 according to an embodiment, and Figure 4B is based on Figure 4AA partial three-dimensional cross-sectional view of a power semiconductor device 100 of the illustrated example is taken along line A1 - A2 .

[0080] Reference Figure 3A The power semiconductor device 100 according to the embodiment may include one or more of the following items: a substrate 110, a first conductive type epitaxial layer 120, a stepped second conductive type well 130, a buried insulating layer 150, a first conductive type source region 140, a gate insulating layer 160, a junction electric field region 122, and a second conductive type ion implantation region 135 (see Figure 4B ), gate 170, interlayer insulating layer 180 and / or source electrode 190.

[0081] According to an embodiment, the stepped second conductive type well 130 may include a second conductive type second-first well 131 and a second conductive type second-second well 132. The first conductive type may be an N type, and the second conductive type may be a P type, but is not limited thereto. In addition, the substrate 110 and the first conductive type epitaxial layer 120 may include silicon carbide (SiC), but are not limited thereto.

[0082] Specifically, refer to Figure 3A According to an embodiment, a power semiconductor device 100 may include: a substrate 110, a first conductive type epitaxial layer 120 disposed on the substrate 110, a stepped second conductive type well 130 disposed on the first conductive type epitaxial layer 120 and a source region 140 disposed to be partially spaced apart from a first region of the stepped second conductive type well 130 and spaced apart from each other, a buried insulating layer 150 disposed in a second region of the second conductive type well 130 between the source regions 140, and a second conductive type ion implantation region 135 disposed on one side of the stepped second conductive type well 130.

[0083] In addition, the power semiconductor device 100 according to the embodiment may include a gate insulating layer 160 disposed on the stepped second conductive type well 130 and a gate 170 disposed on the gate insulating layer 160 , an interlayer insulating layer 180 disposed on the gate 170 , and a source electrode 190 disposed on the source region 140 .

[0084] Due to the nature of the material, it may be difficult to implant ions into SiC (silicon carbide) that may be employed in some embodiments. For example, to form a p-well of about 1 μm, the ion implantation must be performed at an energy of at least about 650 keV. Therefore, there are technical difficulties in the mass production process of forming a well having a depth of 2 μm to 3 μm by ion implantation.

[0085] However, one or more embodiments described herein may provide a power semiconductor device that solves these technical difficulties. According to some embodiments, a second conductive type second-first well 131 may be formed, and a portion of the second conductive type second-first well 131 may be removed to form a trench structure.

[0086] In addition, the second conductive type second-second well 132 may be formed by using ion implantation with a trench structure so that a stepped second conductive type well 130 may be formed. Therefore, the power semiconductor device according to the embodiment may enhance SCWT characteristics through the stepped second conductive type well 130.

[0087] Reference Figure 3B The stepped second conductive type well 130 may include: a second conductive type second-first well 131 having a first width W1, and a second conductive type second-second well 132 having a third width W3 narrower than the first width W1, the second conductive type second-second well being disposed below the second conductive type second-first well 131.

[0088] In addition, the buried insulating layer 150 may be disposed in a region of the second conductive type well 130 between the source regions 140 , and may have a second width W2 that is smaller than a third width W3 of the second conductive type second-second well 132 .

[0089] Therefore, according to the embodiment, since the stepped second conductive type well 130 may include the second conductive type second-first well 131 having the first width W1, and the second conductive type second-second well 132 having the third width W3 smaller than the first width W1 and disposed below the second conductive type second-first well, there is a technical effect that the SCWT characteristic can be enhanced. In the internal technology, the SCWT of the VDMOSFET is about the 2.4μs level, and when the present invention according to the embodiment is applied, the SCWT has been significantly improved to about the 6.8μs level.

[0090] In particular, since the third width of the second conductive type second-second well 132 disposed on the lower side can be controlled to be smaller than the width of the second conductive type second-first well 131 disposed on the upper side, the JFET region can be designed to be further spaced apart in the depth direction of the substrate. JFET The increase in Ron characteristics can improve the special technical effect of the loss.

[0091] For example, the spacing between a pair of second-conductivity type second-second wells 132 (about twice the size of JW2) can be controlled to be wider than the spacing between a pair of second-conductivity type second-first wells 131 (about twice the size of JW1).JFET The addition of Ron's special technical effects improves the special technical effects of Ron's characteristics.

[0092] Next, Figure 4A is a plan view of a power semiconductor device 100 according to an embodiment, and Figure 4B is based on Figure 4A A partial three-dimensional cross-sectional view of the power semiconductor device 100 of the illustrated example is taken along line A1 - A2 (the buried insulating layer 150 is omitted).

[0093] Reference Figure 4A and Figure 4B According to an embodiment, a power semiconductor device 100 may include: a substrate 110, a first conductive type epitaxial layer 120 disposed on the substrate 110 and a stepped second conductive type well 130 disposed on the epitaxial layer 120, a source region 140 disposed at a first area of ​​the stepped second conductive type well 130 and partially spaced apart, a buried insulating layer 150 disposed in the second conductive type well 130 and between the spaced apart source regions 140, and a second conductive type ion implantation region 135 disposed on one side of the stepped second conductive type well 130.

[0094] Reference Figure 4B , the power semiconductor device 100 according to the embodiment may include: a source electrode 190 disposed on the source region 140 and the second conductive type ion implantation region 135. The horizontal width Ws of the contact region 190C of the source electrode may be greater than the horizontal width of the second conductive type ion implantation region 135, and the contact region 190C may be in contact with the source region 140 and the second conductive type ion implantation region 135.

[0095] Reference Figure 4B In an embodiment, the width of the second conductive type second-second well 132 disposed at the lower side may be controlled to be smaller than the width of the second conductive type second-first well 131 disposed at the upper side. By designing the JFET region to be further spaced apart in the depth direction of the substrate, it is possible to maintain high withstand voltage characteristics and prevent R JFET The special technical effect of increasing the loss of Ron characteristics is improved.

[0096] In addition, according to an embodiment, the stepped second conductive type well 130 including the second conductive type second-first well 131 and the second conductive type second-second well 132 arranged with a narrow width may be formed deeply.

[0097] There is a special technical effect that the SCWT characteristic can be enhanced by controlling the second conductive type second-second well 132 to be positioned deeper. In this way, the embodiment has a special technical effect that a power semiconductor device, a power semiconductor module, and a power converter can be provided that can improve robustness by enhancing the short circuit withstand time (SCWT) characteristic.

[0098] Next, we will refer to FIG. 5A to FIG. 5I A manufacturing process of the power semiconductor device 100 according to the embodiment will be described.

[0099] Reference Figure 5A , a substrate 110 including a first conductive type epitaxial layer 120 may be prepared, and a second conductive type second-first well 131 may be formed on the first conductive type epitaxial layer 120 .

[0100] The substrate 110 and the first conductive type epitaxial layer 120 may include 4H-SiC material, but are not limited thereto. For example, the substrate 110 and the first conductive type epitaxial layer 120 may include 3C-SiC or 6H-SiC. The first conductive type epitaxial layer 120 may be an N-type drift region, but is not limited thereto.

[0101] The second conductive type second-first well 131 may be formed using a concentration of about 1×10 16 cm -3 About 1×10 19 cm -3 Ion implantation may be performed using a P-type dopant. For example, Al or boron may be implanted, but is not limited thereto.

[0102] Next, refer to Figure 5B , a first conductive type source region 140 may be formed in the second conductive type second-first well 131. For example, by 17 cm -3 About 2×10 20 cm -3 N-type dopants such as nitrogen or phosphorus are ion-implanted at a concentration of 1000 Å to form the first conductive type source region 140 .

[0103] Next, refer to Figure 5C , a second conductive type ion implantation region 135 may be formed. For example, Al or boron may be implanted into the second conductive type second-first well 131 at a deeper position through the first conductive type source region 140 to form the second conductive type ion implantation region 135.

[0104] Next, refer to Figure 5D, a junction electric field region 122 may be formed on both sides of the second conductive type ion implantation region 135. The junction electric field region 122 may be referred to as a JFET region. The junction electric field region 122 may be formed by ion implantation of a P-type dopant such as phosphorus, and may improve the characteristics of Vth, saturation current, and on-resistance.

[0105] Reference Figure 5E , a trench T may be formed in the second conductivity type second-first well 131. For example, the trench T may be formed by etching to remove the source region 140, the second conductivity type ion implantation region 135, and a portion of the second conductivity type second-first well 131. The first conductivity type epitaxial layer 120 may not be exposed by the trench T.

[0106] Next, refer to Fig. 5F and Figure 5G ( Figure 5G yes Fig. 5F ), a second conductive type second-second well 132 may be formed on the bottom and sidewalls of the trench T by an ion implantation process to form a step difference, so that a stepped second conductive type well 130 may be manufactured.

[0107] For example, the stepped second conductive type well 130 may be formed by forming the second conductive type second-second well 132 on the sidewall and bottom of the trench T of the second conductive type second-first well 131 through ion implantation. For example, the second conductive type second-second well 132 may be formed through an activation process after four ion implantations are performed on four side surfaces tilted and rotated 90°, respectively, and one ion implantation is performed on the bottom surface.

[0108] In addition, according to the embodiment, since the width of the second conductive type second-second well 132 is controlled to be smaller than the width of the second conductive type second-first well 131, there is a special technical effect that the JFET region is controlled to be further spaced apart in the depth direction of the substrate, and the high withstand voltage characteristic is maintained to prevent R JFET The increase in Ron characteristics can improve the loss.

[0109] Next, refer to Figure 5H , a buried insulating layer 150 may be formed in the second conductive type well 130 between the source regions 140 separated by the trenches. The buried insulating layer 150 may be formed of oxide or nitride.

[0110] Next, refer to Fig.5I A gate insulating layer 160 may be formed on the stepped second conductive type well 130, a gate 170 may be formed on the gate insulating layer 160, an interlayer insulating layer 180 may be formed on the gate 170, and a source electrode 190 may be formed on the source region 140 after partially opening the interlayer insulating layer 180.

[0111] The gate insulating layer 160 may be a thermal oxide layer or a deposited oxide layer, but is not limited thereto. The gate 170 may be formed of polysilicon, but is not limited thereto. The interlayer insulating layer 180 may be formed of an oxide film or a nitride film, but is not limited thereto. The source electrode 190 may be formed of Al or the like, but is not limited thereto.

[0112] According to the power semiconductor device, the power semiconductor module, and the power converter including the power semiconductor module of the embodiment, by designing the stepped second conductive type well 130 to be positioned deeper, there is a technical effect of improving SCWT characteristics while minimizing Ron increase.

[0113] The design and manufacture of power semiconductor devices can present competing and often conflicting challenges for optimal performance.

[0114] For example, as described above, as SCWT (short circuit withstand time) increases, a MOSFET device used for a power semiconductor having a high power switching function may have higher robustness.

[0115] However, SiCVD MOSFETs (for example) that employ a shallow P-well structure to facilitate manufacturing in a production line that can ensure withstand voltage may see the robustness of the power semiconductor device weakened due to the shortening of SCWT.

[0116] One of the technical objectives of the embodiments described herein is to provide a power semiconductor device and a power converter including the power semiconductor device that solve this problem. One method of solving this problem is to design a stepped second conductivity type well that is positioned deeper.

[0117] According to some embodiments, the stepped second conductive type well 130 may include a second conductive type second-first well 131 disposed on the upper side and a second conductive type second-second well 132 disposed on the lower side. In this case, the width of the second conductive type second-second well 132 disposed on the lower side may be controlled to be smaller than the width of the second conductive type second-first well 131 disposed on the upper side. Therefore, the JFET region may be designed to be further spaced apart in the depth direction of the substrate. Therefore, there is a possibility of preventing R by maintaining a high withstand voltage characteristic. JFET The increase in Ron characteristics can improve the special technical effect of the loss.

[0118] According to some embodiments, a power semiconductor device is provided, which may include a substrate, a first conductive type epitaxial layer disposed on the substrate, a stepped second conductive type well disposed on the first conductive type epitaxial layer, a source region partially spaced apart from a first region of the stepped second conductive type well, a buried insulating layer disposed in a second region of the second conductive type well between the spaced apart source regions, a gate insulating layer disposed on the stepped second conductive type well, a gate disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate insulating layer, and a source electrode disposed on the source region.

[0119] In some aspects, the stepped second conductivity type well may include: a second conductivity type second-first well having a first width, and a second conductivity type second-second well having a third width narrower than the first width, the second conductivity type second-second well being disposed below the second conductivity type second-first well.

[0120] A buried insulating layer may be disposed in a region of the second conductive type well between the spaced-apart source regions.

[0121] The horizontal width of the buried insulating layer may be a second width that is smaller than a third width of the second conductive type second-second well.

[0122] The doping concentration of the second-conductivity type second-second well may be equal to or less than the doping concentration of the second-conductivity type second-first well.

[0123] Furthermore, the power semiconductor device according to the embodiment may include a second conductive type ion implantation region disposed on one side of the stepped second conductive type well.

[0124] The horizontal width of the contact region of the source electrode may be greater than the horizontal width of the second conductive type ion implantation region.

[0125] The contact region of the source electrode may be in contact with the source region and the second conductive type ion implantation region.

[0126] A power converter according to an embodiment may include at least one of the power semiconductor devices described above.

[0127] In addition, according to an embodiment, the stepped second conductive type well 130 may include a second conductive type second-first well 131 and a second conductive type second-second well 132 arranged thereunder with a narrow width, which has a special technical effect of enhancing the SCWT characteristics by designing the second conductive type second-second well 132 to be positioned deeper.

[0128] Although various aspects are described herein, it should be understood that they are presented by way of example only, not limitation. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above exemplary aspects. Moreover, unless otherwise specified herein or clearly contradictory to the context, the present disclosure encompasses any combination of the above elements in all possible variations thereof.

[0129] In addition, although the above process is described as a sequence of steps, this is done for the purpose of description only. Therefore, it is expected that some steps can be added, some steps can be omitted, the order of the steps can be rearranged, and some steps can be performed in parallel.

Claims

1. A power semiconductor device, comprising: substrate; as well as A stepped well, wherein the stepped well includes a first region, a second region, and an insulating layer in the first region.

2. The power semiconductor device according to claim 1, wherein: The first region has a width W1 , the second region has a width W3 , and the width W1 is greater than the width W3 .

3. The power semiconductor device according to claim 2, wherein: The second area is located below the first area.

4. The power semiconductor device according to claim 3, wherein: The insulating layer is a buried insulating layer having a width W2, and the width W3 is greater than the width W2.

5. The power semiconductor device according to claim 1, further comprising: A source region, wherein the source region includes a first portion and a second portion, and wherein the first portion and the second portion of the source region are separated by the insulating layer.

6. The power semiconductor device according to claim 5, wherein: (i) at least the second region of the stepped well is formed in a first conductivity type epitaxial layer on the substrate, (ii) both the first region and the second region of the stepped well have the second conductivity type, and (iii) The source region has the first conductivity type.

7. The power semiconductor device according to claim 6, wherein: At least one of the substrate or the epitaxial layer includes silicon carbide (SiC).

8. The power semiconductor device according to claim 1, wherein: The doping concentration of the second region of the stepped well is less than or equal to the doping concentration of the first region of the stepped well.

9. The power semiconductor device according to claim 1, further comprising: a gate insulating layer, the gate insulating layer being disposed on the stepped well; a gate, the gate being disposed on the gate insulating layer; an interlayer insulating layer, wherein the interlayer insulating layer is disposed on the gate; as well as A source electrode is disposed on a source region of the power semiconductor device.

10. The power semiconductor device according to claim 9, further comprising: an ion implantation region, the ion implantation region being disposed on at least one side of the stepped well, The width of the contact region of the source electrode is greater than the width of the ion implantation region, and the contact region of the source electrode is in contact with the source region and the ion implantation region.

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