Terminal structure of power device, manufacturing method and chip

Abstract

The embodiment of the present application provides a terminal structure of a power device, a manufacturing method and a chip, the terminal structure comprises: an N-type substrate; a junction terminal extension region, a junction grading doping region and a plurality of field limiting rings arranged on the N-type substrate, the junction terminal extension region is connected with the junction grading doping region, the depth of the junction grading doping region gradually decreases in the direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction grading doping region away from the junction terminal extension region, and the distance between the plurality of field limiting rings and the junction grading doping region gradually increases; the junction terminal extension region, the junction grading doping region and the plurality of field limiting rings are doped with P-type ions; a groove arranged on the N-type substrate, the groove is arranged on the side of the farthest field limiting ring from the junction grading doping region away from the junction grading doping region. Through the composite terminal structure comprising the junction terminal extension region, the junction grading doping region, the plurality of field limiting rings, the groove and the polysilicon field plate, the maximum electric field intensity of the chip can be effectively reduced, and the withstand voltage performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a terminal structure of a power device, a manufacturing method and a chip. BACKGROUND

[0002] Modern power devices (such as MOSFET, IGBT, etc.) are usually composed of thousands of identical cells in parallel, each cell is a small power device, these cells are connected in parallel to improve the total current handling capability of the device, and the surface voltage of each cell is approximately the same because they share the same voltage source and load. In a power device, the voltage difference between the terminal cell (the cell near the edge of the device) and the substrate (the bottom layer of the device) can be large, because the terminal cell needs to withstand a higher voltage to prevent breakdown caused by electric field concentration. This voltage difference can cause electric field concentration in the terminal region, affecting the withstand voltage capability of the device. In order to improve the withstand voltage capability of the device, measures need to be taken to reduce the surface electric field, which is usually achieved by optimizing the terminal structure, such as using field limiting ring (FLR) technology, etc. Field limiting ring can introduce additional doped regions in the terminal region to disperse the electric field and prevent breakdown caused by electric field concentration. Modern silicon power devices usually adopt shallow planar structure, which can improve the withstand voltage capability of the device. In the design of field limiting ring, field limiting ring is often used to reduce the surface electric field concentration caused by junction curvature effect, thereby improving the breakdown voltage. Although field limiting ring can improve the breakdown voltage, they also significantly increase the chip area, because field limiting ring needs to introduce additional doped regions in the terminal region, which occupies part of the chip area. The peak electric field may occur at the junction corner (i.e. the corner of the doped region) of the planar field limiting ring. This peak electric field can cause the breakdown characteristics of the device to degrade, because the electric field concentration increases the risk of breakdown. In order to further increase the junction depth (i.e. the depth of the doped region) and reduce the peak electric field at the junction corner, a trench field limiting ring (TFLR) terminal structure can be used, which further disperses the electric field and reduces the peak electric field by introducing a trench structure in the terminal region. Although the trench field limiting ring can reduce the peak electric field, they also increase the expansion capability of the field limiting ring terminal lateral space charge region, which means that the terminal region needs a larger area to accommodate these expanded space charge regions, resulting in an increase in terminal area.

[0003] In a power device, the main junction ring refers to the main PN junction or Schottky junction of the device. In order to improve the withstand voltage capability of the device, the surface of the main junction ring is usually subjected to high-dose doping injection. The injection dose is usually 1e12-1e15 / cm 2The order of magnitude of the doping intensity. High-dose doping implantation leads to an increase in the surface electric field intensity of the main junction ring. Since the electric field concentration effect is more pronounced at the corners of the main junction ring (i.e., the corners of the doped regions), breakdown typically occurs at these corners. This means that the electric field intensity at the corners of the main junction is the highest, making them prone to breakdown. In actual production, the implantation dose may be affected by deviations in the production line equipment. This deviation can lead to uneven implantation dose, thus affecting device performance and reliability. JTE (Junction Termination Extension) is a termination protection technology used to improve the breakdown voltage capability of devices. The JTE structure disperses the electric field by introducing an additional doped region in the termination region, preventing breakdown caused by electric field concentration. However, if the implantation dose deviation results in a low doping concentration in the JTE structure, the effectiveness of the JTE structure will be affected. If the doping concentration of the JTE structure is low, the electric field distribution will be uneven, causing breakdown to occur at the JTE lateral junction termination extension structure. This means that the JTE structure fails to effectively disperse the electric field and instead becomes the location of breakdown. Because of the low doping concentration in the JTE structure, breakdown occurs at the JTE structure itself, resulting in poor terminal reliability and insufficient withstand voltage. This means that the device is prone to failure under high voltage or high temperature environments, affecting the system's stability and lifespan. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a power device terminal structure, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0005] To address the aforementioned problems, embodiments of the present invention disclose a termination structure for a power device, the termination structure comprising:

[0006] N-type substrate;

[0007] The N-type substrate includes a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings. The junction termination extension region is connected to the junction gradient doped region. The depth of the junction gradient doped region gradually decreases away from the junction termination extension region. The multiple field-limiting rings are located at the end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases. P-type ions are doped within the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings.

[0008] A trench is provided on the N-type substrate, the trench being located on the side of the field limiting ring furthest from the junction graded doping region; polysilicon is deposited in the trench;

[0009] A P-well region and a cutoff ring N+ region are disposed on the N-type substrate. The P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is disposed on the side of the trench away from the field limiting ring.

[0010] An oxide layer disposed on the surface of the N-type substrate;

[0011] A polycrystalline silicon field plate is disposed on the surface of the target region of the oxide layer, wherein the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings;

[0012] A metal layer disposed on the surface of the P-well region, the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, the surface of the N+ region of the stop ring, and the surface of a portion of the oxide layer near the N+ region of the stop ring.

[0013] Optionally, the N-type substrate is an N-type substrate, and the terminal structure further includes:

[0014] An N+ type buffer layer is formed on the other side of the N-type substrate;

[0015] A P+ type collector region is formed on the N+ type buffer layer;

[0016] The collector electrode formed on the P+ type collector region.

[0017] Optionally, the width range of each field limiting ring is 5-12µm.

[0018] Optionally, the depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

[0019] Optionally, the thickness of the metal layer ranges from 3 to 5 μm.

[0020] Accordingly, embodiments of the present invention disclose a method for manufacturing a termination structure of a power device, used to manufacture the termination structure of the power device as described above, the method comprising:

[0021] Provide N-type substrates;

[0022] A junction termination extension region, a junction gradient doped region, and multiple field confinement rings are formed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region, the depth of the junction gradient doped region gradually decreases along the direction away from the junction termination extension region, and the multiple field confinement rings are disposed at one end of the junction gradient doped region away from the junction termination extension region.

[0023] In the N-type substrate, a trench is formed, the trench being located on the side of the field limiting ring furthest from the junction graded doped region.

[0024] depositing polysilicon in the trench;

[0025] forming a P-well region and a cutoff ring N+ region on the N-type substrate; the P-well region is connected with the junction terminal extension region, and the cutoff ring N+ region is arranged on a side of the trench away from the field limiting ring;

[0026] growing an oxide layer on the surface of the N-type substrate,

[0027] removing the oxide layer corresponding to the surface of the P-well region, the central region of the plurality of field limiting rings, and the cutoff ring N+ region;

[0028] generating a polysilicon field plate on the surface of a target region of the oxide layer; the target region is a region covering a preset width of the edge of the plurality of field limiting rings;

[0029] generating a metal layer on the surface of the P-well region, the surface of a partial region of the junction terminal extension region close to the P-well region, the plurality of field limiting rings, the surface of the cutoff ring N+ region, and the surface of a partial region of the oxide layer close to the cutoff ring N+ region.

[0030] Optionally, the N-type substrate is an N- type substrate, and the method further comprises:

[0031] back-thinning the N- type substrate on the other side of the N- type substrate;

[0032] high-concentration N-type doping is performed on the other side of the N- type substrate to form an N+ type buffer layer;

[0033] high-concentration P-type doping is performed on the N+ type buffer layer to form a P+ type collector region;

[0034] a metal layer is deposited on the P+ type collector region to form a collector electrode.

[0035] Optionally, the plurality of field limiting rings gradually increase in distance relative to the junction graded doping region; the junction terminal extension region, the junction graded doping region, and the plurality of field limiting rings are doped with P-type ions; and the width interval of each field limiting ring is 5-12 um.

[0036] Optionally, the coverage range covering the edges of the plurality of field limiting rings is 0.5-1.5 um.

[0037] Optionally, the depth of the trench ranges from 4 um to 6 um, and the width of the trench ranges from 0.6 um to 2 um.

[0038] Optionally, the thickness of the metal layer ranges from 3 um to 5 um.

[0039] Correspondingly, the embodiment of the present application discloses a chip comprising the terminal structure of the power device.

[0040] The embodiment of the present application comprises the following advantages:

[0041] The terminal structure of the power device comprises an N-type substrate, a junction terminal extension region, a junction grading doping region and a plurality of field limiting rings arranged on the N-type substrate, the junction terminal extension region is connected with the junction grading doping region, the depth of the junction grading doping region gradually decreases in the direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction grading doping region away from the junction terminal extension region, and the distance of the plurality of field limiting rings to the junction grading doping region gradually increases; P-type ions are doped in the junction terminal extension region, the junction grading doping region and the plurality of field limiting rings; a trench is arranged on the N-type substrate, the trench is arranged on the side of the farthest field limiting ring from the junction grading doping region away from the junction grading doping region; polycrystalline silicon is deposited in the trench; a P-well region and a cutoff ring N+ region are arranged on the N-type substrate, the P-well region is connected with the junction terminal extension region, and the cutoff ring N+ region is arranged on the side of the trench away from the field limiting ring; an oxide layer is arranged on the surface of the N-type substrate; a polycrystalline silicon field plate is arranged on the surface of a target region of the oxide layer, the target region is a region covering the edges of the plurality of field limiting rings with a preset width; and a metal layer is arranged on the surface of the P-well region, the surface of the part of the junction terminal extension region close to the P-well region, the upper part of the plurality of field limiting rings, the surface of the cutoff ring N+ region and the surface of the part of the oxide layer close to the cutoff ring N+ region. By the composite terminal structure comprising the junction terminal extension region, the junction grading doping region, the plurality of field limiting rings, the trench and the polycrystalline silicon field plate, the maximum electric field strength of the chip can be effectively reduced, and the voltage withstanding performance of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 FIG. 1 is a schematic diagram of a terminal structure of a power device according to an embodiment of the present application;

[0043] Figure 2 FIG. 2 is a schematic diagram of another terminal structure of a power device according to an embodiment of the present application;

[0044] Figure 3 FIG. 3 is a step flow chart of a manufacturing method of a terminal structure of a power device according to an embodiment of the present application;

[0045] Figure 4 FIG. 4 is a structural diagram of the manufacturing of a terminal structure of a power device according to an embodiment of the present application;

[0046] Figure 5 FIG. 5 is a structural diagram of the manufacturing of another terminal structure of a power device according to an embodiment of the present application;

[0047] Figure 6 FIG. 6 is a structural diagram of the manufacturing of another terminal structure of a power device according to an embodiment of the present application;

[0048] Figure 7 is a structural diagram of manufacturing a terminal structure of another power device of an embodiment of the present application;

[0049] Figure 8 is a structural diagram of manufacturing a terminal structure of another power device of an embodiment of the present application;

[0050] Figure 9 is a structural diagram of manufacturing a terminal structure of another power device of an embodiment of the present application;

[0051] Figure 10 is an electric field intensity curve of a terminal structure of a power device of an embodiment of the present application;

[0052] Figure 11 is a concentration-dependent withstand voltage curve of a single-zone JTE terminal of an embodiment of the present application;

[0053] Figure 12 is a concentration-dependent withstand voltage curve of a terminal structure of a power device of an embodiment of the present application.

[0054] Reference signs: N-type substrate 101, junction termination extension region 102, junction grading doped region 103, field limiting ring 104, trench 105, P-well region 106, cutoff ring N+ region 107, oxide layer 108, polysilicon field plate 109, metal layer 110, N+ type buffer layer 111, P+ type collector region 112, collector terminal 113. DETAILED DESCRIPTION

[0055] In order to make the above objectives, features and advantages of the present application more apparent, further detailed description of the present application will be given below in combination with the accompanying drawings and specific embodiments.

[0056] Power semiconductor devices are one of the core devices of power electronic circuits, and are widely used in automobiles, power supplies, and motors. At present, the terminal of a power semiconductor device has a lateral structure terminal structure (JTE), but the surface implantation dose of the JTE terminal structure is currently low, basically in the order of 1e12, and is greatly affected by the process line introduced charge without field plate protection.

[0057] Modern power devices are mainly formed by connecting thousands of same units in parallel in the source region, the surface voltage of each unit is approximately the same, but the voltage between the terminal unit and the substrate is quite different, and some measures need to be taken to reduce the surface electric field and improve the breakdown voltage, modern silicon power devices generally adopt a shallow planar structure, in the design of high-voltage devices, a field limiting ring is often used to reduce the surface electric field caused by the junction curvature effect and improve the breakdown voltage, however, such a structure will significantly increase the chip area. In addition, the planar field limiting ring often causes peak electric field at the corner of the implanted junction, resulting in degradation of the breakdown characteristics of the device. In order to further improve the junction depth and reduce the peak electric field at the corner of the implanted junction, a trench field limiting ring terminal structure can be used to improve the junction depth. However, using a trench field limiting ring structure terminal also has disadvantages, the reduction of peak electric field will increase the expansion ability of the lateral space charge region of the field limiting ring terminal, resulting in an increase in terminal area.

[0058] The terminal of the power device, due to the high surface implantation dose of the main junction ring, the specific implantation dose is in the order of 1e12~1e15 / cm-2, so that the breakdown position of the terminal structure is at the corner of the main junction, that is, the electric field strength at the corner of the main junction is the largest. However, in the actual process, due to the deviation of the implantation dose of the production line machine, the JTE lateral junction terminal expansion structure is affected, the concentration is low, and then the breakdown is at the JTE lateral junction terminal expansion structure, so that the actual terminal reliability of the flow sheet is poor and the withstand voltage is insufficient.

[0059] One of the core ideas of the embodiment of the present application is to solve the problem of insufficient withstand voltage and concentration dose sensitivity of the traditional JTE terminal by using a composite terminal structure including a junction terminal expansion region, a junction gradual doping region, a plurality of field limiting rings, a trench and a polysilicon field plate.

[0060] Referring to Figure 1 , a schematic diagram of a terminal structure of a power device is shown, which can specifically include the following structures:

[0061] N-type substrate 101.

[0062] The N-type substrate refers to using silicon (or other semiconductor materials) doped with donor impurities (such as phosphorus, arsenic, etc.) as a base material in semiconductor device manufacturing. The donor impurities in the N-type substrate provide free electrons in the material, making the material as a whole exhibit negative electrical properties (Negative), hence the name N-type. The characteristics of the N-type substrate: high electron concentration, the N-type substrate is doped with donor impurities, so it has a relatively high free electron concentration, and the electron is the majority carrier; low hole concentration, due to the high electron concentration, the hole (positive charge carrier) concentration is relatively low, which is the minority carrier; high conductivity, due to the existence of free electrons, the conductivity of the N-type substrate is high, which is suitable for application scenarios that require high conductivity.

[0063] A junction terminal extension region 102, a junction grading doping region 103 and a plurality of field limiting rings 104 are arranged in the N-type substrate 101, the junction terminal extension region 102 is connected with the junction grading doping region 103, the depth of the junction grading doping region 103 gradually decreases in a direction away from the junction terminal extension region 102, the plurality of field limiting rings 104 are arranged at one end of the junction grading doping region 103 away from the junction terminal extension region 102, and the distance of the plurality of field limiting rings 104 to the junction grading doping region 103 gradually increases; the junction terminal extension region 102, the junction grading doping region 103 and the plurality of field limiting rings 104 are doped with P-type ions.

[0064] The junction terminal extension region 102 is a key technology for improving the voltage resistance performance of a semiconductor device. By introducing a lightly doped extension region at the edge of the PN junction of the device, a buffer layer is formed, thereby effectively reducing the electric field concentration phenomenon at the edge of the PN junction and improving the voltage resistance capability of the device. In the edge region of the PN junction, the electric field is usually concentrated in a small area, resulting in excessively high local electric field strength, which is easy to cause breakdown. By introducing a lightly doped extension region at the edge of the PN junction, the electric field distribution is more uniform, avoiding the problem of excessively high local electric field. Through the buffer effect of the extension region, the voltage resistance capability of the device is significantly enhanced, which can withstand higher reverse voltage, can effectively improve the breakdown voltage of the device, and at the same time reduce the leakage current. The sensitivity to doping concentration is reduced, and the device performance is more stable.

[0065] The junction grading doping region 103 optimizes the electric field distribution by introducing a gradual distribution of doping concentration in the PN junction region, thereby improving the voltage resistance performance of the device. VLD (Variable Latticed Doping) is a special gradual doping technology that further optimizes the electric field distribution by precisely controlling the change of doping concentration, reduces the maximum electric field strength, and improves the voltage resistance capability of the device. In the traditional abrupt junction, the doping concentration on both sides of the PN junction is abrupt, which causes the electric field to concentrate at the junction edge and is easy to cause breakdown. By introducing a gradual doping region, the doping concentration gradually changes from one side to the other side, the electric field distribution is more uniform, and the problem of excessively high local electric field is avoided. The electric field can be effectively dispersed, the maximum electric field strength is reduced, thereby improving the breakdown voltage of the device. Through the optimization of the doping distribution, the voltage resistance capability of the device is significantly enhanced. The gradual doping technology reduces the sensitivity to doping concentration through structural optimization, making the device performance more stable. The VLD technology allows the doping concentration to gradually change in the junction region, forming a smooth doping gradient. The change of doping concentration can be realized by ion implantation, diffusion and other processes. By precisely controlling the doping gradient, the electric field distribution is more uniform, the maximum electric field strength is reduced, and the voltage resistance capability of the device can be significantly improved.

[0066] Field Limiting Ring (FLR) 104, by introducing a series of ring-shaped doping regions in the edge of the PN junction of the device, a field limiting structure is formed, thereby effectively reducing the electric field concentration phenomenon of the edge of the PN junction, and improving the withstand voltage capability of the device. The principle of the action of the field limiting ring: in the edge area of the PN junction, the electric field will usually concentrate in a small area, resulting in too high local electric field strength, which is easy to cause breakdown. By introducing a series of ring-shaped doping regions in the edge of the PN junction, the electric field distribution is more uniform, avoiding the problem of too high local electric field. Through the buffering effect of the ring-shaped doping region, the withstand voltage capability of the device is significantly enhanced, and it can withstand higher reverse voltage. The core of the FLR is to introduce a series of ring-shaped doping regions in the edge of the PN junction, which is usually opposite to the doping type of the substrate, usually composed of multiple ring-shaped doping regions, forming a multi-level structure, the doping concentration and width of each ring-shaped doping region gradually change, forming a buffer layer, further optimizing the electric field distribution.

[0067] The trench 105 is provided in the N-type substrate 101, and the trench 105 is provided on the side of the field limiting ring 104 farthest from the junction grading doping region 103 and away from the junction grading doping region 103; the trench 105 is deposited with polysilicon.

[0068] The P-well region 106 and the cutoff ring N+ region 107 are provided in the N-type substrate 101, the P-well region 106 is connected with the junction terminal extension region 102, and the cutoff ring N+ region 107 is provided on the side of the trench 105 away from the field limiting ring 104.

[0069] The P-well region (P-Well) 106 is a region formed by implanting P-type impurities (such as boron) in the N-type substrate, used for isolation and construction of NMOS devices. In the CMOS process, the P-well region is used to isolate NMOS transistors to avoid interference between different transistors. The P-well region isolates the NMOS device from the N-type substrate to form a local P-type region. The source and drain of the NMOS transistor can be formed in the P-well region, which are usually N-type doped. The P-well region forms a PN junction with the N-type source and drain region, which constitutes the basic structure of the NMOS transistor, can reduce the formation of parasitic PNP transistors, thereby reducing parasitic effects and improving device performance.

[0070] Guard Ring (GR) is a terminal technology used to improve the voltage withstanding performance of semiconductor devices. N+ region refers to a high-doped N-type region, which is usually used to construct a conductive channel or terminal structure of a device. The principle of Guard Ring is that in the edge region of a PN junction, the electric field is usually concentrated in a small area, resulting in a local electric field strength that is too high and easily triggers breakdown. Guard Ring introduces a series of ring-shaped doped regions in the edge of the PN junction to make the electric field distribution more uniform, avoiding the problem of excessive local electric field. Through the buffering effect of the ring-shaped doped regions, the voltage withstanding capability of the device is significantly enhanced, which can withstand higher reverse voltage, effectively improve the breakdown voltage of the device, and reduce the leakage current, reducing the sensitivity to doping concentration, making the device performance more stable.

[0071] An oxide layer 108 is disposed on the surface of the N-type substrate 101.

[0072] The oxide layer 108 is an ILD (Interlayer Dielectric) oxide layer region. The main function of the ILD oxide layer region is to isolate the electrical connection between different metal layers, prevent short circuit and leakage, and ensure the electrical insulation between layers by filling the oxide layer between the metal layers. The ILD oxide layer region provides mechanical support for the metal wiring of the chip, preventing physical contact between metal layers. The high hardness and stability of the oxide layer help to protect the chip structure. The ILD oxide layer region is surface planarized by chemical mechanical polishing process, providing a flat surface for subsequent processes such as metal wiring, which can protect the underlying devices and metal wiring from environmental influences such as moisture, contaminants, etc.

[0073] A polysilicon field plate 109 is disposed on the surface of a target region of the oxide layer 108. The target region is a region covering a predetermined width of the edges of the plurality of field limiting rings 104. The polysilicon field plate 109 can effectively reduce the electric field concentration phenomenon at the edge of the PN junction, and improve the voltage withstanding capability of the device.

[0074] A metal layer 110 is disposed on the surface of the P-well region 106, the surface of the part of the junction termination extension region 102 close to the P-well region 106, above the plurality of field limiting rings 104, on the surface of the Guard Ring N+ region 107, and on the surface of the part of the oxide layer 108 close to the Guard Ring N+ region 107. The metal layer 110 disposed on the surface of the P-well region 106 and the surface of the part of the junction termination extension region 102 close to the P-well region 106 is a front metal layer, which can form an ohmic contact with Si (silicon).

[0075] The terminal structure of the power device comprises an N-type substrate, a junction terminal extension region, a junction gradual doping region and a plurality of field limiting rings arranged on the N-type substrate, the junction terminal extension region is connected with the junction gradual doping region, the depth of the junction gradual doping region gradually decreases in the direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction gradual doping region away from the junction terminal extension region, and the distance of the plurality of field limiting rings to the junction gradual doping region gradually increases; the junction terminal extension region, the junction gradual doping region and the plurality of field limiting rings are doped with P-type ions; a trench is arranged on the N-type substrate, the trench is arranged on the side of the field limiting ring farthest from the junction gradual doping region away from the junction gradual doping region; polycrystalline silicon is deposited in the trench; a P-well region and a cutoff ring N+ region are arranged on the N-type substrate, the P-well region is connected with the junction terminal extension region, and the cutoff ring N+ region is arranged on the side of the trench away from the field limiting ring; an oxide layer is arranged on the surface of the N-type substrate; a polycrystalline silicon field plate is arranged on the surface of a target region of the oxide layer, the target region is a region covering the edges of the plurality of field limiting rings with a preset width; a metal layer is arranged on the surface of the P-well region, the surface of the part of the junction terminal extension region close to the P-well region, the top of the plurality of field limiting rings, the surface of the cutoff ring N+ region and the surface of the part of the oxide layer close to the cutoff ring N+ region. By the composite terminal structure comprising the junction terminal extension region, the junction gradual doping region, the plurality of field limiting rings, the trench and the polycrystalline silicon field plate, the maximum electric field strength of the chip can be effectively reduced, and the voltage withstanding performance of the device is improved.

[0076] Reference Figure 2 In the embodiment of the present application, the N-type substrate 101 is an N-type substrate, and the terminal structure further comprises:

[0077] An N+ type buffer layer 111 is formed on the other side of the N-type substrate 101.

[0078] The N-type substrate 101 is a lightly doped N-type material with high resistivity and low carrier concentration, and the N+ type buffer layer 111 is a highly doped N-type material with low resistivity and high carrier concentration. The introduction of the N+ type buffer layer on the N-type substrate can optimize the electric field distribution and reduce the electric field concentration phenomenon at the edge of the PN junction. The N+ type buffer layer 111 can effectively disperse the electric field and reduce the maximum electric field strength, thereby improving the breakdown voltage of the device. By optimizing the electric field distribution, the voltage withstanding capacity of the device is significantly enhanced.

[0079] A P+ type collector region 112 is formed on the N+ type buffer layer 111.

[0080] The P+ type collector region 112 is a high-doped P type material with a low resistivity and a high hole concentration.

[0081] The collector electrode end 113 is formed on the P+ type collector region.

[0082] The collector electrode end 113 is formed on the P+ type collector region.

[0083] In the embodiment of the present application, the width of each field limiting ring is 5-12 um, and the widths of the field limiting rings are the same.

[0084] In the embodiment of the present application, the coverage range of the edge of the plurality of field limiting rings is 0.5-1.5 um.

[0085] In the embodiment of the present application, the depth of the trench is 4-6 um, and the width of the trench is 0.6-2 um.

[0086] In the embodiment of the present application, the thickness of the metal layer is 3-5 um.

[0087] Referring to Figure 3 The manufacturing method of the terminal structure of the power device can be used to manufacture the terminal structure of the power device as described above, and can specifically include the following steps.

[0088] Step 201: providing an N type substrate.

[0089] Referring to Figure 4 The N type substrate is a lightly-doped N type material with a low doping concentration and a high resistivity.

[0090] Step 202, forming a junction terminal extension region 102, a junction grading doped region 103 and a plurality of field limiting rings 104 on the N-type substrate 101; the junction terminal extension region 102 is connected with the junction grading doped region 103, the depth of the junction grading doped region 103 gradually decreases along the direction away from the junction terminal extension region 102, and the plurality of field limiting rings 104 are arranged at one end of the junction grading doped region 103 away from the junction terminal extension region 102.

[0091] Referring to Figure 5 , on the basis of the N-type substrate 101, a P-type JTE injection window, a VLD grading doped injection window and a field limiting ring injection window are manufactured by growing a growth medium mask, photolithography and etching, then P-type boron ion doping is performed, the doping ion concentration interval is about 1e12-1e13, high temperature annealing is performed, the annealing temperature is about 1050-1150C, the annealing time is about 200-350min, the junction terminal extension region 102, the junction grading doped region 103 and the plurality of field limiting rings 104 are formed.

[0092] The growth medium mask is usually used to control the direction and area of epitaxial growth. The growth medium mask blocks the growth of epitaxial material in a specific area by forming a layer of mask material on the wafer surface, thereby achieving precise control of the device structure. The role of the growth medium mask is as follows: the growth medium mask is used to define the area of epitaxial growth and prevent epitaxial material from growing in unwanted areas. Through the design of the mask, precise control of the device structure can be achieved. The electrical performance of the device can be optimized, such as reducing the leakage current, increasing the breakdown voltage, etc. The growth medium mask can be used to optimize the electric field distribution and improve the voltage withstanding capability of the device.

[0093] Photolithography is used to define micron or nanometer scale patterns and structures on semiconductor wafers. Photolithography technology transfers the designed patterns to the wafer surface through a photosensitive material (photoresist) and an optical system, thereby achieving precise control of device structures. The process flow of photolithography: a layer of photoresist, a kind of photosensitive material, is uniformly coated on the wafer surface, which is divided into positive and negative types, the exposed area of the positive type is dissolved, and the unexposed area is retained, and the exposed area of the negative type is retained, and the unexposed area is dissolved; align the mask with the wafer to ensure that the pattern on the mask matches the position on the wafer accurately, the mask contains the designed pattern, and the pattern is projected onto the wafer surface through an optical system; use a light source (such as ultraviolet light, deep ultraviolet light, extreme ultraviolet light, etc.) to expose the photoresist through the mask, and the photoresist in the exposed area undergoes a chemical reaction to change its solubility; place the exposed wafer in a developing solution to dissolve the photoresist in the exposed or unexposed area, forming a pattern, after development, the wafer surface will leave a pattern corresponding to the mask pattern; through etching process (such as dry etching, wet etching) or ion implantation process, the pattern is transferred to the material layer (such as oxide layer, polysilicon layer, etc.) on the wafer surface, after etching or ion implantation, the wafer surface will form a structure corresponding to the photoresist pattern; through stripping process (such as wet stripping, plasma stripping) to remove the remaining photoresist, complete the photolithography process.

[0094] After ion implantation or diffusion process, the doping atoms are usually in an inactive state, high-temperature annealing can make the doping atoms enter the lattice position to become free carriers, thereby improving the conductivity of the semiconductor; ion implantation or diffusion process will introduce lattice damage (such as vacancies, interstitial atoms, etc.) in the semiconductor material, high-temperature annealing can repair these damages and restore the integrity of the lattice, thereby improving the performance and reliability of the device; in the area where the metal contacts the silicon, high-temperature annealing can promote the reaction between the metal and the silicon to form a low-resistance metal silicide, which has a low contact resistance and is a key step to form ohmic contact; high-temperature annealing can optimize the electrical performance of the device, such as reducing the leakage current, improving the breakdown voltage, and improving the electric field distribution, etc.

[0095] Step 203, forming a trench 105 on the N-type substrate 101, the trench 105 is located on the side of the field limiting ring 104 farthest from the junction grading doping region 103 away from the junction grading doping region 103.

[0096] Referring to Figure 6 The trench 105 is made on the right side of the field limiting ring through photolithography, etching, sacrificial oxidation, gate oxide oxidation, polysilicon deposition and etching, oxide deposition, etc.

[0097] Step 204, depositing polysilicon in the trench.

[0098] Polysilicon deposition and etching are performed to fill the trench with polysilicon.

[0099] Step 205, forming P-well region 106 and cutoff ring N+ region 107 on N-type substrate 101; P-well region 106 is connected with junction terminal extension region 102, and cutoff ring N+ region 107 is arranged on the side of trench 105 away from field limiting ring 104.

[0100] Referring to Figure 7 P-well region 106 and cutoff ring N+ region 107 are formed by growth medium mask, photolithography, etching, ion implantation and the like, wherein the P-type ion concentration ranges from 5e12 to 5e13, the N-type ion concentration ranges from 1e14 to 2e15, and corresponding annealing treatment is performed, with the annealing temperature being about 1050-1200℃ and the annealing time being about 40-120min.

[0101] Step 206, growing oxide layer 108 on the surface of N-type substrate 101, and removing the corresponding oxide layer 108 on the surface of P-well region 106, the center region of the plurality of field limiting rings 104 and the cutoff ring N+ region 107.

[0102] Referring to Figure 8 An ILD oxide layer is deposited on the ion implantation region by deposition process, as isolation protection.

[0103] Step 207, generating polysilicon field plate 109 on the surface of the target region of oxide layer 208; the target region is a region covering the edges of the plurality of field limiting rings with a predetermined width.

[0104] Referring to Figure 9 Then, polysilicon field plate 109 with a certain length and thickness is formed near the field limiting ring, and polysilicon field plate 109 is located on the surface of oxide layer 108.

[0105] Step 208, generating metal layer 110 on the surface of P-well region 106, on the surface of the part of junction terminal extension region 102 close to P-well region 106, above the plurality of field limiting rings 104, on the surface of cutoff ring N+ region 107 and on the surface of the part of oxide layer 108 close to cutoff ring N+ region 107.

[0106] Referring to Figure 1 Front metal is formed by photolithography, metallization and stripping process, and then high-temperature annealing is performed to form ohmic contact with Si, with the ohmic metal being Ni, Ti or Ti / Ni alloy and AlCu.

[0107] The terminal structure of the power device comprises an N-type substrate, a junction terminal extension region, a junction grading doping region and a plurality of field limiting rings arranged on the N-type substrate, the junction terminal extension region is connected with the junction grading doping region, the depth of the junction grading doping region gradually decreases in a direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction grading doping region away from the junction terminal extension region, and the distance of the plurality of field limiting rings to the junction grading doping region gradually increases; the junction terminal extension region, the junction grading doping region and the plurality of field limiting rings are doped with P-type ions; a trench is arranged on the N-type substrate, the trench is arranged on one side of the farthest field limiting ring to the junction grading doping region away from the junction grading doping region; polycrystalline silicon is deposited in the trench; a P-well region and a cutoff ring N+ region are arranged on the N-type substrate, the P-well region is connected with the junction terminal extension region, and the cutoff ring N+ region is arranged on one side of the trench away from the field limiting ring; an oxide layer is arranged on the surface of the N-type substrate; a polycrystalline silicon field plate is arranged on the surface of a target region of the oxide layer, the target region is a region covering the edges of the plurality of field limiting rings with a preset width; a metal layer is arranged on the surface of the P-well region, the surface of a partial region of the junction terminal extension region close to the P-well region, the top of the plurality of field limiting rings, the surface of the cutoff ring N+ region and the surface of a partial region of the oxide layer close to the cutoff ring N+ region. By the composite terminal structure comprising the junction terminal extension region, the junction grading doping region, the plurality of field limiting rings, the trench and the polycrystalline silicon field plate, the maximum electric field strength of the chip can be effectively reduced, and the voltage withstanding performance of the device is improved.

[0108] In the embodiment of the application, the N-type substrate 101 is an N-type substrate, and the method further comprises:

[0109] back-thinning the N-type substrate on the other side of the N-type substrate;

[0110] high-concentration N-type doping is performed on the other side of the N-type substrate to form an N+ type buffer layer 111;

[0111] high-concentration P-type doping is performed on the N+ type buffer layer 111 to form a P+ type collector region 112;

[0112] a metal layer is deposited on the P+ type collector region 112 to form a collector electrode terminal 113.

[0113] Specifically, refer to Figure 2The back surface process is carried out on the back surface of the N-substrate high-resistance semiconductor region, the chip is thinned to a suitable thickness through a back surface thinning process, N-type doping with a concentration gradient is carried out twice along the lateral direction of the device to obtain a heavily doped N+ buffer layer 111 with an electric field cutoff effect, P-type heavy doping is carried out on the buffer layer to obtain a P+ collector region 112, and finally a thin metal layer is deposited from the P+ collector region 112 to serve as a collector electrode 113, and an ohmic metal contact is formed on the back surface, and the ohmic metal is Ni, Ti or Ti / Ni alloy and AlCu.

[0114] In the embodiment of the present application, the distance between the multiple field limiting rings and the junction grading doped region gradually increases; the junction termination extension region, the junction grading doped region and the multiple field limiting rings are doped with P-type ions; the width of each field limiting ring is 5-12 um.

[0115] In the embodiment of the present application, the coverage of the edge of the multiple field limiting rings is 0.5-1.5 um.

[0116] In the embodiment of the present application, the depth of the trench is 4-6 um, and the width of the trench is 0.6-2 um.

[0117] In the embodiment of the present application, the thickness of the metal layer is 3-5 um.

[0118] Referring to Figure 10 , the electric field intensity curve of the terminal structure of a power device in an embodiment of the present application is shown, Figure 10 is the electric field intensity distribution along the horizontal direction of the terminal of the junction termination extension (JTE) terminal structure and the structure of the present application under the same length, and the result is obtained by the tangent of the electric field distribution graph after device BV simulation, the vertical coordinate represents the electric field intensity, and the horizontal coordinate represents the distance along the horizontal direction of the terminal. The result shows that, under the same injection concentration, the JTE terminal electric field intensity is distributed and uneven in the horizontal direction, the electric field is concentrated near the main junction and the JTE end region, and the maximum electric field intensity is 2.32e5 V / m. The horizontal distribution of the electric field intensity of the terminal of the present application is relatively uniform, and the maximum electric field intensity is only 2.23e5 V / m, which is smaller than the previous structure, and the voltage resistance performance is better.

[0119] Referring to Figure 11 , a concentration-dependent voltage resistance curve of a single-zone JTE terminal in an embodiment of the present application is shown, referring to Figure 12 , a concentration-dependent voltage resistance curve of a terminal structure of a power device in an embodiment of the present application is shown, wherein the horizontal coordinate represents the injection concentration, and the vertical coordinate represents the voltage resistance value, according to Figure 11 and Figure 12It can be seen that the single-zone JTE terminal withstand voltage changes sharply with the change of the injection concentration, and the withstand voltage value is sensitive to the concentration change; the terminal of the application has a relatively small BV (breakdown voltage) change with the change of the injection concentration, and the sensitivity to the concentration dependence is reduced, which is beneficial to the stability of the terminal structure of the power device.

[0120] The embodiment of the application is based on the traditional single-zone JTE terminal structure, and a composite terminal structure of junction grading doping + field limiting ring + field plate + trench is constructed through reasonable structure design. Since the terminal structure has a grading doping concentration, the horizontal electric field concentration phenomenon is obviously weakened, and the maximum concentrated electric field strength is reduced by nearly 10% compared with the single-zone JTE terminal structure. In addition, the terminal structure of the application is less affected by the change of the doping concentration, so that the stability of the device withstand voltage is improved.

[0121] Since the trench technology is combined on the junction grading doping terminal, on the one hand, the length of the terminal can be reduced as a whole, and the cost can be reduced; on the other hand, the withstand voltage performance of the terminal can be optimized, the electric field concentration problem of the traditional JTE terminal can be improved, the leakage current can be reduced, and the problem of dependence on the doping concentration can be reduced.

[0122] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the application are not limited by the action sequence described, because according to the embodiments of the application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily required by the embodiments of the application.

[0123] The embodiment of the application discloses a chip, which comprises the terminal structure of the power device as described above.

[0124] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0125] Those skilled in the art should know that the embodiments of the application can be provided as a method, device, or computer program product. Therefore, the embodiments of the application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer usable program code.

[0126] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0127] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, such that a series of operational steps are carried out on the computer or other programmable terminal devices to produce a computer implemented process so that the instructions executed on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0129] Although preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to these embodiments without departing from the scope of the present application. Accordingly, the appended claims are intended to encompass all such modifications and variations as falling within the scope of the present application.

[0130] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover non-exclusive inclusions, so that a process, method, article, or terminal device including a list of elements does not only include those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article, or terminal device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article, or terminal device including the element.

[0131] The terminal structure, manufacturing method and chip of the power device provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this document. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application ranges; in view of the above, the content of this specification should not be understood as a limitation of the present application.

Claims

1. A termination structure for a power device, characterized in that, The terminal structure includes: N-type substrate; The N-type substrate includes a junction termination extension region, a junction gradient doped region, and multiple field-limiting rings. The junction termination extension region is connected to the junction gradient doped region. The depth of the junction gradient doped region gradually decreases away from the junction termination extension region. The multiple field-limiting rings are located at the end of the junction gradient doped region away from the junction termination extension region, and the distance between the multiple field-limiting rings and the junction gradient doped region gradually increases. P-type ions are doped within the junction termination extension region, the junction gradient doped region, and the multiple field-limiting rings. A trench is provided on the N-type substrate, the trench being located on the side of the field limiting ring furthest from the junction graded doping region; polysilicon is deposited in the trench; A P-well region and a cutoff ring N+ region are disposed on the N-type substrate. The P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is disposed on the side of the trench away from the field limiting ring. An oxide layer disposed on the surface of the N-type substrate; A polycrystalline silicon field plate is disposed on the surface of the target region of the oxide layer, wherein the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings; A metal layer disposed on the surface of the P-well region, the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, the surface of the N+ region of the stop ring, and the surface of a portion of the oxide layer near the N+ region of the stop ring.

2. The terminal structure of the power device according to claim 1, characterized in that, The N-type substrate is an N-type substrate, and the terminal structure further includes: An N+ type buffer layer is formed on the other side of the N-type substrate; A P+ type collector region is formed on the N+ type buffer layer; The collector electrode formed on the P+ type collector region.

3. The termination structure of the power device according to claim 1, characterized in that, The width range of each field limiting ring is 5-12 μm.

4. The termination structure of the power device according to claim 1, characterized in that, The coverage range of the edges of the plurality of field limiting rings is 0.5 to 1.5 μm.

5. The terminal structure of the power device according to claim 1, characterized in that, The depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

6. The termination structure of the power device according to claim 1, characterized in that, The thickness of the metal layer ranges from 3 to 5 μm.

7. A method for manufacturing a terminal structure of a power device, characterized in that, The method for manufacturing a termination structure for a power device as described in any one of claims 1 to 6 includes: Provide N-type substrates; A junction termination extension region, a junction gradient doped region, and multiple field confinement rings are formed on the N-type substrate; the junction termination extension region is connected to the junction gradient doped region, the depth of the junction gradient doped region gradually decreases along the direction away from the junction termination extension region, and the multiple field confinement rings are disposed at one end of the junction gradient doped region away from the junction termination extension region. In the N-type substrate, a trench is formed, the trench being located on the side of the field limiting ring furthest from the junction graded doped region. Polycrystalline silicon is deposited within the trench; A P-well region and a cutoff ring N+ region are formed on the N-type substrate; the P-well region is connected to the junction termination extension region, and the cutoff ring N+ region is located on the side of the trench away from the field limiting ring; An oxide layer is grown on the surface of the N-type substrate, and the oxide layers corresponding to the surfaces of the P-well region, the central regions of the plurality of field limiting rings, and the N+ region of the cutoff ring are removed. A polycrystalline silicon field plate is formed on the surface of the target region of the oxide layer; the target region is a region of a predetermined width covering the edges of the plurality of field limiting rings; A metal layer is formed on the surface of the P-well region, the surface of a portion of the junction terminal extension region near the P-well region, above the plurality of field limiting rings, the surface of the N+ region of the stop ring, and the surface of a portion of the oxide layer near the N+ region of the stop ring.

8. The method for manufacturing the terminal structure of the power device according to claim 7, characterized in that, The N-type substrate is an N-type substrate, and the method further includes: The N-type substrate is back-side thinned on the other side of the N-type substrate; On the other side of the N-type substrate, the N-type substrate is subjected to high-concentration N-type doping to form an N+ type buffer layer; High-concentration P-type doping is performed on the N+ type buffer layer to form a P+ type collector region; A metal layer is deposited on the P+ type collector region to form a collector electrode.

9. The method for manufacturing the terminal structure of the power device according to claim 7, characterized in that, The distance between the plurality of field-limiting rings and the junction graded-doped region gradually increases; the junction terminal extension region, the junction graded-doped region, and the plurality of field-limiting rings are doped with P-type ions; the width of each field-limiting ring is 5-12 μm.

10. The method for manufacturing the terminal structure of the power device according to claim 7, characterized in that, The coverage range of the edges of the plurality of field limiting rings is 0.5 to 1.5 μm.

11. The method for manufacturing the terminal structure of the power device according to claim 7, characterized in that, The depth of the trench ranges from 4 to 6 μm, and the width of the trench ranges from 0.6 to 2 μm.

12. The method for manufacturing the terminal structure of the power device according to claim 7, characterized in that, The thickness of the metal layer ranges from 3 to 5 μm.

13. A chip comprising a termination structure of a power device as described in any one of claims 1-6.

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