Groove MOSFET device, manufacturing method and chip

Abstract

The embodiment of the invention provides a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, a manufacturing method and a chip. The device comprises a first section region, a second section region and a third section region which are alternately arranged along a first direction, each of the first section region, the second section region and the third section region comprises an N-type substrate, an epitaxial layer, a first groove, an oxide layer, a first N region, a P well region, an N + region, a second groove, a grid electrode and a source electrode; the epitaxial layer is arranged on one side of the N-type substrate; the first N region is located below the two sides of the first groove; the N + regions are located on the two sides of the first groove. The P well region is connected below the N + region; the second groove is located at the bottom of the first groove; the P regions, located at the bottom and corners of the second groove, of the first section region play a role in electric field shielding, and the P regions, located at the bottom of the first groove, of the third section region play a role in electric field shielding, so that device damage caused by a relatively strong electric field generated at the corners of the grooves is avoided, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench MOSFET device, a manufacturing method and a chip. Background Art

[0002] Silicon carbide (SiC) has become an ideal material for high-temperature and high-voltage power electronics due to its excellent physical and electrical properties, such as high electron saturation drift velocity, high critical breakdown electric field, wide bandgap width and excellent thermal conductivity. In the family of vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, double-injected planar gate (DMOSFET, Double-Diffused MOSFET) and trench gate (UMOSFET) have their own strengths. The 4H-SiC UMOSFET, with its higher density cell structure and high mobility given by the non-polar surface, not only achieves a significant reduction in on-resistance, but also greatly improves the channel density. These unique advantages make the application prospects of 4H-SiC UMOSFET in the field of power electronics broader, indicating its important role in promoting the advancement of power electronics technology.

[0003] Silicon carbide has significant advantages in high-frequency applications due to its excellent physical and electrical properties, such as high electron saturation drift velocity, high thermal conductivity, and high breakdown electric field. These properties not only improve the performance of the device, but also enable it to operate stably in high temperature and high power environments. However, under high breakdown electric field conditions, the electric field strength borne by the gate dielectric is much higher than that under normal operating conditions, which can easily cause dielectric breakdown, damage or degradation, and the reliability of the gate dielectric is low. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a trench MOSFET device, a manufacturing method and a chip that overcome the above problems or at least partially solve the above problems.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a trench MOSFET device, the device comprising a first cross-sectional area, a second cross-sectional area and a third cross-sectional area alternately arranged along a first direction;

[0006] The first cross-sectional area, the second cross-sectional area and the third cross-sectional area each include: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N region, a P well region, an N+ region, a second trench, a gate and a source;

[0007] The epitaxial layer is disposed on one side of the N-type substrate; the first N region is located below both sides of the first trench;

[0008] The N+ region is located on both sides of the first trench;

[0009] The P-well region is connected to the lower part of the N+ region; the P-well region and the N+ region are connected to the sidewalls of the first trench respectively;

[0010] The second groove is located at the bottom of the first groove;

[0011] The gate is embedded in the first trench; the source is embedded in the second trench; the gate is located on both sides of the source;

[0012] The oxide layer is disposed in the first trench and the second trench, and wraps the gate and the source;

[0013] The first cross-sectional area further includes: a P region located below the first trench, the P region and the first N region are located in the same layer; the second trench extends to the inside of the P region;

[0014] The third cross-sectional area further includes: a P region located below the first trench, the P region being connected to the bottom of the first trench; and the second trench penetrating the P region.

[0015] Optionally, the device further comprises:

[0016] The first cross-sectional area and the third cross-sectional area both further include: a P+ region disposed on both sides of the first trench in the epitaxial layer, the P+ region being located in the same layer as the N+ region and being connected to the N+ region;

[0017] The second cross-sectional area further includes: a second N region disposed in the epitaxial layer on both sides of the first trench, the second N region having a depth connected to the first N region, and the second N region being connected to the N+ region and the P well region.

[0018] Optionally, the device further comprises:

[0019] an interlayer dielectric passivation layer disposed on the surface of the epitaxial layer;

[0020] Contact holes provided on both sides of the interlayer dielectric passivation layer;

[0021] A first metal layer is disposed on the surface of the contact hole; the first metal layer is in contact with a portion of the P+ region and the N+ region;

[0022] A second metal layer is provided on the surface of the first metal and the interlayer dielectric passivation layer.

[0023] Optionally, the device further includes: a drain located on the other side of the N-type substrate.

[0024] Accordingly, an embodiment of the present invention discloses a method for manufacturing a trench MOSFET device, which is used to manufacture the trench MOSFET device as described above, and the method comprises:

[0025] Providing an N-type substrate;

[0026] growing an epitaxial layer on one side of the N-type substrate;

[0027] Etching a first trench on the epitaxial layer;

[0028] growing an oxide layer on the surface of the epitaxial layer;

[0029] Injecting N-type ions into the epitaxial layer corresponding to the lower part of both sides of the first trench to form a first N region; the first N region is located below both sides of the first trench;

[0030] In the epitaxial layer, P-type ions are injected into both sides of the first trench to form a P-well region, and N-type ions are injected into the epitaxial layer to form an N+ region; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are respectively connected to the sidewalls of the first trench;

[0031] Etching a second groove at the bottom of the first groove;

[0032] A gate is formed in the first trench, and a source is formed in the second trench, wherein the gate is located at both sides of the source, and an oxide layer is formed around the gate and the source;

[0033] In the first cross-sectional area, when N-type ions are implanted below the two sides of the first trench in the epitaxial layer to form a first N region, P-type ions are implanted below the first trench in the epitaxial layer to form a P region; the first N region and the P region are located in the same layer;

[0034] In the third cross-sectional area, when N-type ions are implanted below the two sides of the first trench in the epitaxial layer to form a first N region, P-type ions are implanted below the first trench in the epitaxial layer to form a P region; the P region is connected to the bottom of the first trench.

[0035] Optionally, the method further includes:

[0036] Injecting P-type ions into the epitaxial layer at both sides of the first trench to form a P-well region, and injecting N-type ions into the epitaxial layer to form an N+ region. Injecting P-type ions into the epitaxial layer at both sides of the first trench to form a P+ region, wherein the P+ region is located in the same layer as the N+ region and is connected to the N+ region;

[0037] In the second cross-sectional area, P-type ions are injected into the epitaxial layer at both sides corresponding to the first trench to form a P-well region, and N-type ions are injected into the epitaxial layer at both sides corresponding to the first trench to form an N+ region. N-type ions are injected into the epitaxial layer at both sides corresponding to the first trench to a depth that is connected to the first N region to form a second N region; the second N region is connected to the N+ region and the P-well region.

[0038] Optionally, forming a gate in the first trench, forming a source in the second trench, the gate being located on both sides of the source, and an oxide layer being formed around the gate and the source, comprises:

[0039] Removing the oxide layer on the surface of the epitaxial layer, and growing a gate oxide layer on the surface of the first trench and the second trench;

[0040] Depositing polysilicon on the surface of the epitaxial layer to deposit polysilicon in the first trench and the second trench;

[0041] Etching the polysilicon on the surface of the epitaxial layer, and retaining the polysilicon on both sides of the first trench as a gate;

[0042] growing an oxide layer in the first trench and the second trench;

[0043] Etching the oxide layer in the first trench and the second trench to form a groove in the oxide layer, and retaining the oxide layer covering the surface of the gate and the second trench;

[0044] Depositing polysilicon in the groove as a source electrode;

[0045] An oxide layer is formed around the gate and the source.

[0046] Optionally, forming an oxide layer around the gate and the source includes:

[0047] In the first cross-sectional area, growing an oxide layer in the first trench and the second trench;

[0048] In the second cross-sectional area, an oxide layer is grown in the first trench and the second trench, and the oxide layer on the surface of the source electrode is removed;

[0049] In the third cross-sectional area, an oxide layer is grown in the first trench and the second trench, and polysilicon is deposited on the surface of the epitaxial layer so that the gates on both sides of the first trench are connected through the polysilicon, and the polysilicon on the surface of the epitaxial layer except the first trench and the second trench is removed.

[0050] Optionally, the method further includes:

[0051] Depositing an insulating material on the surface of the epitaxial layer to form an interlayer dielectric passivation layer;

[0052] Remove the interlayer dielectric passivation layer above the N+ region and above the P+ region to form a contact hole

[0053] Depositing a first metal layer on the surface of the contact hole;

[0054] A second metal layer is deposited on the surface of the first metal and the interlayer dielectric passivation layer.

[0055] Optionally, the method further includes:

[0056] Thinning the other side of the N-type substrate;

[0057] A metal is deposited on the other side of the N-type substrate as a drain.

[0058] Correspondingly, an embodiment of the present invention discloses a trench MOSFET device as described in any one of the above items.

[0059] The embodiments of the present invention include the following advantages:

[0060] A trench MOSFET device according to an embodiment of the present invention comprises a first cross-sectional area, a second cross-sectional area and a third cross-sectional area alternately arranged along a first direction; the first cross-sectional area, the second cross-sectional area and the third cross-sectional area each comprise: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N region, a P well region, an N+ region, a second trench, a gate and a source; the epitaxial layer is arranged on one side of the N-type substrate; the first N region is located below both sides of the first trench; the N+ region is located on both sides of the first trench; the P well region is connected to the bottom of the N+ region; the P well region and the N + region, respectively connected to the sidewalls of the first trench; the second trench is located at the bottom of the first trench; the gate is embedded in the first trench; the source is embedded in the second trench; the gate is located on both sides of the source; the oxide layer is arranged in the first trench and the second trench, wrapping the gate and the source; the first cross-sectional area also includes: a P region located below the first trench, the P region and the first N region are located in the same layer; the second trench extends to the inside of the P region; the third cross-sectional area also includes: a P region located below the first trench, the P region is connected to the bottom of the first trench; the second trench runs through the P region. The embodiment of the present invention uses the electric field shielding effect of the P region located at the bottom and corner of the second trench in the first cross-sectional area, and the electric field shielding effect of the P region located at the bottom of the first trench in the third cross-sectional area, thereby avoiding device damage caused by a strong electric field generated at the corner of the trench, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 is a three-dimensional structural diagram of a trench MOSFET device according to an embodiment of the present invention;

[0062] Figure 2 is a schematic structural diagram of a first cross-sectional area of ​​a trench MOSFET device according to an embodiment of the present invention;

[0063] Figure 3 is a schematic structural diagram of a second cross-sectional area of ​​a trench MOSFET device according to an embodiment of the present invention;

[0064] Figure 4 is a schematic structural diagram of a third cross-sectional area of ​​a trench MOSFET device according to an embodiment of the present invention;

[0065] Figure 5 is a flowchart of the steps of a method for manufacturing a trench MOSFET device according to an embodiment of the present invention;

[0066] Figure 6 It is a structural schematic diagram of a trench MOSFET device manufacturing according to an embodiment of the present invention;

[0067] Figure 7 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0068] Figure 8 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0069] Fig. 9 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0070] Fig.10 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0071] Fig.11 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0072] Fig.12 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0073] Fig.13 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0074] Fig.14 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0075] Fig.15 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0076] Fig.16It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0077] Fig.17 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0078] Fig.18 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0079] Fig.19 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0080] Fig. 20 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0081] Fig.21 It is a structural schematic diagram of another trench MOSFET device manufacturing according to an embodiment of the present invention;

[0082] Fig. 22 It is a schematic structural diagram of another trench MOSFET device manufacturing embodiment of the present invention.

[0083] Figure numerals: first cross-sectional area 10, second cross-sectional area 20, third cross-sectional area 30, N-type substrate 101, epitaxial layer 102, first trench 103, oxide layer 104, first N region 105, P well region 106, N+ region 107, second trench 108, gate 109, source 110, P region 111, P+ region 112, second N region 113, interlayer dielectric passivation layer 114, first metal layer 115, second metal layer 116, drain 117. DETAILED DESCRIPTION

[0084] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0085] Silicon carbide has become an ideal material for high-temperature and high-voltage power electronics due to its excellent physical and electrical properties, such as high electron saturation drift velocity, high critical breakdown electric field, wide bandgap width and excellent thermal conductivity. In the family of vertical MOSFET devices, double-injection planar gate and trench gate types each have their own strengths. The 4H-SiC UMOSFET, with its higher density cell structure and high mobility given by the non-polar surface, not only achieves a significant reduction in on-resistance, but also greatly improves the channel density. These unique advantages make the application prospects of 4H-SiC UMOSFET in the field of power electronics broader, indicating its important role in promoting the advancement of power electronics technology.

[0086] Silicon carbide has significant advantages in high-frequency applications due to its excellent physical and electrical properties, such as high electron saturation drift velocity, high thermal conductivity, and high breakdown electric field. These characteristics not only improve the performance of the device, but also enable it to operate stably in high temperature and high power environments. However, under high breakdown electric field conditions, the electric field strength borne by the gate dielectric is much higher than that under normal operating conditions, which can easily cause dielectric breakdown, damage or degradation, and the reliability of the gate dielectric is low. Moreover, due to the fast switching speed of SiC MOSFET, it is easily affected by external circuits and has poor anti-interference ability.

[0087] One of the core concepts of the embodiment of the present invention is to avoid device damage caused by strong electric fields at the corners of the trenches by utilizing the electric field shielding effect of the P region at the bottom and corners of the second trench in the first cross-sectional area and the electric field shielding effect of the P region at the bottom of the first trench in the third cross-sectional area, thereby improving the reliability of the device.

[0088] Reference Figure 1 , shows a three-dimensional structure diagram of a trench MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0089] The first cross-sectional areas 10 , the second cross-sectional areas 20 , and the third cross-sectional areas 30 are alternately arranged along the first direction.

[0090] The first cross-sectional area 10 , the second cross-sectional area 20 and the third cross-sectional area 30 all include: an N-type substrate 101 , an epitaxial layer 102 , a first trench 103 , an oxide layer 104 , a first N region 105 , a P well region 106 , an N+ region 107 , a second trench 108 , a gate 109 and a source 110 .

[0091] The epitaxial layer is disposed on one side of the N-type substrate 101 ; the first N region 105 is located below both sides of the first trench 103 .

[0092] The N+ region 107 is located at two sides of the first trench 103 .

[0093] The P-well region 106 is connected to the lower portion of the N+ region 107 ; the P-well region 106 and the N+ region 107 are connected to the sidewalls of the first trench 103 , respectively.

[0094] The second groove 108 is located at the bottom of the first groove 103 .

[0095] The gate 109 is embedded in the first trench 103 ; the source 110 is embedded in the second trench 108 ; and the gate 109 is located at both sides of the source 110 .

[0096] The oxide layer 104 is disposed in the first trench 103 and the second trench 108 , and wraps the gate 109 and the source 110 .

[0097] The first cross-sectional area 10 further includes: a P region 111 located below the first trench 103 , wherein the P region 111 and the first N region are located in the same layer 105 ; and the second trench 108 extends into the inside of the P region 111 .

[0098] The third cross-sectional area 30 further includes: a P region 111 located below the first trench 103 , wherein the P region 111 is connected to the bottom of the first trench 103 ; and the second trench 108 penetrates the P region.

[0099] In the first cross-sectional area 10, a gate 109 and a source 110 are manufactured through multi-level grooves. The gate 109 is polysilicon connected to the gate, and the source 110 is polysilicon connected to the source. A thicker oxide layer 104 is deposited below and on both sides of the source 110, thereby increasing Cgs (gate-source capacitance), reducing Cgd (gate-drain capacitance), and lowering the ratio of Cgd / Ciss, thereby improving the dv / dt processing capability during switching and improving the switching stability of the device.

[0100] Cgd / Ciss is an important parameter ratio used to describe the parasitic capacitance characteristics of MOSFET, especially the performance related to the Miller Effect. Cgd / Ciss: The ratio of gate-drain capacitance to input capacitance reflects the proportion of Cgd in the total input capacitance. The Miller effect refers to the fact that during the switching process of MOSFET, due to the presence of Cgd, the change in drain voltage will be fed back to the gate through Cgd, causing the gate voltage to oscillate or delay. The larger the value of Cgd / Ciss, the more significant the Miller effect and the worse the stability of the gate drive circuit. The larger the value of Cgd / Ciss, the slower the switching speed of the MOSFET and the higher the dynamic power consumption. In high-frequency applications, a smaller Cgd / Ciss value helps to improve switching speed and efficiency.

[0101] In the first cross-sectional area 10, the P region 111 is located below and at the corner of the second trench 108, which can play an electric field shielding role, and can prevent the strong electric field from being generated at the corner of the second trench 108 and damaging the chip. In addition, the JFET (Junction Field-Effect Transistor) structure formed between the P regions 111 in the two cell structures has a relatively large resistance value, and the first N region 105 is a deep implantation of N-type ions, which can effectively reduce the resistance value there, that is, reduce the resistance value in the current conduction path. Figure 1 There are two cells in the figure, and the structures of the two cells are the same.

[0102] JFET is the abbreviation of junction field effect transistor, which is a field effect transistor based on PN junction. Unlike MOSFET, JFET adjusts the resistance of the conductive channel by controlling the depletion layer width of the PN junction, thereby achieving current control. The basic structure of FET includes the following parts: channel, the channel is the core part of JFET, composed of N-type or P-type semiconductor materials. According to the type of channel, JFET is divided into N-channel JFET and P-channel JFET; gate, the gate forms a PN junction with the channel. For N-channel JFET, the gate is P-type material; for P-channel JFET, the gate is N-type material, and the gate controls the conductivity of the channel by reverse bias (PN junction is in reverse bias state); source, the source is the input end of the current, usually connected to the low end of the channel; drain, the drain is the output end of the current, usually connected to the high end of the channel; PN junction, the PN junction between the gate and the channel is the key to the operation of JFET. By changing the gate voltage, the depletion layer width of the PN junction can be adjusted, thereby controlling the conductivity of the channel.

[0103] In the third cross-sectional area 10 , the P region 111 is located below the first trench 103 and above the bottom of the second trench 108 , which can better shield the electric field at the bottom corner of the first-level trench 103 .

[0104] A trench MOSFET device according to an embodiment of the present invention comprises a first cross-sectional area, a second cross-sectional area and a third cross-sectional area arranged alternately along a first direction; the first cross-sectional area, the second cross-sectional area and the third cross-sectional area all comprise: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N region, a P-well region, an N+ region, a second trench, a gate and a source; the epitaxial layer is arranged on one side of the N-type substrate; the first N region is located below both sides of the first trench; the N+ region is located on both sides of the first trench; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are connected to the first trench, respectively. The second trench is located at the bottom of the first trench; the gate is embedded in the first trench; the source is embedded in the second trench; the gate is located on both sides of the source; the oxide layer is arranged in the first trench and the second trench, wrapping the gate and the source; the first cross-sectional area also includes: a P region located below the first trench, the P region and the first N region are located in the same layer; the second trench extends to the inside of the P region; the third cross-sectional area also includes: a P region located below the first trench, the P region is connected to the bottom of the first trench; the second trench runs through the P region. The embodiment of the present invention uses the electric field shielding effect of the P region located at the bottom and corner of the second trench in the first cross-sectional area, and the electric field shielding effect of the P region located at the bottom of the first trench in the third cross-sectional area, thereby avoiding device damage caused by a strong electric field at the corner of the trench, thereby improving the reliability of the device.

[0105] Reference Figure 2-Figure 4 In an embodiment of the present invention, the device further comprises:

[0106] The first cross-sectional area 10 and the third cross-sectional area 30 both further include: a P+ region 112 disposed on both sides of the first trench 103 in the epitaxial layer 102 , wherein the P+ region 112 is located in the same layer as the N+ region 107 and is connected to the N+ region 107 .

[0107] The second cross-sectional area also includes: a second N region 113 disposed in the epitaxial layer 102 on both sides of the first trench 103 , the second N region 113 is deep enough to connect with the first N region 105 , and the second N region 113 is connected with the N+ region 107 and the P well region 106 .

[0108] In the second cross-sectional area, the depth of the second N region 113 is such that it is connected to the first N region 105 , so that a Schottky contact is formed at the parasitic diode of the MOSFET, and the on-resistance is relatively small.

[0109] In the third cross-sectional area, the gate 109 is polysilicon connected to the gate, and the polysilicon on both sides is connected together through the polysilicon on the top.

[0110] In an embodiment of the present invention, the device further includes:

[0111] An interlayer dielectric passivation layer 114 is disposed on the surface of the epitaxial layer 102 .

[0112] Contact holes are provided on both sides of the interlayer dielectric passivation layer 114 .

[0113] A first metal layer 115 is disposed on the surface of the contact hole; the first metal layer 115 is in contact with a portion of the P+ region 112 and the N+ region 107 .

[0114] A second metal layer 116 is provided on the first metal 115 and the surface 114 of the interlayer dielectric passivation layer.

[0115] In the embodiment of the present invention, the device further includes: a drain 117 located on the other side of the N-type substrate 101 .

[0116] Reference Figure 5 , shows that in an embodiment of the present invention, a method for manufacturing a trench MOSFET device is shown, which is used to manufacture the trench MOSFET device as described above, and the method includes:

[0117] Step 201, providing an N-type substrate.

[0118] Step 202 : growing an epitaxial layer on one side of the N-type substrate.

[0119] Step 203: etching a first trench on the epitaxial layer.

[0120] Step 204: growing an oxide layer on the surface of the epitaxial layer.

[0121] Step 205 , implanting N-type ions into the epitaxial layer corresponding to the lower part of both sides of the first trench to form a first N region; the first N region is located below both sides of the first trench.

[0122] Step 206, injecting P-type ions into the epitaxial layer corresponding to both sides of the first trench to form a P-well region, and injecting N-type ions to form an N+ region; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are respectively connected to the side walls of the first trench.

[0123] Step 207 , etching a second trench at the bottom of the first trench.

[0124] Step 208: forming a gate in the first trench and forming a source in the second trench, wherein the gate is located on both sides of the source, and an oxide layer is formed around the gate and the source.

[0125] Step 209, in the first cross-sectional area, N-type ions are injected into the epitaxial layer below the two sides of the first trench to form a first N region, and P-type ions are injected into the epitaxial layer below the first trench to form a P region; the first N region and the P region are located in the same layer.

[0126] Step 210, in the third cross-sectional area, N-type ions are injected into the epitaxial layer below the two sides of the first trench to form a first N region, and P-type ions are injected into the epitaxial layer below the first trench to form a P region; the P region is connected to the bottom of the first trench.

[0127] Specifically, the N-type substrate 101 and the epitaxial layer 102 are made of SiC material. Figure 6 , an epitaxial layer 102 is grown on one side of the N-type substrate 101; Figure 7 , etching a first trench 103 on the epitaxial layer 102, and growing an oxide layer on the surface of the epitaxial layer 102; Figure 8 , deep implantation is performed to implant N-type ions into the epitaxial layer 102 corresponding to the lower part of both sides of the first trench 103 to form a first N region 105, wherein the first N region 105 is located below both sides of the first trench 103; Fig. 9 , near-surface implantation is performed, P-type ions are implanted into the epitaxial layer 102 corresponding to both sides of the first trench 103 to form a P-well region 106, and N-type ions are implanted to form an N+ region 107, wherein the P-well region 106 is connected to the bottom of the N+ region 107, and the P-well region 106 and the N+ region 107 are respectively connected to the sidewalls of the first trench 103; Fig.10 , a second trench 108 is etched at the bottom of the first trench 103; Fig.11 , a gate 109 is formed in the first trench 103, a source 110 is formed in the second trench 108, the gate 109 is located on both sides of the source 110, and an oxide layer 104 is formed around the gate 109 and the source 110; Fig. 9 , in the first cross-sectional area 10, when N-type ions are implanted below the two sides of the first trench 103 in the epitaxial layer 102 to form the first N region 105, P-type ions are implanted below the first trench 103 in the epitaxial layer 102 to form the P region 111, and the P region 111 of the third cross-sectional area 30 is shallower than the P region 111 of the first cross-sectional area 10; the first N region 105 and the P region 111 are located in the same layer; refer to Fig.12In the third cross-sectional area 30, when N-type ions are injected into the epitaxial layer 102 below the two sides of the first trench 103 to form a first N region 105, P-type ions are injected into the epitaxial layer 102 below the first trench 103 to form a P region 111; the P region 111 is connected to the bottom of the first trench 103.

[0128] A trench MOSFET device according to an embodiment of the present invention comprises a first cross-sectional area, a second cross-sectional area and a third cross-sectional area arranged alternately along a first direction; the first cross-sectional area, the second cross-sectional area and the third cross-sectional area all comprise: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N region, a P-well region, an N+ region, a second trench, a gate and a source; the epitaxial layer is arranged on one side of the N-type substrate; the first N region is located below both sides of the first trench; the N+ region is located on both sides of the first trench; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are connected to the first trench, respectively. The second trench is located at the bottom of the first trench; the gate is embedded in the first trench; the source is embedded in the second trench; the gate is located on both sides of the source; the oxide layer is arranged in the first trench and the second trench, wrapping the gate and the source; the first cross-sectional area also includes: a P region located below the first trench, the P region and the first N region are located in the same layer; the second trench extends to the inside of the P region; the third cross-sectional area also includes: a P region located below the first trench, the P region is connected to the bottom of the first trench; the second trench runs through the P region. The embodiment of the present invention uses the electric field shielding effect of the P region located at the bottom and corner of the second trench in the first cross-sectional area, and the electric field shielding effect of the P region located at the bottom of the first trench in the third cross-sectional area, thereby avoiding device damage caused by a strong electric field at the corner of the trench, thereby improving the reliability of the device.

[0129] In an embodiment of the present invention, the method further includes:

[0130] Reference Fig. 9 , when P-type ions are injected into the epitaxial layer 102 corresponding to both sides of the first trench 103 to form a P-well region 106, and N-type ions are injected into the epitaxial layer 102 to form an N+ region 107, that is, when near-surface injection is performed, P-type ions are injected into the epitaxial layer 102 corresponding to both sides of the first trench 103 to form a P+ region 112, and the P+ region 112 and the N+ region 107 are located in the same layer and connected to the N+ region 107. The near-surface injection of the first cross-sectional area 10 and the third cross-sectional area 30 is the same, and both form a P-well region 106, a P+ region 112 and an N+ region 107 in the same position.

[0131] Reference Fig.13In the second cross-sectional area 20, P-type ions are injected into the epitaxial layer 102 at both sides of the first trench 103 to form a P-well region 106, and N-type ions are injected into the epitaxial layer 102 to form an N+ region 107. N-type ions are injected into the epitaxial layer 102 at both sides of the first trench 103 to a depth that is connected to the first N region 105 to form a second N region 113; the second N region 113 is connected to the N+ region 112 and the P-well region 106.

[0132] In the embodiment of the present invention, the gate 109 is formed in the first trench 103, the source 110 is formed in the second trench 108, the gate 109 is located on both sides of the source 110, and an oxide layer 104 is formed around the gate 109 and the source 110, including:

[0133] Reference Fig.10 , the oxide layer on the surface of the epitaxial layer 102 is removed, and a gate oxide layer 104 is grown on the surfaces of the first trench 103 and the second trench 108 .

[0134] Reference Fig.14 , polysilicon is deposited on the surface of the epitaxial layer 102 , so as to deposit polysilicon in the first trench 103 and the second trench 108 .

[0135] Reference Fig.15 , the polysilicon on the surface of the epitaxial layer 102 is etched, and the polysilicon on both sides of the first trench 103 is retained as the gate 109.

[0136] Reference Fig.15 , growing an oxide layer 104 in the first trench 103 and the second trench 108; etching the oxide layer 104 in the first trench 103 and the second trench 108 to form a groove in the oxide layer 104, and retaining the oxide layer covering the surface of the gate 109 and the second trench 108;

[0137] Reference Fig.17 , polysilicon is deposited in the groove as the source 110 ; an oxide layer 104 is formed around the gate 109 and the source 110 .

[0138] In an embodiment of the present invention, the oxide layer 104 is formed around the gate 109 and the source 110, including:

[0139] In the first cross-sectional area 10, an oxide layer 104 is grown in the first trench 103 and the second trench 108;

[0140] Reference Fig.18, in the second cross-sectional area 20 , growing an oxide layer 104 in the first trench 103 and the second trench 108 , and removing the oxide layer 104 on the surface of the source 110 ;

[0141] Reference Fig.19 In the third cross-sectional area 30, an oxide layer 104 is grown in the first trench 103 and the second trench 108, and polysilicon is deposited on the surface of the epitaxial layer 102 so that the gates 109 on both sides of the first trench 103 are connected through the polysilicon, and the polysilicon on the surface of the epitaxial layer 102 except for the first trench 103 and the second trench 108 is removed.

[0142] In an embodiment of the present invention, the method further includes:

[0143] Reference Fig. 20 , depositing insulating material on the surface of the epitaxial layer 102 to form an interlayer dielectric passivation layer 114; removing the interlayer dielectric passivation layer above a portion of the N+ region and above the P+ region to serve as a contact hole.

[0144] Reference Fig.21 , depositing a first metal layer 115 on the surface of the contact hole; and depositing a second metal layer 116 on the surface of the first metal layer 115 and the interlayer dielectric passivation layer 114 .

[0145] In an embodiment of the present invention, the method further includes:

[0146] Reference Fig. 22 , thinning the other side of the N-type substrate 101;

[0147] Metal is deposited on the other side of the N-type substrate 101 as a drain 117 .

[0148] The first cross-sectional area 10 of the embodiment of the present invention is made into polysilicon connected to the gate and polysilicon connected to the source through multi-level grooves, and a thicker oxide layer is deposited under and on both sides of the polysilicon connected to the source, thereby increasing Cgs, reducing Cgd, and lowering the ratio of Cgd / Ciss, thereby improving the dv / dt processing capability during switching and improving the switching stability of the device. Moreover, the P region 111 deeply implanted in the first cross-sectional area 10 is located below the second trench 108, which can play an electric field shielding role to avoid the generation of a strong electric field at the corner of the second trench 108 (the weak point of the chip structure) to damage the chip.

[0149] In the second cross-sectional area 20, the polysilicon is connected to the source metal on the front side. At the same time, during deep implantation, P-type ion implantation is not performed, but during near-surface implantation, N-type ion implantation is performed and connected to the N-type ion area during deep implantation, so that a Schottky contact is formed at the parasitic diode of the MOSFET, which has a smaller on-resistance.

[0150] In the third cross-sectional area 30, the polysilicon on both sides are connected together through the top and finally connected to the gate. At the same time, the P-type ions during deep implantation are located below the first trench 103 and above the bottom of the second trench 108, which can better shield the electric field at the bottom corner of the first trench 103.

[0151] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0152] An embodiment of the present invention provides a chip, comprising the trench MOSFET device as described above.

[0153] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0154] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0155] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0156] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0158] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0159] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0160] The trench MOSFET device, manufacturing method and chip provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A trench MOSFET device, characterized in that: The device comprises a first cross-sectional area, a second cross-sectional area and a third cross-sectional area alternately arranged along a first direction; The first cross-sectional area, the second cross-sectional area and the third cross-sectional area each include: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N region, a P well region, an N+ region, a second trench, a gate and a source; The epitaxial layer is disposed on one side of the N-type substrate; the first N region is located below both sides of the first trench; The N+ region is located on both sides of the first trench; The P-well region is connected to the lower part of the N+ region; the P-well region and the N+ region are connected to the sidewalls of the first trench respectively; The second groove is located at the bottom of the first groove; The gate is embedded in the first trench; the source is embedded in the second trench; the gate is located on both sides of the source; The oxide layer is disposed in the first trench and the second trench, and wraps the gate and the source; The first cross-sectional area further includes: a P region located below the first trench, the P region and the first N region are located in the same layer; the second trench extends to the inside of the P region; The third cross-sectional area further includes: a P region located below the first trench, the P region being connected to the bottom of the first trench; and the second trench penetrating the P region.

2. The trench MOSFET device according to claim 1, characterized in that: The device further comprises: The first cross-sectional area and the third cross-sectional area both further include: a P+ region disposed on both sides of the first trench in the epitaxial layer, the P+ region being located in the same layer as the N+ region and being connected to the N+ region; The second cross-sectional area further includes: a second N region disposed in the epitaxial layer on both sides of the first trench, the second N region having a depth connected to the first N region, and the second N region being connected to the N+ region and the P well region.

3. The trench MOSFET device according to claim 2, characterized in that: The device further comprises: An interlayer dielectric passivation layer disposed on the surface of the epitaxial layer; Contact holes provided on both sides of the interlayer dielectric passivation layer; A first metal layer is disposed on the surface of the contact hole; the first metal layer is in contact with a portion of the P+ region and the N+ region; A second metal layer is provided on the surface of the first metal and the interlayer dielectric passivation layer.

4. The trench MOSFET device according to claim 1, characterized in that: The device further includes: a drain located on the other side of the N-type substrate.

5. A method for manufacturing a trench MOSFET device, characterized in that: For manufacturing a trench MOSFET device according to any one of claims 1 to 4, the method comprising: Providing an N-type substrate; growing an epitaxial layer on one side of the N-type substrate; Etching a first trench on the epitaxial layer; growing an oxide layer on the surface of the epitaxial layer; Injecting N-type ions into the epitaxial layer corresponding to the lower part of both sides of the first trench to form a first N region; the first N region is located below both sides of the first trench; In the epitaxial layer, P-type ions are injected into both sides of the first trench to form a P-well region, and N-type ions are injected into the epitaxial layer to form an N+ region; the P-well region is connected to the bottom of the N+ region; the P-well region and the N+ region are respectively connected to the sidewalls of the first trench; Etching a second groove at the bottom of the first groove; A gate is formed in the first trench, and a source is formed in the second trench, wherein the gate is located at both sides of the source, and an oxide layer is formed around the gate and the source; In the first cross-sectional area, when N-type ions are implanted below the two sides of the first trench in the epitaxial layer to form a first N region, P-type ions are implanted below the first trench in the epitaxial layer to form a P region; the first N region and the P region are located in the same layer; In the third cross-sectional area, when N-type ions are implanted below the two sides of the first trench in the epitaxial layer to form a first N region, P-type ions are implanted below the first trench in the epitaxial layer to form a P region; the P region is connected to the bottom of the first trench.

6. The method for manufacturing a trench MOSFET device according to claim 5, characterized in that: The method further comprises: Injecting P-type ions into the epitaxial layer at both sides of the first trench to form a P-well region, and injecting N-type ions into the epitaxial layer to form an N+ region. Injecting P-type ions into the epitaxial layer at both sides of the first trench to form a P+ region, wherein the P+ region is located in the same layer as the N+ region and is connected to the N+ region; In the second cross-sectional area, P-type ions are injected into the epitaxial layer at both sides corresponding to the first trench to form a P-well region, and N-type ions are injected into the epitaxial layer at both sides corresponding to the first trench to form an N+ region. N-type ions are injected into the epitaxial layer at both sides corresponding to the first trench to a depth that is connected to the first N region to form a second N region; the second N region is connected to the N+ region and the P-well region.

7. The method for manufacturing a trench MOSFET device according to claim 5, characterized in that: The method comprises forming a gate in the first trench, forming a source in the second trench, the gate being located at both sides of the source, and an oxide layer being formed around the gate and the source, comprising: Removing the oxide layer on the surface of the epitaxial layer, and growing a gate oxide layer on the surface of the first trench and the second trench; Depositing polysilicon on the surface of the epitaxial layer to deposit polysilicon in the first trench and the second trench; Etching the polysilicon on the surface of the epitaxial layer, and retaining the polysilicon on both sides of the first trench as a gate; growing an oxide layer in the first trench and the second trench; Etching the oxide layer in the first trench and the second trench to form a groove in the oxide layer, and retaining the oxide layer covering the surface of the gate and the second trench; Depositing polysilicon in the groove as a source electrode; An oxide layer is formed around the gate and the source.

8. The method for manufacturing a trench MOSFET device according to claim 7, characterized in that: The step of forming an oxide layer around the gate and the source includes: In the first cross-sectional area, growing an oxide layer in the first trench and the second trench; In the second cross-sectional area, an oxide layer is grown in the first trench and the second trench, and the oxide layer on the surface of the source electrode is removed; In the third cross-sectional area, an oxide layer is grown in the first trench and the second trench, and polysilicon is deposited on the surface of the epitaxial layer so that the gates on both sides of the first trench are connected through the polysilicon, and the polysilicon on the surface of the epitaxial layer except the first trench and the second trench is removed.

9. The method for manufacturing a trench MOSFET device according to claim 6, characterized in that: The method further comprises: Depositing an insulating material on the surface of the epitaxial layer to form an interlayer dielectric passivation layer; Remove the interlayer dielectric passivation layer above the N+ region and above the P+ region to form a contact hole Depositing a first metal layer on the surface of the contact hole; A second metal layer is deposited on the surface of the first metal and the interlayer dielectric passivation layer.

10. The method for manufacturing a trench MOSFET device according to claim 5, characterized in that: The method further comprises: Thinning the other side of the N-type substrate; A metal is deposited on the other side of the N-type substrate as a drain.

11. A chip, characterized in that: The invention comprises a trench MOSFET device as claimed in any one of claims 1 to 4.

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