MOS structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor preparation processes, and provides an MOS structure and a preparation method thereof, and the preparation method of the MOS structure comprises the steps: providing a substrate initial body; the substrate initial body comprises an active region defined by a shallow trench isolation structure; forming a lower concave hole in the surface of the active region; forming an oxide layer on the side wall and the bottom of the lower concave hole, and filling a gate material to form a gate structure initial body; cutting the initial body of the gate structure and the initial body of the substrate in a direction perpendicular to the arrangement direction of the active region to obtain the gate structure and the substrate of the MOS structure; wherein the downward concave part is formed by part of the side wall and part of the bottom of the downward concave hole; wherein a contact surface formed by the contact of the gate structure and the side wall of the downward concave part is a non-planar surface. Therefore, the short channel effect of the MOS structure can be improved to a certain extent.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing process technology, and more particularly to a MOS structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the size of transistors has been continuously reduced. At present, the process node of transistors can reach 2nm or even 0.3nm.

[0003] The reduction of process nodes allows more transistors to be accommodated per unit area, thus achieving higher density integration and improving chip performance. However, there are also technical problems that need to be solved, such as the short channel effect of MOSFET (metal-oxide-semiconductor field-effect transistor, MOS). The short channel effect affects the on and off characteristics of the transistor and increases leakage current. As the size of MOSFET decreases, its short channel effect may become more obvious, reducing the performance and reliability of MOSFET. Summary of the invention

[0004] In view of this, multiple embodiments of the present application are directed to providing a MOS structure and a method for manufacturing the same, which can improve the short channel effect of the MOS structure to a certain extent.

[0005] An embodiment of the present application provides a MOS structure, comprising: a substrate; a concave portion formed on the surface of the substrate, and a concave portion also has a concave portion formed on a side surface adjacent to the substrate surface; a gate structure; the gate structure is embedded in the concave portion; wherein a contact surface formed by the gate structure contacting the side wall of the concave portion is non-planar.

[0006] Optionally, the substrate and gate structure of the MOS structure are obtained by cutting the gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

[0007] Optionally, a contact contour line is formed at the junction of the contact surface and the substrate surface, and the contact contour line has a bent morphology.

[0008] Optionally, a contact contour line is formed at the junction of the contact surface and the substrate surface, and the contact contour line is in an arc shape.

[0009] Optionally, source and drain regions are formed in the substrate and are located on both sides of the contact surface; wherein an extension direction of the channel between the source and drain regions is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel is greater than the spacing between the source and drain regions.

[0010] Optionally, contact holes are provided on the source and drain regions and the gate structure; wherein the contact holes are filled with metal material, and a connection layer covered by the metal material is formed on the sidewalls and bottom of the contact holes; wherein a contact connection layer is also provided between the contact holes on the source and drain regions and the source and drain regions.

[0011] Optionally, an extension direction of the channel is parallel to a surface of the substrate.

[0012] Another embodiment of the present application provides a method for preparing a MOS structure, the method being used to prepare the MOS structure as described above; the method comprising: providing a substrate precursor; the substrate precursor comprising an active area defined by a shallow trench isolation structure; making a recessed hole on the surface of the active area; forming an oxide layer on the sidewall and bottom of the recessed hole, and filling a gate material to form a gate structure precursor; cutting the gate structure precursor and the substrate precursor perpendicular to the arrangement direction of the active area to obtain the gate structure and substrate of the MOS structure; wherein part of the sidewall and part of the bottom of the recessed hole form the recessed portion.

[0013] Optionally, in the step of cutting the gate structure precursor and the substrate precursor perpendicularly to the arrangement direction of the active area, the cutting surface passes through the center of the gate structure precursor.

[0014] Optionally, the method for preparing the MOS structure also includes: forming source and drain regions on both sides of the contact surface in the substrate; wherein an extension direction of the channel between the source and drain regions is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel is greater than the spacing between the source and drain regions; forming a contact bonding layer on the surface of the source and drain regions, and making contact holes on the surface of the contact bonding layer and the surface of the gate structure; forming a connecting layer on the sidewall and bottom of the contact hole, and filling it with metal material; wherein the connecting layer is covered by the metal material.

[0015] The unexpected effect of the multiple embodiments provided by the present application is that a gate structure precursor filled in a recessed hole is formed on the surface of the active area of ​​the substrate precursor, and a MOS structure consisting of a gate structure and a substrate is obtained after cutting. In the MOS structure thus prepared, the gate structure is embedded in the recessed portion of the substrate, and the contact surface between the gate structure and the substrate is a part of the side wall of the recessed hole, so that the channel length of the MOS structure is increased while occupying the same wafer area, and the short channel effect can be improved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a method for preparing a MOS structure provided in an embodiment of the present application.

[0017] Figure 2 and Figure 3 A schematic diagram of a substrate initial body is provided in the method for preparing the MOS structure provided in an embodiment of the present application.

[0018] Figure 4 A schematic diagram of making a recessed hole in the method for preparing a MOS structure provided in an embodiment of the present application.

[0019] Figure 5 A schematic diagram of forming an oxide layer in the method for preparing a MOS structure provided in an embodiment of the present application.

[0020] Figure 6 A schematic diagram of forming a preliminary gate structure in the method for preparing a MOS structure provided in an embodiment of the present application.

[0021] Figure 7 A schematic diagram of forming a MOS structure in the method for preparing a MOS structure provided in an embodiment of the present application.

[0022] Figure 8 A schematic cross-sectional view of a substrate in a method for preparing a MOS structure provided in an embodiment of the present application.

[0023] Fig. 9 A three-dimensional reference schematic diagram of a substrate in a method for preparing a MOS structure provided in an embodiment of the present application.

[0024] Fig.10 A schematic cross-sectional view of a MOS structure in a method for preparing a MOS structure provided in an embodiment of the present application.

[0025] Fig.11 A three-dimensional reference schematic diagram of a MOS structure in a method for preparing a MOS structure provided in an embodiment of the present application.

[0026] Fig.12 A schematic diagram of forming source and drain regions in the method for preparing a MOS structure provided in an embodiment of the present application.

[0027] Fig.13 A schematic diagram of making a contact connection layer and a contact hole in a method for preparing a MOS structure provided in an embodiment of the present application.

[0028] Description of reference numerals: 10. Substrate precursor; 11. Shallow trench isolation structure; 12. Active area; 13. Recessed hole; 14. Oxide layer; 15. Gate material; 16. Gate structure precursor; 17. MOS structure; 121. Substrate; 161. Gate structure; 18. Recessed part; 131. Part of the side wall; 132. Part of the bottom; 101. Deep well area; 102. Well area; 21. Contact contour line; 103. Source and drain area; 22. Contact connection layer; 23. Metal material; 24. Connection layer; aa. Arrangement direction of active area; bb. Extension direction of channel. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0030] In the present application, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0031] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as those generally understood by those skilled in the art of the technical field of this application. The terms used in this application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above-mentioned" and "the" used in the embodiments of this application are also intended to include majority forms, unless the context clearly indicates other meanings.

[0032] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0033] In the description of the present application, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of simplified description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0034] In the description of this application, unless otherwise clearly defined, the terms "install", "connect", "connect", "fix", "set", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] In related technologies, in order to add more transistors within a limited area and improve chip performance and operating speed, the process nodes of semiconductor manufacturing are also shrinking.

[0036] As the size of transistors decreases, problems such as the short channel effect become more prominent. The short channel effect weakens the electric field control ability of the transistor, increases leakage current, and severely limits performance. In response to this, the industry has gradually introduced new MOS structures such as FinFET and GAA (Gate-All-Around) to alleviate the short channel effect. These new MOS structures can improve the control effect of the electric field through three-dimensional structural design, such as the full-surround gate design of the GAA structure, and thus effectively alleviate the short channel effect.

[0037] However, although these new MOS structures can alleviate the short channel effect and improve the performance of the MOS structure to a certain extent, the structural changes make their preparation process more complicated. For example, the fin structure of FinFET requires the formation of multiple vertical fins on the wafer. The spacing and height between these fins need to be precisely controlled, so additional photolithography and etching steps are required. The preparation process is more complicated than the traditional MOS structure and may require more wafer area.

[0038] Therefore, it is necessary to provide a method for preparing a MOS structure, which can prepare a MOS structure capable of improving the short channel effect while occupying the same wafer area.

[0039] See also Figure 1-Figure 13 An embodiment of the present application provides a method for preparing a MOS structure. The MOS structure may be a basic structure consisting of a substrate and a gate formed on the substrate, or may be a semiconductor structure formed after a back-end process such as an ion implantation process, a contact hole process, etc. The method for preparing the MOS structure may include the following steps.

[0040] S110: Providing a substrate preliminary body. The substrate preliminary body includes an active area defined by a shallow trench isolation structure.

[0041] In this embodiment, reference Figure 2 and Figure 3 The substrate precursor 10 can be used as the basic structure of the MOS structure, not only for providing mechanical support, but also for affecting the electrical properties of the MOS structure, such as threshold voltage and carrier mobility, by doping ions. Specifically, the substrate precursor 10 can be made of silicon (Si), or can be made of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), etc., according to requirements.

[0042] In this embodiment, if Figure 2 and Figure 3 As shown in , a shallow trench isolation structure 11 can be first produced, and the position and size of the active area 12 can be defined by the shallow trench isolation structure 11, and then a well region can be formed by ion doping to obtain a substrate preliminary body 10. Depending on the type of MOS structure prepared, the ion doping type of the well region is different. For example, for an NMOS structure, the ion doping type of the well region is P-type. For a PMOS structure, the ion doping type of the well region is N-type. In some embodiments, before forming the well region, a deep well region can also be formed by doping ions of the opposite ion doping type to the well region. The well region can be located on the deep well region. For example, for an NMOS structure, the ion doping type of the deep well region is N-type. For a PMOS structure, the ion doping type of the deep well region is P-type.

[0043] In this embodiment, the shallow trench isolation structure 11 (STI) is used to form effective electrical isolation between different active regions 12 by etching a shallow trench in the substrate body 10 and filling it with an insulating material, such as silicon dioxide SiO2, so as to reduce parasitic capacitance and leakage current and improve the performance and reliability of the MOS structure. For example, in the CMOS process, the shallow trench isolation structure 11 can effectively isolate NMOS and PMOS, prevent parasitic capacitance and leakage current between them, ensure that each MOS works independently, and thus improve the speed and stability of the circuit.

[0044] In this embodiment, if Figure 3 As shown, a plurality of active areas 12 (Active Area) can be divided on the substrate body 10 through the shallow trench isolation structure 11. The area between adjacent shallow trench isolation structures 11 is the active area 12. The active area 12 can be used as a specific area for manufacturing transistors and other active devices.

[0045] S120: making a recessed hole on the surface of the active area.

[0046] In this embodiment, if Figure 4As shown, a concave lower hole 13 can be etched on the surface of the active area 12 by photolithography and etching processes. Specifically, the size of the lower lower hole 13 can be flexibly set according to actual needs, and this application does not make specific limitations on this. In this embodiment, the lower recessed hole 13 may be formed with a hole profile on the surface of the active region 12. Specifically, the shape of the hole profile may be an ellipse, a polygon, etc. In some embodiments, the depth of the lower recessed hole 13 relative to the surface of the active region 12 may be less than the thickness of the well region, that is, the lower recessed hole 13 does not penetrate the well region.

[0047] In some embodiments, the hole profile of the lower recessed hole 13 is circular, and the diameter of the hole profile of the lower recessed hole 13 may be three times the gate width in a conventional MOS structure.

[0048] S130: forming an oxide layer on the sidewall and the bottom of the lower recessed hole, and filling the gate material to form a preliminary gate structure.

[0049] In this embodiment, reference Figure 4 and Figure 5 , the furnace tube process can be used to grow oxide in the lower recessed hole 13, and the area where the oxide does not need to be grown is blocked by a hard mask. Among them, oxide will grow on the sidewalls and the bottom of the lower recessed hole 13 to form an oxide layer 14. Specifically, the thickness of the oxide layer 14 can be flexibly set according to actual needs by controlling the duration of the furnace tube process. For example, if a MOS structure for a high-voltage device needs to be prepared, the furnace tube is applied for a longer time to make the thickness of the oxide layer 14 thicker.

[0050] In this embodiment, the gate structure precursor 16 can be used to affect the switching state of the MOS structure. Specifically, the gate structure precursor 16 can be composed of a gate material 15 and a gate oxide layer. As a gate electrode, the gate material 15 can be polysilicon or a metal (such as aluminum Al). The gate material 15 can be isolated from the substrate precursor 10 by the gate oxide layer. The material of the gate oxide layer can specifically be silicon dioxide SiO2. When a voltage is applied to the gate structure precursor 16, carriers in the channel region can be attracted or repelled, thereby affecting the flow of carriers.

[0051] In this embodiment, please refer to Figure 4 , Figure 5 and Figure 6 , a gate material 15 is filled in the lower recess 13 formed with the oxide layer 14, and the gate material 15 is polished by CMP to form a gate structure precursor 16 composed of the gate material 15 and the oxide layer 14 on the side wall of the lower recess 13 as a gate oxide layer. Specifically, in the gate structure precursor 16, the height of the gate material 15 can be flush with the surface of the substrate precursor 10, or can be higher than the surface of the substrate precursor 10.

[0052] S140: perpendicular to the arrangement direction of the active area, the gate structure initial body and the substrate initial body are cut to obtain a MOS structure composed of the gate structure and the substrate. The substrate includes a concave portion formed by a part of the sidewall and a part of the bottom of the concave hole; the gate structure is filled in the concave portion; the gate structure contacts the sidewall of the concave portion, and the contact surface is non-planar.

[0053] In this embodiment, reference Figure 6 and Figure 7 , cutting is performed perpendicular to the arrangement direction aa of the active area 12, wherein the cutting plane passes through the substrate precursor 10 and the gate structure precursor 16 at the same time, so as to simultaneously cut the gate structure precursor 16 and the substrate precursor 10. Specifically, for example, for polycrystalline silicon gate material, a poly-cut process can be used to define the shape of a poly-cut at the center of the gate structure precursor 16, and then cut to obtain two independent MOS structures 17. Each MOS structure 17 is respectively composed of the cut substrate 121 and the gate structure 161.

[0054] In this embodiment, the cutting surface for cutting the gate structure precursor 16 and the substrate precursor 10 can pass through the center of the gate structure precursor 16 to obtain a MOS structure 17 with a gate structure 161 of the same size, or can pass through other positions of the gate structure precursor 16 to obtain a MOS structure 17 with a gate structure 161 of different sizes. The specific cutting surface can be flexibly adjusted according to actual needs.

[0055] In this embodiment, please refer to Figure 4 as well as Figures 7 to 11 , Figure 8 and Fig.10 Along Figure 7 A schematic cross-sectional view of the substrate 121 and the MOS structure 17 at the dotted line position, wherein: Figure 8 is a schematic diagram of a substrate 121, Fig.10 The schematic diagram of the MOS structure 17 is composed of the gate structure 161 and the substrate 121. The substrate 121 may be formed with a well region 102 and a deep well region 101. Fig. 9 and Fig.11 1 and 2 are three-dimensional reference images of the substrate 121 and the MOS structure 17, respectively. Since the lower recessed hole 13 filled with the gate structure precursor 16 is also cut when the gate structure precursor 16 is cut, Figure 8 and Fig. 9 As shown in FIG. 1 , part of the sidewall 131 and part of the bottom 132 of the recessed hole 13 respectively form a recessed portion 18 in the cut substrate 121. In the cut MOS structure 17, the Figure 7 , Figure 8 and Fig. 9The gate structure 161 is embedded in the concave portion 18. The contact surface between the gate structure 161 and the concave portion 18 is the side wall of the concave portion 18, that is, part of the side wall 131 of the concave hole 13. It can be understood that the contact surface is a non-planar surface.

[0056] In this embodiment, an unexpected effect is that a gate structure precursor 16 filled in the recessed hole 13 is formed on the surface of the active area 12 of the substrate precursor 10, and a MOS structure 17 consisting of a gate structure 161 and a substrate 121 is obtained after cutting. In the MOS structure 17 thus prepared, the gate structure 161 is embedded in the recessed portion 18 of the substrate 121, and the contact surface between the gate structure 161 and the substrate 121 is a part of the side wall 131 of the recessed hole 13, so that under the same size, the channel length of the MOS structure 17 is increased, and the short channel effect can be improved to a certain extent.

[0057] In addition, the MOS structure 17 provided in this embodiment has a high utilization rate of the active area under the premise of the pre-defined active area size. At the same time, a single MOS structure 17 occupies less active area and has a lower process complexity, which can improve process flexibility under the premise of the same wafer area.

[0058] In some embodiments, the contact surface forms a contact contour line on the surface of the substrate, and the contact contour line has a bent morphology.

[0059] In some embodiments, reference Figure 4 and Figure 7 In the prepared MOS structure 17, the contact surface between the gate structure 161 and the substrate 121 can form a contact contour line 21 on the surface of the substrate 121. Since the contact surface is a part of the side wall 131 of the lower recessed hole 13 during the preparation process, the shape of the contact contour line 21 can depend on the shape of the hole contour of the lower recessed hole 13. Specifically, the shape of the contact contour line 21 of the contact surface can be any shape with bends, such as a fold line with one bend or multiple bends. In this way, the channel of the MOS structure 17 can be extended along the contact contour line 21, and then the channel length can be increased under the same size conditions.

[0060] In some embodiments, the contact surface forms a contact contour line on the substrate surface, and the contact contour line is in an arc shape.

[0061] In some embodiments, please refer to Figure 4 and Figure 7 In the case where the hole contour of the lower recessed hole 13 is circular, it can be understood that in the MOS structure 17 obtained after cutting, the contact contour line 21 of the contact surface between the gate structure 161 and the substrate 121 can be in an arc shape.

[0062] In some embodiments, when the contact contour line 21 is in an arc shape, the channel of the MOS structure 17 can be made smoother. Compared with shapes such as a fold line, the occurrence of tip discharge due to an insufficiently smooth channel can be reduced.

[0063] In some embodiments, the method for preparing the MOS structure may further include: forming source and drain regions in the substrate located on both sides of the contact surface; wherein an extension direction of the channel between the source and drain regions is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel is greater than the spacing between the source and drain regions.

[0064] In some embodiments, reference Fig.12 ,against Figure 7 The MOS structure 17 shown in the figure can also form source and drain regions 103 in the substrate on both sides of the gate structure 161 through an ion implantation process. In some embodiments, a lightly doped region (LDD) and a pocket region (Pocket) can also be formed between the source and drain regions 103 and the gate structure 161. In this way, the channel length of the MOS structure 17 formed between the source and drain regions 103 can be greater than the spacing between the source and drain regions 103, that is, the channel length under the same size condition is increased, thereby improving the short channel effect. Figure 4 Taking the preparation process in which the hole contour of the concave hole 13 is circular and the cutting surface passes through the center of the gate structure primary body 16 as an example, the diameter of the hole contour can be 40nm, then the channel length of the MOS structure 17 can be 62.8nm, and the channel length is increased by 57%.

[0065] In some embodiments, the extension direction of the channel may be parallel to the surface of the substrate 121 .

[0066] In some embodiments, after forming the source and drain regions 103, Fig.13 As shown, a contact layer 22 can be further formed on the surface of the source and drain regions 103 to serve as a contact between the metal material and the source and drain regions 103 to reduce the contact resistance of the source and drain regions. Specifically, the contact layer can be made of metal silicide, such as silicon nickel.

[0067] Then, contact holes can be made on the surface of the metal silicide 22 corresponding to the source and drain regions 103 and the surface of the gate structure 161, and metal material 23, such as metal tungsten, can be filled in the contact holes. In some embodiments, a connection layer 24 that wraps the metal material can also be provided on the sidewalls and bottom of the contact hole. Specifically, the connection layer 24 can be located between the contact hole and the metal material 23. The connection layer 24 can be composed of metal titanium and titanium nitride. The connection layer 24 can prevent the diffusion of the metal material 23 and can increase adhesion.

[0068] An embodiment of the present application provides a MOS structure, and the MOS structure can be prepared by using the MOS structure preparation method described in the above embodiment. Specifically, in this embodiment, Figures 7 to 11 As shown in , the MOS structure 17 may specifically include: a substrate 121 and a gate structure 161 .

[0069] In this embodiment, a concave lower concave portion 18 is formed on the surface of the substrate 121, and the lower concave portion 18 is also concave on the side adjacent to the surface of the substrate 121. It should be noted that the concave direction of the lower concave portion 18 on the surface of the substrate 121 is different from that formed on the side. The concave portion 18 formed on the surface of the substrate 121 extends from the surface of the substrate 121 to the bottom of the lower concave portion 18 (part of the bottom 132 of the lower concave hole 13), while the concave portion 18 formed on the side adjacent to the surface of the substrate 121 extends from the side along the side wall of the lower concave portion 18 (part of the side wall 131 of the lower concave hole 13).

[0070] In this embodiment, the shape of the gate structure 161 can match the concave portion 18 so as to be embedded in the concave portion 18. The contact surface formed by the gate structure 161 contacting the sidewall of the concave portion 18 is a non-planar surface.

[0071] In some embodiments, the substrate and gate structure of the MOS structure are obtained by cutting the gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

[0072] In some embodiments, a contact contour line is formed at the interface between the contact surface and the substrate surface, and the contact contour line has a bent morphology.

[0073] In some embodiments, a contact contour line is formed at the interface between the contact surface and the substrate surface, and the contact contour line is in an arc shape.

[0074] In some embodiments, source and drain regions are further formed in the substrate and are located on both sides of the contact surface; wherein an extension direction of the channel between the source and drain regions is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel is greater than the spacing between the source and drain regions.

[0075] In some embodiments, contact holes are provided on the source and drain regions and the gate structure; wherein the contact holes are filled with metal material, and a connection layer covered by the metal material is formed on the sidewalls and the bottom of the contact holes; wherein a contact connection layer is also provided between the contact holes on the source and drain regions and the source and drain regions.

[0076] In some embodiments, an extension direction of the channel is parallel to a surface of the substrate.

[0077] It should be noted that, in this embodiment, the explanation of the MOS structure and its various parts can refer to the aforementioned embodiments and will not be repeated here.

[0078] In this embodiment, an unexpected effect is that by embedding the gate structure in the recessed portion of the substrate, and the contact surface between the gate structure and the substrate is the non-planar side wall of the recessed portion, the channel length of the MOS structure 17 is increased while maintaining the same size, thereby improving the short channel effect to a certain extent.

[0079] In this embodiment, the MOS structure can also be applied to high-voltage devices, and the breakdown voltage of the high-voltage devices can be increased under the same size conditions.

[0080] It should be understood that the specific examples in this article are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the present invention.

[0081] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0082] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0083] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are identical with the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above-mentioned" and "the" used in the embodiments of the present application are also intended to include majority forms, unless the context clearly indicates other meanings.

[0084] The above description is only a specific embodiment of the present application, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A MOS structure, characterized in that: include: A substrate; a concave portion is formed on the surface of the substrate, and a concave portion is also formed on a side surface adjacent to the substrate surface; A gate structure; the gate structure is embedded in the recess; wherein a contact surface formed by the gate structure contacting the side wall of the recess is non-planar.

2. The MOS structure according to claim 1, characterized in that: The substrate and gate structure of the MOS structure are obtained by cutting the gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

3. The MOS structure according to claim 1, characterized in that: A contact contour line is formed at the interface between the contact surface and the substrate surface, and the contact contour line has a bent morphology.

4. The MOS structure according to claim 1, characterized in that: A contact contour line is formed at the interface between the contact surface and the substrate surface, and the contact contour line is in an arc shape.

5. The MOS structure according to any one of claims 1 to 4, characterized in that: The substrate also has source and drain regions on both sides of the contact surface, wherein the extension direction of the channel between the source and drain regions is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel is greater than the spacing between the source and drain regions.

6. The MOS structure according to claim 5, characterized in that: Contact holes are arranged on the source and drain regions and the gate structure; wherein the contact holes are filled with metal material, and a connection layer covered by the metal material is formed on the sidewalls and bottom of the contact holes; wherein a contact connection layer is also arranged between the contact holes on the source and drain regions and the source and drain regions.

7. The MOS structure according to claim 5, characterized in that: An extension direction of the channel is parallel to a surface of the substrate.

8. A method for preparing a MOS structure, characterized in that: Used to prepare a MOS structure as claimed in any one of claims 1 to 7; the preparation method comprises: Providing a substrate body; the substrate body includes an active area defined by a shallow trench isolation structure; Making a recessed hole on the surface of the active area; An oxide layer is formed on the sidewall and bottom of the lower recessed hole, and a gate material is filled therein to form a gate structure precursor; The gate structure precursor and the substrate precursor are cut perpendicularly to the arrangement direction of the active area to obtain the gate structure and substrate of the MOS structure; wherein part of the sidewall and part of the bottom of the recessed hole form the recessed portion.

9. The method for preparing a MOS structure according to claim 8, characterized in that: In the step of cutting the gate structure precursor and the substrate precursor perpendicularly to the arrangement direction of the active area, the cutting plane passes through the center of the gate structure precursor.

10. The method for preparing a MOS structure according to claim 9, characterized in that: The method for preparing the MOS structure further comprises: Forming source and drain regions on both sides of the contact surface in the substrate; wherein the extension direction of the channel between the source and drain regions is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel is greater than the spacing between the source and drain regions; Forming a contact layer on the surface of the source and drain regions, and making contact holes on the surface of the contact layer and the surface of the gate structure; A connection layer is formed on the sidewall and the bottom of the contact hole and filled with a metal material; wherein the connection layer is covered by the metal material.

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