Preparation method of embedded source-drain selective epitaxial layer
By forming epitaxial trench on the semiconductor substrate and synchronously performing epitaxial deposition and etching in the epitaxial chamber, the growth problem of epitaxial residues in the prior art is solved, and efficient epitaxial layer growth and yield improvement are achieved.
Patent Information
- Application Number
- CN202311401217.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-25
- Publication Date
- 2025-04-29
AI Technical Summary
When the prior art uses selective epitaxial process to form the epitaxial layer of the source and drain region of the MOS tube, epitaxial residues are easily grown on the non-set area interface outside the set source and drain region interface, resulting in the inability to completely remove the subsequent etching steps, which seriously affects the yield.
By forming epitaxial trench on the semiconductor substrate and synchronously performing epitaxial deposition and etching in the epitaxial chamber, using the homologous growth characteristics of the epitaxial process, efficient epitaxial deposition is achieved in the source and drain region, and at the same time, epitaxial residues are effectively removed through secondary reinforcement etching in the outside of the source and drain region.
The epitaxial layer is achieved to grow freely only in the source and drain region, while there is no epitaxial residue growth outside the source and drain region interface, effectively improving the yield of MOS devices.
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Figure CN119907293A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for preparing an embedded source-drain selective epitaxial layer. Background Art
[0002] In the field of semiconductor integrated circuit manufacturing technology, with the development of semiconductor technology, the characteristic dimensions of various semiconductor devices are constantly decreasing, and CMOS technology has entered the critical dimensions of 28nm and below, and the requirements for the performance of semiconductor devices are getting higher and higher. Stress channel transistors have been widely studied in the integrated circuit industry. They use embedded epitaxial layers in the source and drain regions of MOS tubes to change the stress in the channel region, thereby improving the mobility of carriers and thus improving the performance of the device. For example, for PMOS devices, currently, the hole channel mobility of PMOS devices is usually improved by forming a silicon germanium epitaxial layer through an embedded silicon germanium epitaxial process, thereby improving the performance of PMOS devices.
[0003] However, when the epitaxial layer of the source and drain regions of the MOS tube is formed by a selective epitaxial process, epitaxial residues (selectivity loss) are easily grown on the interface of the non-set region outside the set source and drain region interface, so that the subsequent etching step cannot etch the epitaxial residues cleanly, seriously affecting the yield. For example, when a PMOS device is formed by growing an embedded silicon germanium epitaxial layer, silicon germanium residues will grow on the top corners and / or sidewalls of the gate structure of the PMOS device. Summary of the invention
[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing an embedded source-drain selective epitaxial layer, which is used to solve the problem that when the epitaxial layer of the source and drain regions of a MOS tube is formed by a selective epitaxial process in the prior art, epitaxial residues (selectivity loss) are easily grown on the non-set region interface outside the set source and drain region interface, so that the subsequent etching step cannot etch the epitaxial residues cleanly, seriously affecting the yield.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an embedded source-drain selective epitaxial layer, the preparation method comprising:
[0006] Providing a semiconductor substrate, on which a gate structure and a source / drain region of a MOS tube are formed, and an epitaxial trench is formed in the source / drain region;
[0007] The embedded epitaxial process is performed, including: step one, placing the semiconductor substrate in an epitaxial chamber, and introducing a reaction gas source and an etching gas source into the epitaxial chamber to perform synchronous epitaxial deposition and etching to form a partial embedded epitaxial layer in the epitaxial groove; step two, introducing an etching gas source into the epitaxial chamber to perform secondary enhanced etching; step three, repeating steps one and two until the embedded epitaxial layer reaches a preset thickness.
[0008] Optionally, before the epitaxial trenches are formed in the source and drain regions, the method further includes depositing an epitaxial shielding layer and removing the epitaxial shielding layer on the epitaxial trenches where the embedded epitaxial process is to be performed.
[0009] Optionally, the MOS tube is an NMOS tube or a PMOS tube, and the epitaxial shielding layer is a single-layer structure of a silicon nitride layer or a stacked-layer structure of a silicon oxide layer and a silicon nitride layer.
[0010] Furthermore, when the MOS tube is an NMOS tube, the embedded epitaxial layer is an n-type doped silicon epitaxial layer or an n-type doped silicon carbide epitaxial layer; when the MOS tube is a PMOS tube, the embedded epitaxial layer is a p-type doped silicon germanium epitaxial layer.
[0011] Furthermore, during the embedded epitaxial growth process, the etching gas source in step one is a chlorine-containing gas, and the etching gas source in step two is a chlorine-containing gas.
[0012] Further, when the embedded epitaxial layer is a p-type doped germanium silicon epitaxial layer: the etching gas sources in step one and step two are both chlorine gas; when performing the embedded epitaxial process, the duration of step one is 8s to 20s, the pressure is 0mtorr to 30mtorr, and the temperature is 480℃ to 530℃, including endpoint values, and the duration of step two is 8s to 16s, the pressure is 0mtorr to 30mtorr, and the temperature is 480℃ to 530℃, including endpoint values.
[0013] Furthermore, when the embedded epitaxial process is performed, the flow rate of the chlorine gas introduced in step one is 0.1 sccm to 1 sccm, and the flow rate of the chlorine gas introduced in step two is 1 sccm to 4 sccm, both inclusive.
[0014] Optionally, when the embedded epitaxial layer is an n-type doped silicon epitaxial layer or an n-type doped silicon carbide epitaxial layer: the etching gas sources in step one and step two are both hydrogen chloride gas.
[0015] Optionally, before executing the embedded epitaxial process, the step of pre-cleaning the semiconductor substrate is also included to clean the oxide layer and impurities on the surface; before executing step one of the embedded epitaxial process, the step of pre-treating the semiconductor substrate in the epitaxial chamber to reduce the content of oxygen atoms and carbon atoms on its surface is also included.
[0016] Optionally, when performing the embedded epitaxial process, a carrier gas is also introduced into the epitaxial chamber in step 1 and step 2, and the carrier gas is hydrogen or nitrogen.
[0017] As described above, the preparation method of the embedded source-drain selective epitaxial layer of the present invention performs etching while executing the epitaxial deposition of step one of the embedded epitaxial process. Based on the homologous growth characteristics of the epitaxial process, the nucleation rate in the source-drain region (i.e., in the epitaxial trench) is much greater than the nucleation rate in the region outside the source-drain region (e.g., the epitaxial shielding layer). Therefore, the epitaxial deposition rate in the source-drain region is much greater than the epitaxial deposition rate outside the source-drain region. Generally, the epitaxial deposition stage includes a stable stage, a low-speed deposition stage, and a high-speed deposition stage. At this time, the etching process performed simultaneously can effectively suppress the particle radius of the epitaxial deposition in the region outside the source-drain region from exceeding the critical nucleation radius, so that at the beginning stage of the epitaxial deposition in the source-drain region, the epitaxial stable deposition stage can be easily entered into the epitaxial trench. The fixed stage then enters the low-speed and high-speed deposition stages, while the areas outside the source and drain areas (such as the epitaxial shielding layer) have a slow nucleation rate and are continuously etched, and their nucleation centers are continuously etched, making it impossible for them to grow, and then they are completely etched during the secondary enhanced etching process in step two. Therefore, during the entire embedded epitaxial process, the epitaxial layer in the source and drain areas (i.e., in the epitaxial trenches) can grow stably, while the epitaxial layer in the areas outside the source and drain areas (such as the epitaxial shielding layer) is always in the process of repeatedly forming nucleation centers and then being cleaned by the secondary enhanced etching, thereby achieving the free growth of the epitaxial layer only in the source and drain areas (i.e., in the epitaxial trenches), and the preferential growth mode of the growth of no epitaxial residues on the non-set area interface outside the source and drain area interface, effectively improving the yield of MOS devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a schematic diagram of the cross-sectional structure of epitaxial residues generated on the epitaxial shielding layer after the embedded source-drain selective epitaxial layer is prepared by the CDE (cycled epitaxial etch) method in the prior art.
[0019] Figures 2 to 3 It shows a schematic diagram of the cross-sectional structure of a MOS tube prepared by the method for preparing an embedded source-drain selective epitaxial layer of the present invention.
[0020] Figure 4It shows the three stages that the embedded source-drain selective epitaxial layer will go through during the epitaxial deposition process: a stable stage, a low-speed deposition stage and a high-speed deposition stage; the high-speed deposition stage is only a schematic representation of a certain thickness and is not used as a limitation on the deposition thickness of the high-speed deposition stage.
[0021] Figure 5 It shows a simulation effect diagram of depositing a silicon nitride epitaxial shielding layer on the surface of a bare wafer and then depositing an embedded source-drain selective epitaxial layer on the silicon nitride epitaxial shielding layer using the CDE (cycle dep etch) method in the prior art.
[0022] Figure 6 It shows a simulation effect diagram of depositing an embedded source-drain selective epitaxial layer on the silicon nitride epitaxial shielding layer after depositing a silicon nitride epitaxial shielding layer on the surface of a bare wafer using the embedded epitaxial process in the preparation method of the present invention.
[0023] Component number description
[0024] 10 Semiconductor substrate
[0025] 11 Gate structure
[0026] 12 Source and drain regions
[0027] 13 Epitaxial shielding layer
[0028] 14 Epitaxial trench
[0029] 15 Embedded epitaxial layer
[0030] 150 Stable Layer
[0031] 151 Low-speed layer
[0032] 152 High-speed layer
[0033] 16 Epitaxial Residue
[0034] 17 Embedded SiGe Epitaxial Layer
[0035] 18 Foreign particles DETAILED DESCRIPTION
[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] See also Figures 1 to 6It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0038] Epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate. Epitaxial process is widely used in semiconductor manufacturing, such as epitaxial silicon wafers in the integrated circuit industry. At present, with the continuous reduction of the feature size of semiconductor devices, especially when CMOS technology enters a smaller node, stress channel transistors have emerged. By selectively epitaxially forming an in-situ doped embedded epitaxial layer in the source and drain regions of the MOS tube, the uniaxial strain (UniaxialStrain) of the embedded epitaxial layer is used to change the stress in the channel region, thereby improving the mobility of carriers and thus improving the performance of the device. Usually, selective epitaxy is carried out at low temperature. One way to reduce the epitaxial growth temperature is to reduce the pressure in the process, such as ultra-high vacuum chemical vapor deposition (UH / CVD). The selective epitaxial layer formed by ultra-high vacuum chemical vapor deposition generally adopts the CDE (cycled epi etch) method. The entire CDE deposition process consists of multiple cycles, in which each cycle is a deposition-first-then-etch mode. However, the CDE method is prone to growing selective epitaxial residues on the non-set region interface outside the set source and drain region interface, such as Figure 1 As shown, epitaxial residues 16 are generated on the epitaxial shielding layer 13 on the side walls of the gate structure 11 and at the junction of the top of the gate structure and the side wall epitaxial shielding layer 13. The epitaxial residues are generally difficult to remove, which will have a serious impact on the yield of the MOS device.
[0039] Based on this, this embodiment provides a method for preparing an embedded source-drain selective epitaxial layer, the preparation method comprising:
[0040] S1, providing a semiconductor substrate, on which a gate structure and a source / drain region of a MOS tube are formed, and an epitaxial trench is formed in the source / drain region;
[0041] S2, executes the embedded epitaxial process, including: step 1, placing the semiconductor substrate in an epitaxial chamber, and introducing a reaction gas source and an etching gas source into the epitaxial chamber to perform synchronous epitaxial deposition and etching to form a partial embedded epitaxial layer in the epitaxial groove; step 2, introducing an etching gas source into the epitaxial chamber to perform secondary enhanced etching; step 3, repeating steps 1 and 2 until the embedded epitaxial layer reaches a preset thickness.
[0042] In the preparation method of this embodiment, etching is performed while performing the epitaxial deposition of step 1 of the embedded epitaxial process. Based on the homologous growth characteristics of the epitaxial process, the nucleation rate in the source and drain region (i.e., in the epitaxial trench) is much greater than the nucleation rate in the region outside the source and drain region (e.g., the epitaxial shielding layer). Therefore, the epitaxial deposition rate in the source and drain region is much greater than the epitaxial deposition rate outside the source and drain region. Generally, the epitaxial deposition stage includes a stable stage, a low-speed deposition stage, and a high-speed deposition stage. At this time, the etching process performed simultaneously can effectively suppress the particle radius of the epitaxial deposition in the region outside the source and drain region from exceeding the critical nucleation radius, so that at the beginning stage of the epitaxial deposition in the source and drain region, the epitaxial trench can easily enter the stable stage of epitaxy and then enter the low-speed deposition stage. In the high-speed and high-speed deposition stages, the areas outside the source and drain areas (such as the epitaxial shielding layer) have a slow nucleation rate and are continuously etched, and their nucleation centers are continuously etched, so that they cannot grow, and are then completely etched during the secondary enhanced etching process in step 2. Therefore, during the entire embedded epitaxial process, the epitaxial layer in the source and drain areas (i.e., in the epitaxial trenches) can grow stably, while the epitaxial layer in the areas outside the source and drain areas (such as the epitaxial shielding layer) is always in the process of repeatedly forming nucleation centers and then being cleaned by the secondary enhanced etching, thereby achieving the free growth of the epitaxial layer only in the source and drain areas (i.e., in the epitaxial trenches), and the preferential growth mode of no epitaxial residue growth on the non-set area interface outside the source and drain area interface, effectively improving the yield of the MOS device.
[0043] The method for preparing the embedded source-drain selective epitaxial layer of this embodiment is described in detail below with reference to the specific drawings.
[0044] like Figure 2 As shown, firstly, step S1 is performed to provide a semiconductor substrate 10 , on which a gate structure 11 and a source / drain region 12 of a MOS tube are formed, and an epitaxial trench 14 is formed in the source / drain region 12 .
[0045] The semiconductor substrate 10 may be made of any suitable semiconductor material known to those skilled in the art, such as a germanium substrate, a silicon substrate, a silicon on insulator (SOI), a stacked silicon on insulator (SSOI), a III-V compound semiconductor substrate, a germanium on insulator (GOI), a germanium silicon substrate, etc. In this embodiment, a single crystal silicon substrate commonly used in the existing semiconductor field is selected.
[0046] The MOS transistor structure formed in this embodiment is not specifically limited, and can be, for example, a planar transistor, a fin transistor (FinFET), a gate-all-around (GAA) transistor, etc., as long as the source and drain regions on the semiconductor substrate are etched to form epitaxial trenches and deposited to form embedded epitaxial layers during the preparation process. Figure 2 As shown in , the formed MOS transistor is a planar transistor, an epitaxial trench 14 is formed in a semiconductor substrate 10 , and the gate structure 11 is arranged on the semiconductor substrate 10 on one side or both sides of the epitaxial trench 14 .
[0047] It should be noted that the gate structure 11 is a structure generally used in MOS transistors, such as a gate dielectric layer covered with a gate polysilicon layer, and a dielectric protection layer covering the surface of the gate polysilicon layer. In addition, the shape and size of the epitaxial trench 14 can be set according to the channel stress requirements of the transistor. The greater the channel stress requirements, the greater the size of the epitaxial trench 14, including the depth and width, and the trench shape matching the requirements. This is well known in the art and is not excessively limited here.
[0048] As an example, the MOS transistor may be an NMOS or a PMOS.
[0049] As a preferred example, before the epitaxial trench 14 is formed in the source and drain region 12, the method further includes the steps of depositing an epitaxial shielding layer 13 and removing the epitaxial shielding layer 13 on the epitaxial trench 14 where the embedded epitaxial process is to be performed later. The epitaxial shielding layer 13 here mainly plays a protective role for the gate structure 11 during the epitaxial process. Regardless of whether the MOS tube is NMOS or PMOS, as long as the semiconductor substrate 10 is a silicon substrate, the epitaxial shielding layer 13 is preferably selected as a single-layer structure of a silicon nitride layer or a stacked structure of a silicon oxide layer and a silicon nitride layer. This is because in the subsequent epitaxial process, the nucleation rate of the epitaxial layer on the silicon semiconductor substrate is significantly different from the nucleation rate on the silicon nitride.
[0050] On this basis, the process of forming the epitaxial trench 14 is generally as follows: first, the gate structure 11 is formed on the semiconductor substrate 10, and the source and drain regions 12 are defined on both sides of the gate structure 11; then, a layer of epitaxial shielding material layer is deposited on the semiconductor substrate 10, and at this time, the epitaxial shielding material layer covers the entire surface of the semiconductor substrate 10 and the surface and side walls of the gate structure 11; then, the source and drain regions 12 are etched by an etching process, the epitaxial shielding material layer of the source and drain regions 12 is removed, and the semiconductor substrate thereunder is further etched, thereby forming the epitaxial trench 14, and the remaining epitaxial shielding material layer is formed as the epitaxial shielding layer 13. It should be noted that, during this step, the epitaxial shielding material layer on the upper surface of the gate structure 11 may be etched away during the etching process, thereby exposing the dielectric protection layer on the surface of the gate structure 11 (for example, when the gate structure 11 is a polysilicon gate, the dielectric protection layer is a silicon oxide layer), and at this time, the epitaxial shielding layer 13 only covers the side walls of the gate structure 11.
[0051] like Figure 3 As shown, step S2 is then performed to execute the embedded epitaxial process, which includes: step one, placing the semiconductor substrate 10 in an epitaxial chamber, and introducing a reaction gas source and an etching gas source into the epitaxial chamber to perform synchronous epitaxial deposition and etching, that is, epitaxial deposition and etching are performed simultaneously to form an embedded epitaxial layer 15 in the epitaxial groove 14; step two, introducing an etching gas source into the epitaxial chamber to perform secondary enhanced etching; step three, repeating steps one and two until the embedded epitaxial layer 15 reaches a preset thickness, that is, steps one and two constitute a deposition cycle (i.e., cycle), and executing the cycle multiple times until the embedded epitaxial layer 15 reaches a preset thickness, wherein the preset thickness of the embedded epitaxial layer 15 is designed according to actual needs and is not excessively restricted.
[0052] Generally, the epitaxial deposition stage includes a stable stage, a low-speed deposition stage, and a high-speed deposition stage. Based on the homologous growth characteristics of the epitaxial process (i.e., the lattice orientation of the epitaxial layer and the semiconductor substrate 10 is the same or similar), the nucleation rate in the source and drain region (i.e., in the epitaxial trench 14) is much greater than the nucleation rate in the region outside the source and drain region (e.g., the epitaxial shielding layer 13). Therefore, the epitaxial deposition rate in the source and drain region is much greater than the epitaxial deposition rate outside the source and drain region. Thus, the embedded epitaxial layer 15 can continuously transition from the stable stage to the low-speed deposition stage and then to the high-speed deposition stage in the epitaxial trench 14, as shown in FIG. Figure 4As shown, in the epitaxial trench 14, the embedded epitaxial layer 15 gradually enters the low-speed layer 151 from the stable layer 150 and then transfers to the high-speed layer 152; and in the area outside the source and drain region (such as the epitaxial shielding layer 13), since its material is different from that of the epitaxial layer, the lattice difference is large, the nucleation rate is slow, and it is continuously etched during the nucleation process, as its nucleation center is continuously etched, the epitaxial layer in the area outside the source and drain region in step one cannot grow, and the epitaxial layer in the area outside the source and drain region is completely etched by the secondary enhanced etching in step two, so in the entire epitaxial deposition process, the area outside the source and drain region is always in a process of repeatedly forming a nucleation center and then being subjected to secondary enhanced etching, thereby eventually forming an epitaxial layer deposited only in the epitaxial trench 14, and the deposition of the epitaxial layer in the area outside it is completely suppressed.
[0053] It should be noted here that Figure 4 The purpose is to illustrate that the embedded epitaxial layer 15 generally goes through three stages during its formation: a stable layer 150, a low-speed layer 151, and a high-speed layer 152. In fact, the stable layer 150, the low-speed layer 151, and the high-speed layer 152 are of the same material layer, and Figure 4 The thickness of the high-speed layer 152 is set according to actual needs, and generally fills the epitaxial trench 14. The figure is only a schematic diagram. In addition, it should be noted that the definition of the three formation stages is determined by the size of the nucleation radius, which depends on the selection of the epitaxial material.
[0054] As an example, during the embedded epitaxial process, the etching gas source in step one and the etching gas source in step two may be the same or different, but in terms of process control and etching effect, it is better to select the same etching gas source as the etching gas source in step one and the etching gas source in step two.
[0055] As an example, when the MOS tube is an NMOS tube and the semiconductor substrate 10 is a silicon substrate, the embedded epitaxial layer 15 is an n-type doped silicon epitaxial layer or an n-type doped silicon carbide epitaxial layer; when the MOS tube is a PMOS tube and the semiconductor substrate 10 is a silicon substrate, the embedded epitaxial layer 15 is a p-type doped germanium silicon epitaxial layer. Further, in the process of performing the embedded epitaxial process, the etching gas source in step one is preferably a chlorine-containing gas, and the etching gas source in step two is also preferably a chlorine-containing gas, such as chlorine gas, hydrogen chloride gas, etc. The chlorine-containing gas reacts with the epitaxial material to generate gas to achieve the etching effect.
[0056] As a preferred example, when the MOS tube is a PMOS tube, the semiconductor substrate 10 is a silicon substrate, and the embedded epitaxial layer 15 is a p-type doped germanium silicon epitaxial layer, during the embedded epitaxial process, the etching gas in step one and step two is selected as chlorine gas; when performing the embedded epitaxial process, the duration of step one is 8s to 20s, the pressure is 0mtorr to 30mtorr, and the temperature is 480°C to 530°C, including the endpoint values, the duration of step two is 8s to 16s, the pressure is 0mtorr to 30mtorr, and the temperature is The temperature is 480°C to 530°C, including the endpoint value, and a better deposition and etching effect can be achieved. On this basis, preferably, when performing the embedded epitaxial process, the flow rate of the chlorine gas introduced in step 1 is 0.1sccm to 1sccm, including the endpoint value, such as 0.1sccm, 0.3sccm, 0.5sccm, 0.7sccm, 0.9sccm, 1.0sccm, etc., and the flow rate of the chlorine gas introduced in step 2 is 1sccm to 4sccm, including the endpoint value, such as 1sccm, 2sccm, 3sccm, 4sccm, etc. It should be noted here that the reaction gas source used for epitaxially forming the p-type doped germanium silicon epitaxial layer can select a conventional gas source, such as DCS (dichlorosilane), silane, germane, diborane, disilane, etc., and the specific gas source combination method is selected according to actual needs.
[0057] As another preferred example, when the MOS transistor is an NMOS transistor, the semiconductor substrate 10 is a silicon substrate, and the embedded epitaxial layer 15 is an n-type doped silicon epitaxial layer or an n-type doped silicon carbide epitaxial layer, in the embedded epitaxial process, the etching gas in step 1 and step 2 is selected as hydrogen chloride gas. It should be noted that the reaction gas source used for epitaxially forming the n-type doped silicon epitaxial layer or the n-type doped silicon carbide epitaxial layer can be a conventional gas source.
[0058] As an example, when performing an embedded epitaxial process, no matter it is an NMOS tube or a PMOS tube, a carrier gas needs to be introduced into the epitaxial chamber, and the carrier gas is generally selected to be hydrogen or nitrogen.
[0059] As an example, before executing the embedded epitaxial process of step S2, it is also necessary to pre-clean the semiconductor substrate to clean the oxide layer and impurities formed on its surface; in addition, before executing step one of the embedded epitaxial process, it also includes a pre-treatment step of reducing the content of oxygen atoms and carbon atoms on the surface of the semiconductor substrate in the epitaxial chamber. Generally, hydrogen is introduced into the epitaxial chamber to reduce the oxygen atoms and carbon atoms on the surface at high temperature, thereby further improving the cleanliness of the semiconductor substrate surface.
[0060] In order to further demonstrate the effect of the preparation method of this embodiment, two groups of experiments were conducted. Figure 5 and Figure 6 As shown, a silicon nitride epitaxial shielding layer is deposited on the surface of two groups of bare wafers respectively, and one group uses the CDE (cycled etch) method in the prior art to deposit an embedded source-drain selective epitaxial layer on the silicon nitride epitaxial shielding layer to obtain the following Figure 5 Another group uses the embedded epitaxial process of this embodiment to deposit an embedded source-drain selective epitaxial layer on the silicon nitride epitaxial shielding layer, and obtains the following Figure 6 The simulation effect is shown in the figure. Figure 5 and Figure 6 It can be seen that Figure 5 In the example, dense impurity particles 18 appeared on the silicon nitride epitaxial shielding layer, while in Figure 6 No obvious impurity particles were seen on the silicon nitride epitaxial shielding layer. The second group grew embedded source-drain selective epitaxial layers in the source-drain regions on both sides of the gate structures of two groups of planar transistors, respectively. One group used the CDE (cycled epitaxial etch) method in the prior art to grow the embedded source-drain selective epitaxial layers; the other group used the embedded epitaxial process of this embodiment to grow the embedded source-drain selective epitaxial layers. Comparing the two sets of data results, it can be seen that the use of the CDE method in the prior art to grow the embedded source-drain selective epitaxial layers formed obvious epitaxial residues on the side walls of the gate structure, while the use of the embedded epitaxial process of this embodiment to grow the embedded source-drain selective epitaxial layers did not form epitaxial residues on the side walls of the gate structure.
[0061] In summary, the present invention provides a method for preparing an embedded source-drain selective epitaxial layer, wherein the preparation method performs etching while executing the epitaxial deposition of step one of the embedded epitaxial process. Based on the homologous growth characteristics of the epitaxial process, the nucleation rate in the source-drain region (i.e., in the epitaxial trench) is much greater than the nucleation rate in the region outside the source-drain region (e.g., the epitaxial shielding layer), so the epitaxial deposition rate in the source-drain region is much greater than the epitaxial deposition rate outside the source-drain region. Generally, the epitaxial deposition stage includes a stable stage, a low-speed deposition stage, and a high-speed deposition stage, and the etching process performed simultaneously at this time can effectively suppress the particle radius of the epitaxial deposition in the region outside the source-drain region from exceeding the critical nucleation radius, so that at the beginning stage of the epitaxial deposition in the source-drain region, it is easy to enter the epitaxial trench. The stable stage of epitaxy then enters the low-speed and high-speed deposition stages, and the area outside the source and drain area (such as the epitaxial shielding layer) has a slow nucleation rate and is continuously etched, and its nucleation center is continuously etched, so that it cannot grow, and then is completely etched during the secondary enhanced etching process of step 2. Therefore, the epitaxial layer in the source and drain area (i.e., in the epitaxial trench) can grow stably during the entire embedded epitaxial process, and the epitaxial layer in the area outside the source and drain area (such as the epitaxial shielding layer) is always in the process of repeatedly forming a nucleation center and then being cleaned by the secondary enhanced etching, thereby realizing the free growth of the epitaxial layer only in the source and drain area (i.e., in the epitaxial trench), and the preferential growth mode of the growth of no epitaxial residue on the interface of the non-set area outside the source and drain area interface, effectively improving the yield of the MOS device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0062] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing an embedded source-drain selective epitaxial layer, characterized in that: The preparation method comprises: Providing a semiconductor substrate, on which a gate structure and a source / drain region of a MOS tube are formed, and an epitaxial trench is formed in the source / drain region; The embedded epitaxial process is performed, comprising: step 1, placing the semiconductor substrate in an epitaxial chamber, and introducing a reaction gas source and an etching gas source into the epitaxial chamber to perform synchronous epitaxial deposition and etching, so as to form a partially embedded epitaxial layer in the epitaxial trench; step 2, introducing an etching gas source into the epitaxial chamber to perform secondary enhanced etching; Step 3, repeating steps 1 and 2 until the embedded epitaxial layer reaches a preset thickness.
2. The method for preparing an embedded source-drain selective epitaxial layer according to claim 1, characterized in that: Before the epitaxial trenches are formed in the source and drain regions, the method further includes the steps of depositing an epitaxial shielding layer and removing the epitaxial shielding layer on the epitaxial trenches where the embedded epitaxial process is to be performed.
3. The method for preparing an embedded source-drain selective epitaxial layer according to claim 1, characterized in that: The MOS tube is an NMOS tube or a PMOS tube, and the epitaxial shielding layer is a single-layer structure of a silicon nitride layer or a stacked-layer structure of a silicon oxide layer and a silicon nitride layer.
4. The method for preparing an embedded source-drain selective epitaxial layer according to claim 3, characterized in that: When the MOS tube is an NMOS tube, the embedded epitaxial layer is an n-type doped silicon epitaxial layer or an n-type doped silicon carbide epitaxial layer; When the MOS tube is a PMOS tube, the embedded epitaxial layer is a p-type doped silicon germanium epitaxial layer.
5. The method for preparing an embedded source-drain selective epitaxial layer according to claim 4, characterized in that: In the process of performing the embedded epitaxial growth process, the etching gas source in step one is a chlorine-containing gas, and the etching gas source in step two is a chlorine-containing gas.
6. The method for preparing an embedded source-drain selective epitaxial layer according to claim 5, characterized in that: When the embedded epitaxial layer is a p-type doped germanium silicon epitaxial layer: the etching gas sources in step one and step two are both chlorine; when performing the embedded epitaxial process, the duration of step one is 8s to 20s, the pressure is 0mtorr to 30mtorr, and the temperature is 480℃ to 530℃, including endpoint values; the duration of step two is 8s to 16s, the pressure is 0mtorr to 30mtorr, and the temperature is 480℃ to 530℃, including endpoint values.
7. The method for preparing an embedded source-drain selective epitaxial layer according to claim 6, characterized in that: When performing the embedded epitaxial process, the flow rate of the chlorine gas introduced in step one is 0.1 sccm to 1 sccm, and the flow rate of the chlorine gas introduced in step two is 1 sccm to 4 sccm, including end points.
8. The method for preparing an embedded source-drain selective epitaxial layer according to claim 5, characterized in that: When the embedded epitaxial layer is an n-type doped silicon epitaxial layer or an n-type doped silicon carbide epitaxial layer: the etching gas sources in step 1 and step 2 are both hydrogen chloride gas.
9. The method for preparing an embedded source-drain selective epitaxial layer according to claim 1, characterized in that: Before performing the embedded epitaxial process, the method further includes pre-cleaning the semiconductor substrate to clean the oxide layer and impurities on the surface; Before performing step 1 of the embedded epitaxial process, a pretreatment step of reducing the content of oxygen atoms and carbon atoms on the surface of the semiconductor substrate in the epitaxial chamber is also included.
10. The method for preparing an embedded source-drain selective epitaxial layer according to claim 1, characterized in that: When the embedded epitaxial growth process is performed, a carrier gas is introduced into the epitaxial growth chamber in step 1 and step 2, and the carrier gas is hydrogen or nitrogen.